Sr. Engineer, Performance Infrastructure

Tenstorrent · Semiconductors · Austin, TX · RISC V

The role focuses on CPU design infrastructure for performance analysis, correlation, and verification, working with RISC-V ISA and collaborating with core architects and RTL teams to deliver efficient and performant designs. It involves enhancing the design environment, tools, and methodologies, and optimizing power, performance, and area.

What you'd actually do

  1. Join a team driving improvements in CPU microarchitecture, verify performance and correlate with the RTL.
  2. Enhance design environment, tools, and methodologies to improve development efficiency.
  3. Collaborate closely with RTL engineers and core architects to meet performance goals, debug miscorrelation and verify performance features.
  4. Use innovative techniques to optimize power, performance, and area while driving performance experiments and evaluating results.

Skills

Required

  • C++
  • Python
  • debugging RTL/logic
  • CPU architecture and microarchitecture

Nice to have

  • infrastructure
  • methodology
  • performance verification
  • compilation tools
  • simulation tools
  • emulation tools

What the JD emphasized

  • requires access to technology that requires a U.S. export license
  • contingent upon the applicant being eligible to access U.S. export-controlled technology
  • contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency