Sr. Engineer, Rtl Implementation

Tenstorrent Tenstorrent · Semiconductors · Austin, TX · RISC V

This role is for a Sr. Engineer, RTL Implementation focused on CPU design using RISC-V ISA. The engineer will work on front-end CAD flows, collaborate with micro-architects to optimize PPA, and work with DV, PD, RTL, and performance teams to deliver a converged design. The role involves synthesis, place and route, and enhancing physical design methodologies.

What you'd actually do

  1. Perform synthesis and initial place and route for new and legacy designs.
  2. Collaborate closely with core micro-architects to optimize core configurations for best PPA.
  3. Use innovative techniques to optimize power, performance, and area while driving physical design experiments and evaluating results.
  4. Enhance physical design environment, tools, and methodologies to improve development efficiency.

Skills

Required

  • RTL coding (Verilog/VHDL)
  • Synthesis
  • Place and route tools
  • Physical design methodology
  • CPU micro-architecture

Nice to have

  • Simulation tools
  • Power analysis tools

What the JD emphasized

  • Experienced in high-performance physical design.
  • Proficient in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation and power analysis.
  • Skilled in synthesis, place and route tools including flows and physical design methodology.
  • Background in CPU micro-architecture.
  • This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology.