Top Level Physical Design Engineer

Tenstorrent Tenstorrent · Semiconductors · Austin, Fort Collins +1 · Advanced Physical Design

This role focuses on the physical design of AI and CPU System-on-Chip (SOC) designs, including floorplanning, power grids, and clock networks, to ensure chip-level closure. It involves collaboration with cross-disciplinary teams and optimization for power, performance, and area.

What you'd actually do

  1. Drive top-level implementation of our complex AI and CPU System-on-Chip designs.
  2. Orchestrate cross-disciplinary collaboration, implementing sophisticated floorplans, power grids, and clock networks while ensuring design closure at the chip level.
  3. Manage the complexity of full-chip physical design and deliver next-generation AI hardware.
  4. Implement cutting-edge AI accelerators and high-performance CPUs at the SOC level.
  5. Drive successful chip-level closure through effective cross-functional collaboration.

Skills

Required

  • Top-level SOC physical design experience
  • Hierarchical floorplanning
  • Fabric implementation
  • Power grid design
  • Global clock distribution
  • Bump planning
  • RDL implementation
  • Multi-voltage domain designs
  • Timing closure
  • EM/IR analysis
  • Physical verification

Nice to have

  • Collaboration with architecture, RTL, and packaging teams
  • Chiplet integration
  • Next-generation packaging co-design

What the JD emphasized

  • 8+ years of top-level SOC physical design experience on complex, multi-million gate designs.
  • Deep expertise in hierarchical floorplanning, fabric implementation, power grid design, and global clock distribution.
  • Mastery of timing closure, EM/IR analysis, and physical verification at the chip level.