Senior Research Engineer focused on optimizing Gemini Robotics models for low-latency on-device inference, driving alignment between model architectures and edge device constraints, and influencing research and engineering teams for robust solutions. Requires deep knowledge of inference techniques across GPU, TPU, and CPU architectures.

This role focuses on defining and driving the power architecture roadmap for Google's next-generation TPUs, which are AI/ML hardware accelerators. The architect will bridge the gap between high-level concepts and silicon execution, optimizing for performance-per-watt for ML workloads and ensuring successful implementation of power management features. This involves collaboration with various teams, including SOC implementation, hardware/software validation, and data center operations, to align silicon capabilities with system-level power constraints. The role requires deep expertise in computer chip design, performance analysis, and power analysis, with a strong emphasis on machine learning accelerator architecture and workload characterization for power optimization.