Currently tracking 22 active AI roles, down 23% versus the prior 4 weeks. Primary focus: Serve · Engineering. Salary range $100k–$500k (avg $300k).
| Title | Stage | AI score |
|---|---|---|
| System IP & Site Lead India Tenstorrent is seeking a System IP & Site Lead in India to manage the technical direction of their System IP portfolio and oversee the operational success, cultural health, and strategic growth of their India engineering design center. This role requires deep technical expertise in SoC architecture and System IP development, strategic business acumen, and proven experience in managing large-scale cross-functional engineering teams and engineering sites. | — | 0 |
| Business Development Lead, India Business Development Lead for Tenstorrent's sovereign AI strategy in India, focusing on identifying opportunities, managing client relationships, and supporting go-to-market execution. Requires experience in the AI hardware/software market and strong client relationships in India. | — | 0 |
| Sr. Staff Engineer, Post-Silicon Validation This role focuses on post-silicon validation of RISC-V based SoCs, involving bring-up, validation, and debug. It requires hands-on lab experience and understanding of SoC architectures, working closely with design, firmware, and software teams. |
| — |
| 0 |
| Staff Engineer Design Verification Seeking a Design Verification Engineer to join the RISC-V CPU team, responsible for block-level verification of high-performance Cache and Coherence units using UVM environments. | — | 0 |
| Sr.Staff, Design Verification - CPU Cluster / SoC Tenstorrent is seeking a Sr. Staff Design Verification Engineer to architect, develop, and evolve verification infrastructure for high-performance RISC-V CPU clusters and SoCs. The role involves building robust verification environments using SystemVerilog and UVM, integrating multiple IPs, and ensuring correct behavior at the cluster or SoC level. Familiarity with AXI/CHI protocols and system IPs is required. | — | 0 |
| Staff, Design for Test Engineer (DFT) Tenstorrent is seeking a Staff Design for Test (DFT) Engineer for their high-performance AI/ML architectures. The role involves RTL implementation, ATPG, test coverage analysis, JTAG, scan compression, ASST, gate-level simulation, silicon bring-up support, MBIST, and DFx flow development for ASIC designs. Experience with finFET technologies and industry-standard DFx tools is required. | — | 0 |