Tenstorrent
Semiconductors · RISC-V AI chip (Jim Keller)
- HQ
- Toronto, CA
- Founded
- 2016
- Website
- tenstorrent.com
Currently tracking 22 active AI roles, down 50% versus the prior 4 weeks. Primary focus: Serve · Engineering. Salary range $100k–$500k (avg $300k).
Semiconductors · RISC-V AI chip (Jim Keller)
Tenstorrent currently has 27 active AI-related job listings, with a significant majority, 81%, focused on serving infrastructure. Engineering roles comprise all of their AI hiring. The company is primarily hiring in the United States and Canada. Frequent technical tags include model_serving, inference_infra, and agent_orchestration, suggesting a focus on AI model deployment and management. In the last 30 days, Tenstorrent has not posted any new AI roles, representing a 100% decrease compared to the previous 30-day period.
Tenstorrent currently has 25 active AI-related roles in our index. The most common open titles are: Sr. Engineer, Software - AI Compiler (2), AI/ML Physical Design Flow Engineer, C++ Machine Learning Engineer, Models Training, Design Verification Lead, AI Hardware , Infrastructure and Platform Development Engineer. Most positions are in Engineering and Research.
Tenstorrent's active AI hiring is concentrated in: serving infrastructure (80%), agents (8%), application (4%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
Tenstorrent is hiring AI talent in: United States (10 roles), Canada (8 roles), Serbia (4 roles), Poland (2 roles).
Job postings at Tenstorrent most frequently reference: inference infra, model serving, fine tuning, agent orchestration, vision.
In the past 30 days, Tenstorrent has posted 1 new AI-related role.
| Title | Stage | AI score |
|---|---|---|
| Software Architect, Automotive Robotics Software Architect role focused on defining and developing software stacks for automotive (ADAS, IVI) and robotics applications, particularly for RISC-V based heterogeneous edge computing environments. The role involves working across software development teams, customers, and partners to define software strategy and enable adoption of RISC-V architecture. Experience with ISO26262, IEC61508, and ASPICE is mentioned. | — | 0 |
| Munich Site Manager Site Lead for Tenstorrent's Munich engineering hub, responsible for program planning and execution of silicon and platform initiatives, bridging German engineering with global priorities, and fostering innovation. | — | 0 |
| SOC Architect Tenstorrent is seeking an SOC Architect to design central compute chiplets for next-generation automotive SoCs. This role involves translating automotive and safety requirements into architecture, focusing on performance, power, and reliability. The position requires a systems mindset and experience with SoC architecture, interconnects, memory, and CPUs, with familiarity in functional safety (ISO 26262) and automotive-grade design challenges. |
| — |
| 0 |
| Sr. Staff Design Verification Engineer, Automotive Robotics Sr. Staff Design Verification Engineer for Tenstorrent, focusing on digital designs for AI accelerators and RISC-V CPUs in an automotive robotics context. The role involves leading verification strategy, building test environments, and mentoring engineers, with a strong emphasis on SystemVerilog and UVM. | — | 0 |
| Emulation Engineer, Automotive Robotics Tenstorrent is seeking an Emulation Engineer to build and scale emulation platforms for their SiP-based AI or ML engines. This role involves architecting and developing emulation environments, testbenches, and support systems to enable hardware, software, and architectural validation, with a focus on silicon debug, DV, and performance. | — | 0 |
| DFT Engineer, Automotive Robotics DFT Engineer for Automotive Robotics team, focusing on designing and delivering core hardware modules for next-generation chiplet-based SoCs. The role involves defining DFx strategy, ensuring aggressive performance, quality, and safety targets are met, and collaborating with silicon design, DFT, OSAT partners, and customers. Experience with ATPG, DFx insertion tools, RTL coding for DFx logic, and fault models is required. Exposure to post-silicon testing and fault campaigns is a plus. The role will involve learning about SiP production, chiplet integration, and balancing architecture, DFT, and test costs. | — | 0 |