Tesla

Software Engineer role focused on designing and developing the AI inference stack, including compilers and runtimes, for neural networks powering Tesla's vehicles and Optimus robot. The role involves optimizing performance on custom hardware and collaborating with AI and hardware engineers.

Software Engineer role focused on developing and maintaining a compiler toolchain and runtime for Tesla's custom AI hardware accelerators, specifically for pre-silicon development of Autopilot and Optimus robot AI models. The role involves optimizing neural network compilation and inference stack performance, designing DSLs, and backend code generation using MLIR/LLVM.

This role focuses on optimizing and deploying ML models for Tesla's Optimus humanoid robots. The engineer will work on model optimization (latency, memory, speed), quantization, pruning, conversion to various formats, benchmarking, packaging, and deploying models as services. They will also implement CI/CD pipelines for ML models and ensure scalability and reliability in production environments, ultimately shipping models to thousands of robots.

Senior Power Optimization Engineer for AI Hardware at Tesla, focusing on RTL-stage power analysis and optimization for next-generation inferencing chips. The role involves using EDA tools to reduce power consumption through techniques like clock-gating refinement and datapath rebalancing, influencing architectural decisions, and collaborating with various design teams to achieve system-level power reductions for AI accelerators.

This role focuses on building pre-silicon development tools, including functional simulators and testing environments, for in-house AI silicon (AI6 and Dojo 3) used in autonomy projects. The engineer will develop algorithms for analysis tools, debug issues on parallel systems, and collaborate with hardware and software teams to improve reliability.

Technical Program Manager for Tesla's AI Hardware team, focusing on the end-to-end silicon development cycle for AI inference chips and custom supercomputer systems (Dojo) used for training neural networks for FSD and Optimus robot. The role involves managing cross-functional teams through component design, verification, physical design, integration, bring-up, validation, and production ramp-up.

Internship role focused on developing and bringing up system software for AI platforms in embedded systems for Tesla's autonomous vehicles and humanoid robots. Responsibilities include RTOS bring-up, C code delivery, and developing Linux device drivers for AI hardware accelerators and sensors.

The AI Hardware team is seeking a SOC Verification Engineer to focus on pre-silicon RTL verification of AI inference chips and custom silicon for Tesla's AI initiatives, including Dojo, FSD, and Optimus. The role involves architecting verification environments, ensuring coverage, and collaborating with design and software teams. Experience with SOC architecture, verification methodologies, and post-silicon validation is required.

This role focuses on integrating and optimizing ML models for real-time inference within robotic systems, requiring strong C++ and Python programming skills, and experience with embedded systems and performance optimization for neural networks.

This role is for a Staff DFT Architecture & RTL Engineer focused on designing and implementing test structures for AI inference chips and custom AI accelerators used in Tesla's AI hardware, including the Dojo supercomputer. The role involves defining DFT architecture, RTL insertion, and leveraging agentic AI flows for automation, contributing to the hardware that powers FSD and Optimus.

The role focuses on building and scaling the inference infrastructure for AI models on custom AI hardware. This includes owning the AI inference cluster, developing job scheduling and cluster management systems, designing inference pipelines for validation and deployment, and creating developer tooling for model validation and debugging. The position requires strong backend engineering fundamentals, experience with hardware accelerator infrastructure, and familiarity with ML inference workloads.