Tenstorrent
Semiconductors · RISC-V AI chip (Jim Keller)
- HQ
- Toronto, CA
- Founded
- 2016
- Website
- tenstorrent.com
Semiconductors · RISC-V AI chip (Jim Keller)
Tenstorrent currently has 27 active AI-related job listings, with a significant majority, 81%, focused on serving infrastructure. Engineering roles comprise all of their AI hiring. The company is primarily hiring in the United States and Canada. Frequent technical tags include model_serving, inference_infra, and agent_orchestration, suggesting a focus on AI model deployment and management. In the last 30 days, Tenstorrent has not posted any new AI roles, representing a 100% decrease compared to the previous 30-day period.
Currently tracking 22 active AI roles, down 42% versus the prior 4 weeks. Primary focus: Serve · Engineering. Salary range $100k–$500k (avg $300k).
Tenstorrent currently has 25 active AI-related roles in our index. The most common open titles are: Sr. Engineer, Software - AI Compiler (2), AI/ML Physical Design Flow Engineer, C++ Machine Learning Engineer, Models Training, Design Verification Lead, AI Hardware , Infrastructure and Platform Development Engineer. Most positions are in Engineering and Research.
Tenstorrent's active AI hiring is concentrated in: serving infrastructure (80%), agents (8%), application (4%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
Tenstorrent is hiring AI talent in: United States (10 roles), Canada (8 roles), Serbia (4 roles), Poland (2 roles).
Job postings at Tenstorrent most frequently reference: inference infra, model serving, fine tuning, agent orchestration, vision.
In the past 30 days, Tenstorrent has posted 1 new AI-related role.
| Title | Stage | AI score |
|---|---|---|
| System IP RTL Design Lead Tenstorrent is seeking an experienced System IP RTL Design Lead to drive the definition and implementation of complex datacenter class IP for their next-generation semiconductor products. The role involves leading a design team, defining system-level requirements, and ensuring IP design sign-off. The company is focused on AI technology and developing high-performance RISC-V CPUs and AI platforms. | — | 0 |
| Sr. Engineer, Design Verification,System IP Senior Design Verification Engineer responsible for end-to-end verification of IOMMU IP, ensuring functional correctness and performance. Involves test planning, coverage closure, and debugging complex issues within ASIC/SoC verification using SystemVerilog and UVM. Familiarity with bus protocols and scripting for automation is required. | — | 0 |
| Staff Engineer, CPU Core Verification Tenstorrent is seeking a Staff Engineer for CPU Core Verification to own CPU core-level verification and shape how out-of-order RISC-V CPUs behave in silicon. Responsibilities include planning and driving functional verification, developing stimulus and coverage, debugging regressions, and collaborating with cross-functional teams. |
| — |
| 0 |
| System IP & Site Lead India Tenstorrent is seeking a System IP & Site Lead in India to manage the technical direction of their System IP portfolio and oversee the operational success, cultural health, and strategic growth of their India engineering design center. This role requires deep technical expertise in SoC architecture and System IP development, strategic business acumen, and proven experience in managing large-scale cross-functional engineering teams and engineering sites. | — | 0 |
| Sr.Staff, Design Verification - CPU Cluster / SoC Tenstorrent is seeking a Sr. Staff Design Verification Engineer to architect, develop, and evolve verification infrastructure for high-performance RISC-V CPU clusters and SoCs. The role involves building robust verification environments using SystemVerilog and UVM, integrating multiple IPs, and ensuring correct behavior at the cluster or SoC level. Familiarity with AXI/CHI protocols and system IPs is required. | — | 0 |
| Staff, Design for Test Engineer (DFT) Tenstorrent is seeking a Staff Design for Test (DFT) Engineer for their high-performance AI/ML architectures. The role involves RTL implementation, ATPG, test coverage analysis, JTAG, scan compression, ASST, gate-level simulation, silicon bring-up support, MBIST, and DFx flow development for ASIC designs. Experience with finFET technologies and industry-standard DFx tools is required. | — | 0 |