Currently tracking 440 active AI roles, down 53% versus the prior 4 weeks. Primary focus: Serve · Engineering. Salary range $100k–$575k (avg $262k).
NVIDIA currently has 496 active AI-related job listings. The majority of these roles, 52%, are focused on serving infrastructure, with agents representing another significant segment at 23%. Engineering is the dominant function, with 441 positions. The United States leads hiring geographies with 287 roles, followed by China with 64. Frequent tech tags include model_serving, inference_infra, and agent_orchestration, suggesting a focus on deployment and management of AI models. Over the last 30 days, NVIDIA posted 214 new AI roles, a 27% decrease compared to the previous 30-day period.
NVIDIA currently has 487 active AI-related roles in our index. The most common open titles are: Deep Learning Performance Architect (4), Senior Deep Learning Performance Architect (4), AI Research Scientist (3), Developer Technology Engineer - AI (3), Manager, Deep Learning Algorithms (3). Most positions are in Engineering and Research.
NVIDIA's active AI hiring is concentrated in: serving infrastructure (54%), agents (21%), application (8%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
NVIDIA is hiring AI talent in: United States (286 roles), China (59 roles), Israel (50 roles), Germany (21 roles).
Job postings at NVIDIA most frequently reference: model serving, inference infra, agent orchestration, llm observability, multimodal.
In the past 30 days, NVIDIA has posted 110 new AI-related roles. That is a -50% change versus the prior 30 days (218 → 110).
| Title | Stage | AI score |
|---|---|---|
| Senior System Design Engineer NVIDIA is seeking a Senior System Design Engineer to work on GPU/Tegra based products for various applications including automotive, robotics, and industrial PCs. The role involves reviewing board designs, collaborating with cross-functional teams, optimizing circuits for performance and cost, and participating in product release documentation. Requires 10+ years of board design experience and strong analytical skills. | — | 0 |
| Formal Verification Manager Lead a team of formal verification engineers responsible for verifying next-generation NVIDIA Networking products and GPU technologies, ensuring design correctness at the highest level for complex digital designs. | — | 0 |
| Principal Formal Verification Engineer Principal Formal Verification Engineer to join NVIDIA Networking team, responsible for shaping the formal strategy and execution of complex, high-performance silicon designs for data centers, AI infrastructure, networking, and storage systems. Requires deep hands-on experience and strong execution mindset in applying formal methods to validate designs. |
| — |
| 0 |
| Manager, Hardware and System Development Engineering Manager for Hardware and System Development Engineering at NVIDIA, focusing on creating and optimizing test and validation platforms for high-performance networking products. The role involves leading hardware lifecycle, collaborating with cross-functional teams, and driving technical execution. | — | 0 |
| Senior Site Reliability Engineer, HPC and LSF NVIDIA is seeking a Senior Site Reliability Engineer to manage and operate large-scale compute clusters that power silicon development. The role involves automating deployments, managing workload schedulers, troubleshooting complex issues, and optimizing system performance and reliability. The engineer will collaborate with domain experts to improve infrastructure utilization and contribute to faster time-to-market for new chips. | — | 0 |
| DFT Change Analyst NVIDIA is seeking a Hardware Engineer to lead Change Impact Analysis for engineering design changes (ECOs/ECRs) on networking and computing platforms. The role involves collaborating with cross-functional teams to evaluate impacts on hardware, mechanical design, system performance, and test coverage, ensuring product quality and integrity. | — | 0 |
| Senior System Test Design Engineer Senior System Test Design Engineer for NVIDIA's networking product engineering team. This role involves designing and developing automated tests for networking switches, collaborating with HW, ASIC, and SW Engineering teams to ensure product quality and high availability. Responsibilities include defining and developing tests from development to final production, and working with manufacturing teams to improve yields, coverage, and capacity. | — | 0 |
| Senior Package Engineer NVIDIA is seeking a Senior Package Engineer to join their team. The role involves collaborating with design and program teams on the development of sophisticated IC substrates for groundbreaking products, working closely with SI, layout, and ASIC design teams to develop complex ASIC packages. Responsibilities include planning schedules, resolving costs, and addressing packaging, manufacturing, and electrical design issues. The ideal candidate will have 10+ years of experience, including at least 5 years with complex ASIC package development and manufacturing, and experience with subcontractors and vendors. | — | 0 |
| Senior Design Verification Engineer - PCIE Senior Design Verification Engineer for PCI Express controllers used in GPUs, SOCs, and DPUs. Requires expertise in verification methodologies like UVM and Specman/e, and knowledge of industry standard protocols. | — | 0 |
| Senior Design Verification Engineer, Chip Design Senior Design Verification Engineer responsible for verifying portions of a high performance and low power chip, focusing on micro-architectural understanding, verification environment coding, and logic debug. The role involves crafting and delivering verification components and ensuring the quality of Chip Design related logic. | — | 0 |
| System Software Engineer - OpenBMC System Software Engineer role focused on designing and implementing OpenBMC Core Infrastructure and Features for GPU Server platforms. Responsibilities include BMC firmware bring-up, performance analysis, developing manageability features, contributing to the OpenSource community, and ensuring code quality and security. Requires expertise in BMC firmware development, board bring-up, system management standards, and strong programming skills in C/C++, Bash, Python, Go. | — | 0 |
| Senior Software and System Architect Senior Software and System Architect role at NVIDIA focusing on cloud networking, security, virtualization, and orchestration for DPUs & NICs. The role involves researching new technologies, defining architecture for next-generation hardware, and building end-to-end solutions from application to hardware level. It requires strong C/Python development skills, Linux, Docker, and deep knowledge of data center networking. | — | 0 |
| Manager, IC Reliability Labs Manager for an IC Reliability Lab at NVIDIA, responsible for leading lab activities, managing a team of operators and engineers, and overseeing various types of IC testing, equipment maintenance, and lab processes. | — | 0 |
| Senior ASIC Architect NVIDIA is seeking a Senior ASIC Architect for its switch division. This role involves defining the architecture of next-generation switch product lines, focusing on performance for Ethernet and InfiniBand. The position requires cross-disciplinary collaboration with software, ASIC design, verification, physical design, and platform teams to improve performance and debug complex issues. The ideal candidate will have 5+ years of experience in ASIC design/uarch/arch/performance and strong analytical and debug skills. | — | 0 |
| Senior Verification Engineer, Memory Subsystem Senior Verification Engineer role focused on verifying the ASIC design, architecture, and micro-architecture of the GPU memory subsystem using advanced verification methodologies. Responsibilities include defining verification scope, developing infrastructure, and ensuring correctness through functional coverage and performance verification. | — | 0 |
| Senior Physical Design Backend Engineer NVIDIA is seeking a Senior Physical Design Backend Engineer to join their Networking Silicon Engineering team. The role involves designing high-speed communication devices, focusing on power, area, and performance constraints. Responsibilities include RTL2GDS flows, synthesis, place and route, timing closure, power/noise analysis, and physical verification. Requires 5+ years of experience in physical design and familiarity with EDA tools. | — | 0 |
| Verification Engineer, Low Power NVIDIA is seeking a Verification Engineer focused on the low power aspects of their chips. The role involves developing test plans, writing test cases, and collaborating with various teams to ensure the functional, electrical, and performance aspects of low power features are verified, both in pre- and post-silicon stages. | — | 0 |
| Senior SRAM Circuit Design Engineer NVIDIA is seeking a Senior SRAM Circuit Design Engineer to develop sophisticated SRAM compilers and explore future process nodes. Responsibilities include transistor-level circuit design, supervising layout, verification, debug, and automating the assembly and validation of SRAM macros. The role also involves collaborating with SOC design, silicon test, and productization teams. | — | 0 |
| Senior IP DV Engineer - NOC IP Senior Verification Engineer to verify the design and implementation of memory subsystem units for GPUs and SOCs, impacting product lines from consumer graphics to self-driving cars and AI. Responsibilities include defining verification scope, developing infrastructure, and ensuring correctness using advanced methodologies like SV/UVM. | — | 0 |
| Senior PHY System Engineer NVIDIA is seeking a Senior PHY System Engineer to join their Post-silicon department, focusing on the End-to-End physical-layer performance characterization, verification, and debugging of NVIDIA systems, including ASICs and Electro-Optical/Electrical chips and systems. The role involves silicon bring-up, lab measurements with various equipment, and leading data-driven discussions for product improvement and mass production. | — | 0 |
| Senior Verification Engineer, PCIE Senior Verification Engineer for PCI Express controllers in GPUs and SOCs, focusing on ASIC design verification using UVM and SystemVerilog. | — | 0 |
| Senior Verification Engineer, PCIE Senior Verification Engineer to verify the design and implementation of PCI Express controllers for GPUs and SOCs, using UVM and Verilog/SystemVerilog. | — | 0 |
| Senior Formal Verification Engineer Senior Formal Verification Engineer at NVIDIA, focusing on pre-silicon design and verification of NIC technologies using state-of-the-art formal verification tools and methodologies to prove design correctness. | — | 0 |
| Senior DevOps Engineer Seeking a Senior DevOps Engineer with extensive hardware and IT infrastructure knowledge to research, create, and handle automated build and deployment processes for Storage solutions. The role involves maintaining bare-metal infrastructure, driving CI/CD improvements, and participating in the development, integration, verification, and performance during R&D on next-generation Storage solutions. | — | 0 |
| Senior Chip Design Engineer Senior Chip Design Engineer at NVIDIA, focusing on the verification of state-of-the-art Switch Silicon chips for high-speed communication devices. The role involves planning and executing dynamic verification environments, integrating and verifying the Switch at the system level, and driving FullChip verification execution. | — | 0 |
| Senior Chip Design RTL Engineer Senior Chip Design Engineer to join our Switch Silicon team. Design and implement the next generation state-of-the-art Switch Silicon chips. Develop industry's best high-speed communication devices, delivering the highest throughput and lowest latency! | — | 0 |
| Senior Chip Design Verification Engineer Senior Chip Design Verification Engineer at NVIDIA, focusing on networking silicon for high-speed communication devices. Responsibilities include building reference models, verifying and simulating chip blocks, and collaborating with cross-functional teams. Requires 5+ years of RTL Frontend ASIC Design or Verification experience. | — | 0 |
| Senior SRAM Circuit Design Engineer Senior SRAM Circuit Design Engineer at NVIDIA, focusing on transistor-level circuit design, SRAM compiler development, and advanced process node exploration for high-performance chips. Requires 5+ years of SRAM design experience and Python scripting. | — | 0 |
| Senior SRAM Circuit Design Engineer NVIDIA is seeking a Senior SRAM Circuit Design Engineer to develop sophisticated SRAM compilers and design SRAM macros for their chips. The role involves transistor-level circuit design, layout supervision, verification, and automation of SRAM assembly and validation. The engineer will also explore future process nodes and collaborate with SOC design, silicon test, and productization teams. | — | 0 |
| Senior SRAM Circuit Design Engineer Senior SRAM Circuit Design Engineer at NVIDIA, focusing on transistor-level circuit design, SRAM compiler development, and advanced process node exploration for high-performance chips. Requires 5+ years of SRAM design experience and Python scripting. | — | 0 |
| Senior SRAM Circuit Design Engineer NVIDIA is seeking a Senior SRAM Circuit Design Engineer to design and optimize custom SRAM circuits for performance-critical IPs like CPUs/GPUs. The role involves full custom circuit design, transistor-level design, verification, and developing advanced flows for timing, EM/IR, and variation tolerance in advanced technology nodes. | — | 0 |
| Senior Analog Layout Design Engineer NVIDIA is looking for a Senior Analog Layout Design Engineer to perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, SerDes, general I/O's, ESD structures designs in state-of-the-art sub-micron CMOS FinFET technologies using Cadence tools. The role involves working with ASIC and mixed-signal engineers to customize designs for integration in VLSI products, including floor planning, custom layout, and verifying against design rules and schematics, and EM/IR analysis. Requires a minimum of 8 years of relevant mask analog layout experience, an Electronics Practical Engineer certificate or B.Sc. in Electrical Engineering, proven understanding of analog circuit layout concepts, expertise with Cadence custom circuit design tools (Virtuoso), and experience with DRC/LVS verification tools. | — | 0 |
| Software Test Development Engineer NVIDIA is seeking a Test Development Engineer to join their networking and interconnect products team. The role involves automation development, test plan creation, execution, and debugging of hardware and software failures. The engineer will also design technical processes, deploy test solutions, and train personnel. Requires a technical degree, 3+ years of experience, and programming skills in Python, Java, C#, or C++. | — | 0 |
| Senior Malware Research Architect NVIDIA is seeking a Senior Malware Research Architect to design and implement advanced malware detection systems using Virtual Machine Introspection (VMI) and file system techniques. The role involves researching, developing, and deploying solutions for next-generation secure networks, focusing on extracting critical security events for threat detection. Requires expertise in memory forensics, operating systems, file systems, and programming in Python and C/C++. | — | 0 |
| Software Engineer, DOCA SDK | — | — |
| Physical Design Backend Engineer | — | — |
| Silicon Power Engineer | — | — |
| Manager, Manufacturing Test Engineering | — | — |
| Principal Software Engineer - Networking Hyperscale Engineering | — | — |
| Senior Manager, Test, Manufacturability, Reliability and Quality | — | — |
| Software R&D Engineer, Digital Logic Synthesis - New College Grad 2026 | — | — |
| Senior Software Manager, AI Networking | — | — |
| System Test Engineer | — | — |
| Implementation Methodology Engineer | — | — |
| System Test Engineer | — | — |
| Senior Compiler Engineer - AI | — | — |
| Director, AI for Tools | — | — |
| Senior Software Engineer, AI Performance Analysis | — | — |
| Senior Research Engineer, OmniDreams and Alpasim | — | — |
| Principal CPU Power Architect | — | — |