Tenstorrent
Semiconductors · RISC-V AI chip (Jim Keller)
- HQ
- Toronto, CA
- Founded
- 2016
- Website
- tenstorrent.com
Currently tracking 22 active AI roles, down 50% versus the prior 4 weeks. Primary focus: Serve · Engineering. Salary range $100k–$500k (avg $300k).
Semiconductors · RISC-V AI chip (Jim Keller)
Tenstorrent currently has 27 active AI-related job listings, with a significant majority, 81%, focused on serving infrastructure. Engineering roles comprise all of their AI hiring. The company is primarily hiring in the United States and Canada. Frequent technical tags include model_serving, inference_infra, and agent_orchestration, suggesting a focus on AI model deployment and management. In the last 30 days, Tenstorrent has not posted any new AI roles, representing a 100% decrease compared to the previous 30-day period.
Tenstorrent currently has 25 active AI-related roles in our index. The most common open titles are: Sr. Engineer, Software - AI Compiler (2), AI/ML Physical Design Flow Engineer, C++ Machine Learning Engineer, Models Training, Design Verification Lead, AI Hardware , Infrastructure and Platform Development Engineer. Most positions are in Engineering and Research.
Tenstorrent's active AI hiring is concentrated in: serving infrastructure (80%), agents (8%), application (4%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
Tenstorrent is hiring AI talent in: United States (10 roles), Canada (8 roles), Serbia (4 roles), Poland (2 roles).
Job postings at Tenstorrent most frequently reference: inference infra, model serving, fine tuning, agent orchestration, vision.
In the past 30 days, Tenstorrent has posted 1 new AI-related role.
| Title | Stage | AI score |
|---|---|---|
| Physical Design Engineer: Die-to-Die Interface (RTL to GDSII) Tenstorrent is seeking a Physical Design Engineer to drive the Die-to-Die (D2D) Physical Implementation from RTL to GDSII for multi-die/chiplet architectures. The role involves full physical design flow, including synthesis, floorplanning, place-and-route, CTS, and sign-off, with a focus on high-speed interfaces. | — | 0 |
| Chiplet Physical Design Engineer Tenstorrent is seeking a Senior Chiplet Physical Design Engineer to design and integrate chiplets into a System-in-Package (SiP) for AI silicon. The role involves synthesis, place-and-route, and timing closure for high-speed CPU cores on advanced process nodes, collaborating with global teams and external partners. | — | 0 |
| Senior Tax Manager Senior Tax Manager responsible for leading all aspects of Tenstorrent’s tax function including federal, state, and international income tax filings, annual audits, sales tax reporting and remittance, and strategic tax planning. This role will report to the VP of Finance and key external partners. |
| — |
| 0 |
| SoC Physical Design Verification Engineer Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes. Responsibilities include leading physical verification closure, debugging issues, and collaborating with cross-functional teams to achieve successful tapeouts. | — | 0 |
| Engineering Program Manager, RISCV Tenstorrent is seeking an Engineering Program Manager to lead their RISC-V CPU team, driving the full lifecycle of high-performance CPUs from spec to tapeout and post-silicon debug. This role involves cross-functional collaboration across architecture, design, verification, and DFT, with a focus on program management, risk management, and milestone delivery. Experience with Functional Safety standards like ISO 26262 is desirable. The role is hybrid and open to various experience levels. | — | 0 |
| Staff Technical Program Manager, Physical Design This role is for a Technical Program Manager with physical design expertise to drive the execution of AI/ML and CPU processor projects. The TPM will lead cross-functional teams, manage complex schedules across multiple chiplets, and interface between internal teams and external partners, focusing on the delivery of next-generation AI silicon. | — | 0 |
| Sr.Staff, Design Verification - CPU Cluster / SoC Tenstorrent is seeking a Sr. Staff Design Verification Engineer to architect, develop, and evolve verification infrastructure for high-performance RISC-V CPU clusters and SoCs. The role involves building robust verification environments using SystemVerilog and UVM, integrating multiple IPs, and ensuring correct behavior at the cluster or SoC level. Familiarity with AXI/CHI protocols and system IPs is required. | — | 0 |
| Sr. Engineer, SoC Design Verification Tenstorrent is seeking a Sr. Engineer, SoC Design Verification to focus on pre-silicon verification of DFD logic in advanced AI SoCs. This role involves developing and owning verification environments, writing and executing test scenarios, analyzing coverage gaps, and debugging failures. The engineer will also automate flows for JTAG/scanchain testing and integrate AI productivity tools. The company emphasizes its cutting-edge AI technology and the need for innovation in semiconductors. | — | 0 |
| Inventory Manager, Supply Chain Inventory Manager responsible for end-to-end visibility, accuracy, and control of company-owned inventory across global locations, partnering with Supply Chain, Manufacturing, Finance, and Quality teams. Requires strong understanding of semiconductor manufacturing, outsourced operations, and ERP systems (SAP S4 HANA). | — | 0 |
| Power Architect Tenstorrent is seeking a Power Architect to drive architectural strategy, modeling, and design decisions for power optimization in their AI compute systems. This role involves predicting and tracking power consumption, proposing architectural changes, building workloads to stress use cases, and correlating pre-silicon estimates to silicon measurements. The position requires extensive experience with power estimation tools and a background in power-optimization of compute datapath and/or interconnects. | — | 0 |
| Staff Physical Design Engineer – EMIR This role focuses on the physical design and EMIR (Electromigration and IR-drop) analysis for high-performance ICs, specifically for AI chips and RISC-V CPUs. The engineer will ensure robust power delivery, signal integrity, and long-term reliability, working with RTL and physical design teams on advanced technology nodes. | — | 0 |
| Physical Design Engineer - STA Tenstorrent is seeking a Timing Engineer to drive static timing analysis and closure for complex, high-performance designs, collaborating with logic, DFT, and physical design teams to ensure chips meet performance targets. | — | 0 |
| CPU Architect, Load-Store CPU Architect role focusing on the load-store unit for high-performance out-of-order RISC-V CPUs, involving design, analysis, and optimization of memory hierarchy and data prefetchers. Collaboration with hardware and software teams is key. | — | 0 |
| Engineer, PCIe Validation This role focuses on validating high-speed interfaces like PCIe for next-generation AI hardware. It involves debugging complex system-level issues across hardware and firmware, collaborating with cross-functional teams, and working with lab equipment. The role is not directly building AI models or systems but is crucial for the underlying hardware infrastructure. | — | 0 |
| Verification Engineer Tenstorrent is seeking a Verification Engineer in Tokyo to ensure the functionality and performance of their System-in-package, which integrates multiple chiplets. The role involves verifying digital IP and SoC logic, building verification infrastructure, creating testbenches, and collaborating with global teams. Experience in CPU or SoC verification and knowledge of Verilog/System Verilog are required. | — | 0 |
| Staff, Design for Test Engineer (DFT) Tenstorrent is seeking a Staff Design for Test (DFT) Engineer for their high-performance AI/ML architectures. The role involves RTL implementation, ATPG, test coverage analysis, JTAG, scan compression, ASST, gate-level simulation, silicon bring-up support, MBIST, and DFx flow development for ASIC designs. Experience with finFET technologies and industry-standard DFx tools is required. | — | 0 |
| Senior DFT Engineer, Architecture Tenstorrent is seeking a Senior DFT Engineer to design and integrate chiplets into a System-in-package, focusing on DFT implementation for high-speed CPU core design. Responsibilities include building chip-level DFT strategies, inserting test features, collaborating with cross-functional teams, scripting EDA tools, and supporting silicon bring-up. | — | 0 |
| Sr Staff Engineer, SoC RTL Design Tenstorrent is seeking a Sr Staff Engineer, SoC RTL Design to define, build, and optimize high-performance IP and SoC architectures for next-gen AI and compute workloads. This role involves RTL development, performance optimization, and collaboration with cross-functional teams in the design of cutting-edge AI semiconductors. | — | 0 |
| Staff Engineer, Physical Design Tenstorrent is seeking a Staff Engineer for Physical Design to implement high-performance CPU and AI/ML architectures. The role involves owning the complete physical design flow from synthesis to tapeout, optimizing for performance, power, and area on advanced process nodes. This is a hybrid role based in Austin, TX, Santa Clara, CA, or Fort Collins, CO. | — | 0 |
| CPU Core Design Verification Test Generator Lead | — | — |
| Technical Program Manager, Architecture | — | — |