Intel
- HQ
- Santa Clara, US
- Founded
- 1968
- Size
- 120,000+
- Website
- intel.com
Intel currently has 84 active job listings related to artificial intelligence. The majority of these roles, 51%, are focused on serving infrastructure, with agents representing another significant portion at 24%. Engineering is the most frequent function for these positions. The company is actively hiring in the United States, China, and Mexico. Frequent technical tags include model serving, inference infrastructure, and agent orchestration. In the last 30 days, Intel has added 73 new AI roles, representing a 52% increase compared to the previous 30-day period.
Currently tracking 56 active AI roles, down 27% versus the prior 4 weeks. Primary focus: Serve · Engineering. Salary range $122k–$414k (avg $253k).
Intel currently has 59 active AI-related roles in our index. The most common open titles are: AI Software Engineering Intern (3), AI Software Engineer Intern (2), GenAI Software Solutions Engineer (2), Graduate Talent (GenAI Software Solutions Engineer) (2), AI Algorithm Engineer. Most positions are in Engineering and Research.
Intel's active AI hiring is concentrated in: serving infrastructure (49%), agents (29%), application (8%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
Intel is hiring AI talent in: United States (28 roles), China (7 roles), Mexico (6 roles), Malaysia (6 roles).
Job postings at Intel most frequently reference: model serving, inference infra, agent orchestration, rag, tool use.
In the past 30 days, Intel has posted 28 new AI-related roles. That is a -63% change versus the prior 30 days (75 → 28).
| Title | Stage | AI score |
|---|---|---|
| Chip Design Team Lead - AI SOC Lead a digital design team developing cutting-edge AI SoCs, focusing on RTL coding, PPA analysis, and cross-functional collaboration for high-end chip design. | Serve | 7 |
| DevOps & Cloud Infrastructure Engineer DevOps & Cloud Infrastructure Engineer to design, implement, and automate cloud-based solutions on the Azure platform. The team builds and provides the infrastructure powering the AI era across all DCG organizations, enabling scalable, secure, and innovative cloud solutions worldwide. Responsibilities include designing and maintaining scalable, secure, and automated cloud infrastructure on Azure, building and optimizing CI/CD pipelines, managing containerized environments, and developing automation scripts. Qualifications include a Bachelor's degree, strong background in IT infrastructure, Azure experience, CI/CD tools, Kubernetes, Docker, Python, and experience with AI tools and technologies. | — |
| 5 |
| Deep Learning System Validation Engineer This role focuses on validating and developing hardware structures and interfaces to accelerate deep learning hardware and software performance for AI systems. It involves developing test plans, leading pre- and post-silicon activities, and collaborating with product and design teams to define next-generation requirements and influence the AI product roadmap. The work impacts AI solutions in both on-device and data center deployments. | Serve | 5 |
| Post Silicon Validation Engineer Intel is seeking a Post Silicon Validation Engineer to ensure the quality and performance of their cutting-edge System-on-Chip (SoC) products. This role involves developing and executing innovative validation methodologies, conducting silicon debug to resolve functional issues, and testing interactions between various SoC features. The engineer will also develop post-silicon validation infrastructure, collaborate with multidisciplinary teams, and create comprehensive validation reports. The position requires experience in post-silicon validation, proficiency with FPGA/emulation tools, and technical expertise in SoC domains like Graphics, PCIe, and Memory. | — | 0 |
| Bluetooth Phy System Student Student role focused on Bluetooth PHY systems, involving pre- and post-silicon system design, RFIC architecture, calibration algorithms, system performance, and multidisciplinary problem-solving across HW, SW, RF, and Modem domains. Requires knowledge of communication systems, modulation, RFIC impairments, and link budgets. | — | 0 |
| Package and PCB Layout Eng Seeking an RF Design Engineer with 6+ years of experience to design, develop, and verify RF integrated circuits and systems, including PCB and Package Layout, for wireless communication products like WLAN and Bluetooth. Responsibilities include defining floorplans, layouts, and physical designs, collaborating with cross-disciplinary teams, and ensuring compliance with design rules and manufacturing constraints. | — | 0 |
| Senior RF Integration Engineer Senior RF Integration Engineer at Intel, responsible for leading integration activities for advanced wireless connectivity silicon, working with RF circuits, developing automation tools in C#, and performing post-silicon validation. Requires B.Sc. in Electrical/Electronic Engineering and 8-12 years of experience in wireless communication systems and RF engineering. | — | 0 |
| Post Silicon Validation Student Student/Intern position in Intel's Silicon and Platform Engineering Group (SPE) in Haifa, Israel. The role involves learning and applying knowledge, building skills, and exploring future career opportunities through hands-on experience and projects. Requires a Bachelor's degree in Electrical/Computer Engineering, strong analytical and problem-solving skills, and the ability to work in unstructured environments and drive new model path finding. | — | 0 |
| PM Validation - student position Student position in Front End Validation Team at Intel, focusing on validating Intel CORE's Power Management flows and key interfaces. The role involves planning and implementing validation strategies, defining and writing test environments for RTL implementation, debugging, and driving features to tape-in quality. Requires a BSc student in Electrical or Computer Engineering with 3-4 semesters until graduation. Basic usage of GenAI tools is a plus. | — | 0 |
| Experienced Security Software development Engineer Experienced Security Software Development Engineer at Intel to validate TDX (Trusted Domain Extensions), a confidential computing technology. The role involves validating across firmware, OS, drivers, middleware, SDKs, and applications, building frameworks, automation, and reference implementations. Requires 5+ years of experience in software/hardware validation or verification and coding in C, C++, or Java. | — | 0 |
| RF Hardware Design Engineer Designs and develops RF hardware systems for WiFi and Bluetooth technologies, involving simulation, board-level design, and lab validation. The role also includes an interest in leveraging AI-based solutions to enhance engineering productivity. | — | 0 |
| DFT Automation and Validation Engineer This role focuses on developing and maintaining validation testing environments and tooling for CPU core DFT (Design for Test) validation. Key responsibilities include automation, scripting, debug tools, and improving team AI skills to support validation engineers. The role requires strong programming skills in TCL, Python, and/or Perl, and experience in pre-silicon validation or CAD/tool automation. | — | 0 |
| Senior Post Silicon CPU Debug Engineer Seeking a Senior CPU Debug Engineer to lead logical debugging of Core CPU designs, collaborate with Architecture and Design teams, and provide customer debug support. Responsibilities include analyzing and resolving complex logic issues, developing debugging tools, and improving debug processes. | — | 0 |
| DFT Engineer Junior Design-for-Test (DFT) Engineer role focused on developing, integrating, and validating DFT solutions for CPU core designs, including ATPG generation, fault coverage analysis, and pattern debug. Responsibilities involve RTL-level DFT implementation, script development for automation, and collaboration with cross-functional teams for silicon bring-up and test flows. | — | 0 |
| Practical Engineering Student - Kiryat Gat Student position in the UPW group focusing on system verification, maintenance, and monitoring of equipment in a semiconductor manufacturing facility. Requires a Practical Engineer degree and proficiency in Excel and Microsoft Office. | — | 0 |
| IT Network Operation Engineer IT Network Operation Engineer responsible for sustaining and operating mission-critical complex manufacturing network infrastructure supporting Intel Foundry environments. Focuses on operational execution, network stability, incident response, and problem analysis for Cisco networks (including ACI) in a 24x7 production environment. | — | 0 |
| Practical Engineering Student for Intel Kiryat Gat Seeking a Practical Engineering student for a semiconductor manufacturing facility to support advanced equipment, learn maintenance and troubleshooting, and collaborate with engineering teams. Role involves hands-on experience in a high-volume, cutting-edge fabrication environment. | — | 0 |
| CPU Structural Design – Technology and Path finding This role focuses on the physical design and process technology for Intel's High Performance Processor (P-Core) CPUs. Responsibilities include synthesis, place and route, timing analysis, power optimization, and developing physical design methodologies using industry EDA tools. | — | 0 |
| CPU Circuit Design Engineer CPU Circuit Design Engineer role at Intel, focusing on designing next-generation CPU cores and SoCs. Responsibilities include detailed circuit analysis, design implementation, and optimization at the transistor level, meeting power, performance, and area targets. Requires BSc/MSc in EE/CE and at least 2 years of VLSI/circuit design experience. | — | 0 |
| CPU power Architect Power management architect for Intel Architecture group, defining state-of-the-art CPU end-to-end power handling, including active and idle power management solutions, and interaction with OS, driver, and platform components. Focus on defining next-generation CPU power management architecture and delivering architectural specifications, initiating, guiding, and coordinating the design of new ideas and products, and driving implementation post-silicon. | — | 0 |
| Static Timing Analysis Engineer Intel is seeking a Static Timing Analysis (STA) Engineer to join their BE Integration team, focusing on the design of future generation high-performance Intel microprocessors. The role involves advanced timing analysis, integration, optimization, and collaboration with cross-functional teams to ensure silicon meets performance requirements, power, frequency, and area targets. The engineer will also contribute to improving physical design methodologies and flow automation. | — | 0 |
| Process Technology Design Engineer Electrical Engineer to drive silicon processes and collaterals for advanced Intel wireless products, working with foundries to deliver next-generation wireless solutions. | — | 0 |
| Senior VLSI Design Engineer Senior VLSI Process Design Engineer role focused on optimizing Intel's process technology for power, performance, and area (PPA) of Intel IPs. Responsibilities include conducting experiments, defining methodologies, building tools, analyzing results, and collaborating with design teams. | — | 0 |
| Firmware Architect Firmware Architect role at Intel focusing on designing and developing embedded software solutions, emphasizing security and performance. Responsibilities include defining architectural frameworks, translating requirements, developing algorithms, leading vulnerability assessments, and collaborating with engineering teams on implementation and new technology adoption. Requires strong C/low-level Linux driver experience and firmware architecture/system-level design. | — | 0 |
| Back End Cloud Software Developer Experienced Full Stack Cloud Software Developer with a strong backend orientation to design, build, and maintain software components and tools used across the organization. Will work on complex software systems, collaborate with multiple teams, and contribute across the full software development lifecycle. | — | 0 |
| IP Design Verification Engineer Intel is seeking an IP Design Verification Engineer with 6+ years of experience in Pre-Si verification. The role involves developing IP verification plans, test benches, and simulation models to ensure design specifications are met. Responsibilities include debugging issues, collaborating with cross-functional teams, and maintaining verification infrastructure. Requires strong skills in Specman “e” / System Verilog and understanding of verification methodologies. | — | 0 |
| Senior Technical Lead -Power & BatteryLife Designs, develops, and executes power and performance plans for IPs and SoCs. Identifies, builds, and maintains power, thermal, performance/watt optimizations, and characterizations for IPSoC power and performance goals. Conducts feature analysis from power and performance standpoint and drives to close any gaps between observed behavior and target on platforms in development. Provides recommendations for future architectures. Develops and enhances innovative tools for architectural performance analysis. Develops methodologies and models to drive continuous improvements in optimization of power and performance configurations to meet market requirements. Ensures platform and its components are optimized for performance and power balance. Identifies power activity zones and works with design, architecture, binning/technology, and manufacturing teams on ways to meet power consumption goals. Works cross functionally on analysis, validation, and tuning of architectures and features that advance the state of art in performance and efficiency. | — | 0 |
| Senior CPU Physical Design Engineer Senior CPU Physical Design Engineer responsible for the design and delivery of high-performance CPU blocks from RTL to GDS, including synthesis, floorplanning, place and route, CTS, timing closure, and verification. Requires 10+ years of experience with industry-standard EDA tools. | — | 0 |
| CPU Physical Design Engineer This role is for a CPU Physical Design Engineer at Intel, focusing on the design and delivery of high-performance CPU blocks from RTL to GDS. Responsibilities include executing the full physical design flow, leading verification and sign-off, and optimizing designs for power, performance, and area using industry-standard EDA tools. The role requires a BSc or MSc degree in Electrical or Computer Engineering and at least 7 years of experience in physical design. | — | 0 |
| Practical Engineering Student for Intel Kiryat Gat Practical Engineering student role in a semiconductor manufacturing facility, focusing on operating and supporting advanced equipment, learning maintenance, and assisting engineering teams with troubleshooting and process improvement. Requires enrollment in a Mechanical or Mechatronics Practical Engineering program with at least three semesters remaining. | — | 0 |
| System Validation Engineer System Validation Engineer at Intel responsible for defining, developing, and performing functional validation for Thunderbolt technology. This involves engaging from early product stages to define HW/FW hooks, developing methodologies and test plans, executing plans, and collaborating with engineers for design optimization, troubleshooting, and failure analysis. The role requires FPGA and Silicon debug, understanding the full stack (HW/FW, driver, OS), and applying various tools and techniques to ensure validation coverage. The engineer will publish validation reports, work with cross-functional teams (architecture, design, verification, etc.) to improve debug and validation strategies, and develop content for IP interactions. The role also involves engaging in all product life cycle phases, developing and validating content and infrastructure, and performing bug hunts in simulation, emulation, and FPGAs to ensure silicon readiness. | — | 0 |
| Linux Driver Wifi developer Software developer for Linux Wifi team at Intel, contributing to open-source code for Intel's wifi devices on Linux. Role involves working on the Linux kernel in C, focusing on networking, PCI, and the wifi stack. | — | 0 |
| Cache Senior Design Engineer for the new AI Group Seeking a Senior Design Engineer with 10+ years of experience in Block Level design and 3+ years in Cache systems to join the AI industry's Habana group at Intel. Responsibilities include designing and implementing IP solutions, collaborating with cross-functional teams, and ensuring the quality and performance of IP designs. Requires B.Sc. in Electrical Engineering or Computer Engineering and strong RTL skills in System Verilog. | — | 0 |
| Physical Design (Backend) Technical Leader Senior Physical Design Technical Lead at Intel, responsible for leading and driving backend implementation of advanced wireless products. This role involves defining and improving design implementation flows, automation, and signoff methodologies, optimizing PPA metrics, and collaborating with other design teams. Requires extensive experience in VLSI physical design, proficiency in Synopsys tools, and scripting skills. | — | 0 |