NVIDIA currently has 496 active AI-related job listings. The majority of these roles, 52%, are focused on serving infrastructure, with agents representing another significant segment at 23%. Engineering is the dominant function, with 441 positions. The United States leads hiring geographies with 287 roles, followed by China with 64. Frequent tech tags include model_serving, inference_infra, and agent_orchestration, suggesting a focus on deployment and management of AI models. Over the last 30 days, NVIDIA posted 214 new AI roles, a 27% decrease compared to the previous 30-day period.
Currently tracking 440 active AI roles, down 53% versus the prior 4 weeks. Primary focus: Serve · Engineering. Salary range $100k–$575k (avg $262k).
NVIDIA currently has 487 active AI-related roles in our index. The most common open titles are: Deep Learning Performance Architect (4), Senior Deep Learning Performance Architect (4), AI Research Scientist (3), Developer Technology Engineer - AI (3), Manager, Deep Learning Algorithms (3). Most positions are in Engineering and Research.
NVIDIA's active AI hiring is concentrated in: serving infrastructure (54%), agents (21%), application (8%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
NVIDIA is hiring AI talent in: United States (286 roles), China (59 roles), Israel (50 roles), Germany (21 roles).
Job postings at NVIDIA most frequently reference: model serving, inference infra, agent orchestration, llm observability, multimodal.
In the past 30 days, NVIDIA has posted 110 new AI-related roles. That is a -50% change versus the prior 30 days (218 → 110).
| Title | Stage | AI score |
|---|---|---|
| Senior Software Engineer, Hardware-Oriented Senior Software Engineer to develop Python-based software solutions controlling Nvidia HW on Linux, including frameworks and GUI tools for internal engineering groups. The role involves full ownership of the software lifecycle, from requirements to delivery, with a focus on hardware-software interaction and robust engineering workflows. | — | 0 |
| Firmware Engineer Firmware Engineer role focused on developing and testing cutting-edge networking features for NVIDIA NICs in both pre and post-silicon environments. Requires strong C/C++ skills, understanding of data structures, algorithms, and system debugging. | — | 0 |
| Senior C/C++ Software Engineer Senior C/C++ Software Engineer for NVIDIA Networking Unit, focusing on NIC/DPU firmware design and implementation, new standards, and product launches from pre-silicon to full lifecycle. Requires strong C/C++ skills, embedded systems experience, and networking expertise. |
| — |
| 0 |
| Senior Chip Design Engineer NVIDIA is seeking a Senior Chip Design Engineer to join their Switch Silicon group. The role involves designing and implementing next-generation Switch Silicon chips, building reference models, and verifying chip blocks. This position requires 4+ years of experience in RTL design or verification and a degree in Electrical or Computer Engineering. | — | 0 |
| Senior Physical Design Backend Engineer Senior Physical Design Backend Engineer for NVIDIA's Networking Silicon Engineering team, focusing on high-speed communication devices. Responsibilities include physical design of blocks, resolving complex timing and congestion issues, and daily work across RTL2GDS flows (synthesis, place and route, timing closure, power analysis, physical verification). Requires 5+ years of experience in Physical Design, proven RTL2GDS flow experience, knowledge of PNR, STA, physical verification, and familiarity with EDA tools. | — | 0 |
| Senior Test Engineer NVIDIA is seeking a Senior Test Engineer to design and develop automated tests for networking switches and adapters, ensuring product quality and high availability. This role involves close collaboration with HW, ASIC, and SW Engineering teams, implementing and maintaining sophisticated tools to improve development workflows and productivity. Responsibilities include test design, debugging, bug fixing, supporting production lines, and generating quality statistics. | — | 0 |
| Senior Chip Design Verification Engineer Senior Chip Design Verification Engineer to join NVIDIA's Switch Silicon team, focusing on designing and implementing next-generation Switch Silicon chips. Responsibilities include micro-architecture of dynamic verification environments and designing these environments according to specifications, with a focus on power, area, and performance. Requires 5+ years of experience in RTL design/dynamic verification. | — | 0 |
| Network RDMA Algorithms Architect NVIDIA is seeking a Network RDMA Algorithms Architect to research and analyze networking solutions and end-to-end algorithms, focusing on RDMA load balance and congestion control for next-generation networking. The role involves working with simulation environments and real hardware, and collaborating with other research teams. | — | 0 |
| Senior High Speed Optical Transceiver Design Engineer NVIDIA is seeking a Senior High Speed Optical Transceiver Design Engineer to design electrical schematics, lead multi-discipline product design, perform lab work, and scale products from lab to mass production. The role involves working with various teams and learning new technologies for product improvement. | — | 0 |
| Senior Silicon Security Architect Seeking a Senior Silicon Security Architect to define, craft, implement, and guide security research, architecture, and design for next-generation Nvidia Networking products. This role involves a hands-on approach, collaborating with diverse internal and external teams to meet security requirements for state-of-the-art network products. Responsibilities include researching and designing hardware and software solutions, applying hardware security primitives, collaborating on open-source software, guiding silicon security direction, architectural modeling, and addressing customer/partner security issues. | — | 0 |
| Manager, DFT Architecture Manager for DFT Architecture at NVIDIA, leading a group of experts in structural testing for HCA products. Responsibilities include defining team goals, strategies, tools, methodologies, and KPIs, as well as leading functional testing strategy and aligning with global NVIDIA standards. Requires a B.Sc. in Electrical Engineering, 8+ years of experience in hardware design/systems engineering/technical leadership, and 3+ years of managerial experience. | — | 0 |
| Senior Security Architect NVIDIA is seeking a Senior Security Architect to design and implement security solutions for their high-performance networking products. The role involves collaborating across hardware, software, and research teams to ensure security requirements and standards are met, applying hardware security primitives, and working with customers on security issues. Requires 10+ years of experience, a background in embedded systems, firmware, and security-by-design principles, with strong programming skills in Python, ARM assembly, and C/C++. | — | 0 |
| Senior Formal Verification Engineer Senior Formal Verification Engineer for NVIDIA Networking team, working on Pre-Silicon design and verification of Switch and GPU technologies. Uses formal verification tools and methodologies to prove design correctness for HPC, AI infrastructures, data-center, network, and storage markets. | — | 0 |
| Senior Verification Engineer - HWPM NVIDIA is seeking a Senior Verification Engineer for their HWPM team to drive system-level IP verification for NVIDIA's SoCs. The role involves defining and developing performance measurement methodologies, creating test plans, implementing tests, and building reusable testbenches using System Verilog and UVM. Requires experience in hardware verification, scripting languages like Python, and familiarity with design and verification tools. | — | 0 |
| Senior Chip Design Verification Engineer Senior Chip Design Verification Engineer role at NVIDIA focusing on developing and verifying high-speed communication devices and chips within the Networking Silicon engineering team. Responsibilities include building reference models, simulation, planning, coding, coverage, and integration in a design verification team. | — | 0 |
| Senior Packaging Technical Engineer - Hardware NVIDIA is seeking a Senior Packaging Technical Engineer to define chip pad ring, substrate interconnect scheme, and lead the package layout design process. This role involves collaboration with various engineering teams and requires a minimum of 5 years in board/system design, with package design experience being preferred. Strong programming and scripting skills in Perl, Python, Tcl are desired. | — | 0 |
| Chip Design Verification Engineer NVIDIA is seeking a Chip Design Verification Engineer for their Switch Silicon team. The role involves designing and implementing next-generation Switch Silicon chips, focusing on high-speed communication devices with high throughput and low latency. Responsibilities include developing verification components, reference models, and simulating chip blocks under challenging constraints, while collaborating with Architecture, Micro-Architecture, and FW teams. Requires a degree in Electrical/Computer Engineering or equivalent, strong programming and logic design skills, 3-5 years of RTL verification experience, and good teamwork/communication skills. | — | 0 |
| Hardware Tools Application Engineer NVIDIA is seeking a Hardware Tools Application Engineer to act as a liaison between internal engineering teams (chip designers, algorithm engineers, etc.) and the development team. The role involves providing technical support, debugging issues across hardware, software, and Linux, understanding user needs, and collaborating on the design and development of internal tools to improve engineering workflows. | — | 0 |
| Senior Chip Design Engineer Senior Chip Design Engineer role focused on designing and implementing state-of-the-art Switch Silicon chips, emphasizing power, area, and performance. Responsibilities include RTL design, verification, simulation, synthesis, timing, and post-silicon activities, collaborating with various engineering teams. | — | 0 |
| Chip Architect NVIDIA is seeking a Chip Architect to define the Network Adapter chip architecture end-to-end, from market requirements through design and all product life cycles. This role involves collaboration with various engineering teams, research and analysis for current and future architectures, and crafting product design specifications. | — | 0 |
| Senior Package Layout Engineer NVIDIA is seeking a Senior Package Layout Engineer to design state-of-the-art high-speed interconnect systems for Supercomputers and Datacenters. The role involves collaborating on high-speed and PDN design for ASIC packages, developing symbols, pad stacks, and performing substrate package routing, placement, and power distribution using APD or SiP tools. Responsibilities include optimizing package pin-out, developing methodologies to improve layout productivity and reliability, and leading projects from start to finish. Requires a B.Sc. in Electrical Engineering or equivalent, 5+ years of experience in Package or PCB Layout with high-speed design, signal integrity, and PDN planning, and experience with substrate layout for wire bond and flip chip packages. | — | 0 |
| Senior Chip Design Engineer NVIDIA is seeking a Senior Chip Design RTL Design Engineer to join their Switch Silicon group. The role involves designing and implementing next-generation Switch Silicon chips, focusing on high-speed communication devices with high throughput and low latency. Responsibilities include designing RTL units, building reference models, and verifying chip blocks, working closely with architecture, micro-architecture, and firmware teams. | — | 0 |
| Senior Front-End Power Engineer NVIDIA is seeking a Senior Front-End Power Engineer to analyze and improve the power efficiency of their Switch product line. This role involves collaborating with various engineering teams to develop and deploy methodologies for power analysis and reduction, influencing architectural and design improvements for energy consumption. | — | 0 |
| System Design Engineer NVIDIA is seeking a System Design Engineer to develop GPU/Tegra based products for various applications including GPU cards, servers, automotive, robotics, industrial PCs, and consumer electronics. The role involves reviewing board designs, collaborating with cross-functional teams on product cost, performance, and schedule, participating in documentation for manufacturing, and optimizing circuits for performance and cost. | — | 0 |
| Senior System Design Engineer NVIDIA is seeking a Senior System Design Engineer to work on GPU/Tegra based products for various applications including automotive, robotics, and industrial PCs. The role involves reviewing board designs, collaborating with cross-functional teams, optimizing circuits for performance and cost, and participating in product release documentation. Requires 10+ years of board design experience and strong analytical skills. | — | 0 |
| Formal Verification Manager Lead a team of formal verification engineers responsible for verifying next-generation NVIDIA Networking products and GPU technologies, ensuring design correctness at the highest level for complex digital designs. | — | 0 |
| Principal Formal Verification Engineer Principal Formal Verification Engineer to join NVIDIA Networking team, responsible for shaping the formal strategy and execution of complex, high-performance silicon designs for data centers, AI infrastructure, networking, and storage systems. Requires deep hands-on experience and strong execution mindset in applying formal methods to validate designs. | — | 0 |
| Manager, Hardware and System Development Engineering Manager for Hardware and System Development Engineering at NVIDIA, focusing on creating and optimizing test and validation platforms for high-performance networking products. The role involves leading hardware lifecycle, collaborating with cross-functional teams, and driving technical execution. | — | 0 |
| Senior Site Reliability Engineer, HPC and LSF NVIDIA is seeking a Senior Site Reliability Engineer to manage and operate large-scale compute clusters that power silicon development. The role involves automating deployments, managing workload schedulers, troubleshooting complex issues, and optimizing system performance and reliability. The engineer will collaborate with domain experts to improve infrastructure utilization and contribute to faster time-to-market for new chips. | — | 0 |
| DFT Change Analyst NVIDIA is seeking a Hardware Engineer to lead Change Impact Analysis for engineering design changes (ECOs/ECRs) on networking and computing platforms. The role involves collaborating with cross-functional teams to evaluate impacts on hardware, mechanical design, system performance, and test coverage, ensuring product quality and integrity. | — | 0 |
| Senior System Test Design Engineer Senior System Test Design Engineer for NVIDIA's networking product engineering team. This role involves designing and developing automated tests for networking switches, collaborating with HW, ASIC, and SW Engineering teams to ensure product quality and high availability. Responsibilities include defining and developing tests from development to final production, and working with manufacturing teams to improve yields, coverage, and capacity. | — | 0 |
| Senior Design Verification Engineer - PCIE Senior Design Verification Engineer for PCI Express controllers used in GPUs, SOCs, and DPUs. Requires expertise in verification methodologies like UVM and Specman/e, and knowledge of industry standard protocols. | — | 0 |
| System Software Engineer - OpenBMC System Software Engineer role focused on designing and implementing OpenBMC Core Infrastructure and Features for GPU Server platforms. Responsibilities include BMC firmware bring-up, performance analysis, developing manageability features, contributing to the OpenSource community, and ensuring code quality and security. Requires expertise in BMC firmware development, board bring-up, system management standards, and strong programming skills in C/C++, Bash, Python, Go. | — | 0 |
| Senior Software and System Architect Senior Software and System Architect role at NVIDIA focusing on cloud networking, security, virtualization, and orchestration for DPUs & NICs. The role involves researching new technologies, defining architecture for next-generation hardware, and building end-to-end solutions from application to hardware level. It requires strong C/Python development skills, Linux, Docker, and deep knowledge of data center networking. | — | 0 |
| Manager, IC Reliability Labs Manager for an IC Reliability Lab at NVIDIA, responsible for leading lab activities, managing a team of operators and engineers, and overseeing various types of IC testing, equipment maintenance, and lab processes. | — | 0 |
| Senior ASIC Architect NVIDIA is seeking a Senior ASIC Architect for its switch division. This role involves defining the architecture of next-generation switch product lines, focusing on performance for Ethernet and InfiniBand. The position requires cross-disciplinary collaboration with software, ASIC design, verification, physical design, and platform teams to improve performance and debug complex issues. The ideal candidate will have 5+ years of experience in ASIC design/uarch/arch/performance and strong analytical and debug skills. | — | 0 |
| Senior Verification Engineer, Memory Subsystem Senior Verification Engineer role focused on verifying the ASIC design, architecture, and micro-architecture of the GPU memory subsystem using advanced verification methodologies. Responsibilities include defining verification scope, developing infrastructure, and ensuring correctness through functional coverage and performance verification. | — | 0 |
| Senior SRAM Circuit Design Engineer NVIDIA is seeking a Senior SRAM Circuit Design Engineer to develop sophisticated SRAM compilers and explore future process nodes. Responsibilities include transistor-level circuit design, supervising layout, verification, debug, and automating the assembly and validation of SRAM macros. The role also involves collaborating with SOC design, silicon test, and productization teams. | — | 0 |
| Senior IP DV Engineer - NOC IP Senior Verification Engineer to verify the design and implementation of memory subsystem units for GPUs and SOCs, impacting product lines from consumer graphics to self-driving cars and AI. Responsibilities include defining verification scope, developing infrastructure, and ensuring correctness using advanced methodologies like SV/UVM. | — | 0 |
| Senior PHY System Engineer NVIDIA is seeking a Senior PHY System Engineer to join their Post-silicon department, focusing on the End-to-End physical-layer performance characterization, verification, and debugging of NVIDIA systems, including ASICs and Electro-Optical/Electrical chips and systems. The role involves silicon bring-up, lab measurements with various equipment, and leading data-driven discussions for product improvement and mass production. | — | 0 |
| Senior Verification Engineer, PCIE Senior Verification Engineer for PCI Express controllers in GPUs and SOCs, focusing on ASIC design verification using UVM and SystemVerilog. | — | 0 |
| Senior Verification Engineer, PCIE Senior Verification Engineer to verify the design and implementation of PCI Express controllers for GPUs and SOCs, using UVM and Verilog/SystemVerilog. | — | 0 |
| Senior Formal Verification Engineer Senior Formal Verification Engineer at NVIDIA, focusing on pre-silicon design and verification of NIC technologies using state-of-the-art formal verification tools and methodologies to prove design correctness. | — | 0 |
| Senior Chip Design Engineer Senior Chip Design Engineer at NVIDIA, focusing on the verification of state-of-the-art Switch Silicon chips for high-speed communication devices. The role involves planning and executing dynamic verification environments, integrating and verifying the Switch at the system level, and driving FullChip verification execution. | — | 0 |
| Senior Chip Design RTL Engineer Senior Chip Design Engineer to join our Switch Silicon team. Design and implement the next generation state-of-the-art Switch Silicon chips. Develop industry's best high-speed communication devices, delivering the highest throughput and lowest latency! | — | 0 |
| Senior Chip Design Verification Engineer Senior Chip Design Verification Engineer at NVIDIA, focusing on networking silicon for high-speed communication devices. Responsibilities include building reference models, verifying and simulating chip blocks, and collaborating with cross-functional teams. Requires 5+ years of RTL Frontend ASIC Design or Verification experience. | — | 0 |
| Senior SRAM Circuit Design Engineer Senior SRAM Circuit Design Engineer at NVIDIA, focusing on transistor-level circuit design, SRAM compiler development, and advanced process node exploration for high-performance chips. Requires 5+ years of SRAM design experience and Python scripting. | — | 0 |
| Senior SRAM Circuit Design Engineer NVIDIA is seeking a Senior SRAM Circuit Design Engineer to develop sophisticated SRAM compilers and design SRAM macros for their chips. The role involves transistor-level circuit design, layout supervision, verification, and automation of SRAM assembly and validation. The engineer will also explore future process nodes and collaborate with SOC design, silicon test, and productization teams. | — | 0 |
| Senior SRAM Circuit Design Engineer Senior SRAM Circuit Design Engineer at NVIDIA, focusing on transistor-level circuit design, SRAM compiler development, and advanced process node exploration for high-performance chips. Requires 5+ years of SRAM design experience and Python scripting. | — | 0 |
| Senior Analog Layout Design Engineer NVIDIA is looking for a Senior Analog Layout Design Engineer to perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, SerDes, general I/O's, ESD structures designs in state-of-the-art sub-micron CMOS FinFET technologies using Cadence tools. The role involves working with ASIC and mixed-signal engineers to customize designs for integration in VLSI products, including floor planning, custom layout, and verifying against design rules and schematics, and EM/IR analysis. Requires a minimum of 8 years of relevant mask analog layout experience, an Electronics Practical Engineer certificate or B.Sc. in Electrical Engineering, proven understanding of analog circuit layout concepts, expertise with Cadence custom circuit design tools (Virtuoso), and experience with DRC/LVS verification tools. | — | 0 |