Tenstorrent currently has 27 active AI-related job listings, with a significant majority, 81%, focused on serving infrastructure. Engineering roles comprise all of their AI hiring. The company is primarily hiring in the United States and Canada. Frequent technical tags include model_serving, inference_infra, and agent_orchestration, suggesting a focus on AI model deployment and management. In the last 30 days, Tenstorrent has not posted any new AI roles, representing a 100% decrease compared to the previous 30-day period.
Currently tracking 22 active AI roles, down 50% versus the prior 4 weeks. Primary focus: Serve · Engineering. Salary range $100k–$500k (avg $300k).
Tenstorrent currently has 25 active AI-related roles in our index. The most common open titles are: Sr. Engineer, Software - AI Compiler (2), AI/ML Physical Design Flow Engineer, C++ Machine Learning Engineer, Models Training, Design Verification Lead, AI Hardware , Infrastructure and Platform Development Engineer. Most positions are in Engineering and Research.
Tenstorrent's active AI hiring is concentrated in: serving infrastructure (80%), agents (8%), application (4%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
Tenstorrent is hiring AI talent in: United States (10 roles), Canada (8 roles), Serbia (4 roles), Poland (2 roles).
Job postings at Tenstorrent most frequently reference: inference infra, model serving, fine tuning, agent orchestration, vision.
In the past 30 days, Tenstorrent has posted 1 new AI-related role.
| Title | Stage | AI score |
|---|---|---|
| Model Research, Optimization, and Training Research role focused on optimizing and training large language models on custom AI accelerators, involving techniques like speculative decoding and quantization, and translating research into production-ready systems. | Post-trainServe | 9 |
| RISC-V AI / HPC & Agentic Software Engineering Lead Lead engineering efforts for RISC-V CPUs optimized for AI, HPC, and agentic systems, focusing on integrating and optimizing low-level kernels and leading the bring-up of a RISC-V-native agentic AI software stack, including runtime orchestration and distributed execution frameworks. | AgentServe |
| 9 |
| Sr. Engineer, Software - AI Compiler Software Engineer role focused on developing and optimizing an MLIR-based AI compiler (TT-Forge) to run AI models efficiently on Tenstorrent hardware. Involves optimizing computational graphs, creating custom dialects, and transformation passes, with a focus on training and multi-chip scaling. | Serve | 8 |
| AI/ML Physical Design Flow Engineer The role involves architecting, integrating, and deploying AI/ML-driven solutions into production physical design flows for advanced semiconductor nodes. This includes creating custom CAD tools and optimizing EDA tools using data-driven and ML-based techniques to improve PPA and runtime. The engineer will also develop and enhance RTL-to-GDS methodologies. | Serve | 7 |
| Software Engineer, Metal Runtime (Core Systems) Software Engineer on the Metal Runtime team working on low-level software for AI accelerators, focusing on scheduling, memory movement, and efficient execution across parallel processors. The role involves building and optimizing high-performance runtime systems close to the hardware. | Serve | 7 |
| Software Engineer, AI Compiler Software Engineer role focused on developing and scaling an MLIR-based AI compiler (TT-Forge) for Tenstorrent, involving graph transformations, lowering passes, and kernel optimizations to support both training and inference on custom chip architectures. | Serve | 7 |
| Software Engineer, TT-Distributed Software Engineer role focused on developing and optimizing distributed software systems for AI and HPC clusters, specifically for distributed inference and training infrastructure. Requires strong C/C++ systems programming, distributed computing principles, and experience with MPI-based technologies. | ServeData | 7 |
| Design Verification Lead, AI Hardware Lead a team of Verification Engineers to validate the functionality and performance of next-generation AI hardware, focusing on AI-specific data types, compute patterns, and on-chip network validation. | Serve | 7 |
| Director, RISC-V Software TPM & Ops Tenstorrent is seeking a Director, RISC-V Software TPM & Ops to act as a hybrid Chief of Staff and execution-focused TPM for the RISC-V software organization. This role involves defining team goals, creating executable plans, driving cross-functional initiatives, improving planning and execution, managing risks, supporting headcount planning and recruiting, and preparing materials for customer engagements. The ideal candidate is a senior operator with strategic thinking, strong execution skills, and the ability to drive complex technical initiatives in ambiguous environments. | — | 5 |
| Principal Technical Program Manager Tenstorrent is seeking an experienced Technical Program Manager to lead cross-functional product development efforts for their AI hardware and systems. The role involves driving complex programs from concept to execution, managing schedules, risks, and stakeholder communication. This is a hybrid role based in Santa Clara, CA, Austin, TX, or Fort Collins, CO. | — | 5 |
| Tech Recruiter - Contractor Contract Technical Recruiter to help scale engineering teams building AI compute. Role involves partnering with software engineering leaders to identify, attract, and hire talent across AI, machine learning, systems software, and related technical domains. This is a 12-month contract role based in Austin, TX. | — | 5 |
| Associate, Corporate Development This role is in Corporate Development, focusing on M&A, fundraising, partnerships, and corporate strategy for an AI and RISC-V compute company. It requires strategic thinking, financial modeling, and experience in fast-paced professional environments like investment banking or consulting. The role will involve working closely with the C-suite and external stakeholders to drive the company's growth and strategic decisions within the AI and semiconductor ecosystem. | — | 5 |
| Physical Design Engineer, PnR Tenstorrent is seeking a Physical Design Engineer to implement high-performance partitions for an AI SOC. The role involves owning the complete implementation flow from synthesis to tapeout, working with architects, RTL designers, and DFT engineers to resolve issues and ensure signoff. | — | 5 |
| Physical Design Engineer Physical Design Engineer to implement high-performance blocks for CPU and AI/ML architectures, owning the complete implementation flow from synthesis to tapeout. Requires expertise in SOC/ASIC physical design, synthesis, PnR, timing closure, and industry-standard tools. | — | 5 |
| IP Software Generalist Develop and optimize the software stack for AI and RISC-V hardware IP customers, including firmware, drivers, system tools, and APIs, ensuring seamless integration and customer experience. Partner with hardware, IP delivery, customer support, and product teams. | — | 5 |
| Staff Field Application Engineer, Customer Success Field Application Engineer role focused on customer success and driving adoption of Tenstorrent's AI products and solutions. Requires strong technical knowledge in AI/ML, customer-facing skills, and experience with AI technologies and frameworks, embedded systems, and AI accelerators. The role involves collaborating with sales and product teams, understanding customer challenges, and providing solutions. Experience with hardware/software co-optimization for edge inference is important. | — | 5 |
| Software Engineer, Metal Runtime (API & Abstractions) Software Engineer on the Metal Runtime team at Tenstorrent, working on low-level software for AI accelerators. Designs runtime systems close to hardware and defines host/device APIs. Focuses on API design, abstraction, performance, and developer experience. | Serve | 5 |
| SOC Emulation Engineer - Hardware Emulation Infrastructure This role supports hardware emulation infrastructure and internal chip design teams by integrating transactors, developing Python test frameworks, and providing technical support. It requires proficiency in Python, C++, and SystemVerilog, with experience in chip design, verification, or emulation. The role also involves using AI tools for code generation and debugging. | — | 5 |
| Static Timing Analysis (STA) Methodology Engineer This role focuses on Static Timing Analysis (STA) methodology for advanced-node, high-performance, low-power semiconductor designs. The engineer will lead the development and optimization of STA methodologies and flows, drive data- and ML-assisted timing automation, and collaborate with various teams and EDA vendors to solve complex timing challenges. The role involves improving PPA (Power, Performance, Area) and runtime efficiency through automation and data-driven techniques. | — | 5 |
| Interconnect and Compute Architect This role focuses on designing and building next-generation CPU networking architecture for AI/ML workloads, targeting both datacenter and robotics/automotive applications. The primary focus is on the interconnect and compute aspects that enable AI systems, rather than directly building AI models. | Serve | 5 |
| Field Applications Engineer, IP Product Field Applications Engineer for Tenstorrent's RISC-V CPU and AI accelerator IP products. Responsible for end-to-end technical engagements with customers, translating architectural advantages into wins, and shaping product roadmap with market feedback. Requires deep technical expertise in semiconductors and customer engagement skills. | — | 5 |
| Sr. Staff Engineer, RISC-V Software Workload Enablement This role focuses on porting and enabling AI workloads on RISC-V architectures, requiring expertise in DevOps, workload migration, and systems software to optimize hardware performance for AI applications. It involves bridging the gap between IT, DevOps, and AI teams. | — | 5 |
| Fabric SOC Architect This role focuses on performance architecture for AI/HPC platforms, bridging software execution and silicon design. The architect will work on ML software stacks, compilers, CPU design, cache coherency, and interconnect fabrics to optimize SoC performance. Familiarity with ML/AI traffic patterns is a plus. | — | 5 |
| Staff Mixed Signal Design Engineer, Silicon Validation This role focuses on validating and qualifying die-to-die (D2D) subsystems, AI, and Processor IP testchips for the chiplet ecosystem. Responsibilities include developing hardware infrastructure for validation platforms, performing electrical characterization, and supporting customer silicon bring-up. The role requires expertise in silicon test and characterization, lab environments, and high-speed measurements. | — | 5 |
| Risc-V Architect Tenstorrent is seeking a Risc-V Architect to analyze AI workloads and architect custom RISC-V CPU cores optimized for performance, power, and area. The role involves designing custom instructions and collaborating across teams to co-design the company's next-gen compute architecture, focusing on improving programmability and developer experience for AI compute. | — | 5 |
| RISC-V CPU Microarchitecture / RTL Tenstorrent is seeking a RISC-V CPU Microarchitecture/RTL owner to develop next-generation CPU designs. This role involves defining microarchitecture specifications, designing RTL, and performing unit verification for CPU components like branch predictors and vector execution units. The candidate will also use AI tools to accelerate the design process and potentially mentor junior engineers. Experience with high-performance CPU RTL design for architectures like x86, Arm, or RISC-V is required. | — | 5 |
| SoC - Chiplet Design Lead Tenstorrent is seeking a SoC Chiplet Design Lead to drive the design and development of advanced System-on-Chip (SoC) architectures targeting AI, HPC, and automotive markets. This role involves leading cross-functional teams through the entire SoC lifecycle, from concept to tape-out, focusing on performance, scalability, and efficiency. The ideal candidate will have deep expertise in SoC and chiplet design, RTL design, and digital architecture, with proven experience in leading end-to-end SoC development and verification. | — | 5 |
| GCC Compiler Engineer Tenstorrent is seeking a GCC Compiler Engineer to design, develop, and optimize compilers for next-generation RISC-V and AI compute architectures. The role involves working across hardware and software teams to improve performance and integration of custom toolchains for both traditional compute and machine learning workloads. | — | 5 |
| Senior Manager, Global People Operations Tenstorrent is seeking a Senior Manager, Global People Operations to lead and strengthen People Operations across its global footprint. This role will oversee a distributed team, build a consistent and scalable global operating model, and focus on employee data integrity, documentation, compliance, onboarding, and operational excellence. The ideal candidate will have strong judgment, team leadership, and the ability to create clear, repeatable processes for complex multi-country operations. | — | 0 |
| CPU Verification Fellow, RISC-V High-Performance Processor Tenstorrent is seeking a CPU Verification Fellow to lead verification strategy and execution for next-generation RISC-V high-performance processors. This role requires deep CPU verification expertise, strong microarchitecture understanding, and the ability to guide large engineering teams from early design through tapeout and post-silicon validation. The ideal candidate has verified complex out-of-order, speculative, superscalar CPUs and can define scalable methodology across simulation, formal verification, emulation, FPGA, and silicon bring-up. | — | 0 |
| Chip Design Lead Tenstorrent is seeking a Chip Design Lead to drive complex SoC programs from architecture definition through execution, tapeout, and deployment. This role requires strong cross-functional leadership and deep technical credibility across front-end design flows. | — | 0 |
| Sr. Engineer, RTL Implementation This role is for a Sr. Engineer, RTL Implementation focused on CPU design using RISC-V ISA. The engineer will work on front-end CAD flows, collaborate with micro-architects to optimize PPA, and work with DV, PD, RTL, and performance teams to deliver a converged design. The role involves synthesis, place and route, and enhancing physical design methodologies. | — | 0 |
| Sr. Engineer, CPU RTL Design This role is for a Sr. Engineer focused on CPU RTL Design for high-performance RISC-V CPUs, collaborating with various teams to meet functional, timing, and power goals. The role involves owning RTL design and microarchitecture development, optimizing power, performance, and area, and enhancing the RTL design environment. | — | 0 |
| CPU Core Design Verification Testbench Lead Lead CPU core-level testbench development and verification for high-performance out-of-order RISC-V CPUs, utilizing AI-assisted workflows and agents for debug and analysis. | — | 0 |
| Staff Cost & Inventory Specialist, Finance This role is a Finance Specialist focused on cost and inventory analytics for AI hardware. It involves product cost forecasting, inventory metrics, and partnering with supply chain and operations to improve gross margin and production planning. While the company works on AI technology, this specific role is within the finance department and does not involve building or directly working with AI models. | — | 0 |
| Full-Chip Physical Design Verification Engineer Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes. This role involves leading physical verification closure, debugging issues, and collaborating with various teams to achieve successful tapeouts. | — | 0 |
| PDK/CAD Engineer Tenstorrent is seeking an experienced EDA/PDK CAD Engineer to build and maintain design infrastructure for AI silicon innovation. The role involves installing and optimizing PDKs, managing EDA tool flows, and collaborating with various engineering teams to improve design efficiency. Responsibilities include troubleshooting CAD issues and supporting physical verification and simulation flows. | — | 0 |
| Staff Engineer, CPU Core Verification Staff Engineer focused on CPU core-level verification for out-of-order RISC-V CPUs, involving RTL, UVM, C/C++ stimulus development, debug, and collaboration across design and validation teams. | — | 0 |
| Top Level Physical Design Engineer This role focuses on the physical design of AI and CPU System-on-Chip (SOC) designs, including floorplanning, power grids, and clock networks, to ensure chip-level closure. It involves collaboration with cross-disciplinary teams and optimization for power, performance, and area. | — | 0 |
| Staff Engineer, Emulation Technical Lead Tenstorrent is seeking a Staff Engineer, Emulation Technical Lead to lead technical efforts and strategy around their emulation infrastructure for high-performance CPUs that power AI products. This role involves leading technical strategy, enabling emulation infrastructure, driving debug efforts, and optimizing performance with design verification teams and tool vendors. The role is hybrid and based in Austin, TX. | — | 0 |
| Sr. Engineer, Performance Infrastructure The role focuses on CPU design infrastructure for performance analysis, correlation, and verification, working with RISC-V ISA and collaborating with core architects and RTL teams to deliver efficient and performant designs. It involves enhancing the design environment, tools, and methodologies, and optimizing power, performance, and area. | — | 0 |
| Silicon Power & Characterization Lead Tenstorrent is seeking a Lead Engineer to own post-silicon power characterization and correlation for AI semiconductor products. Responsibilities include developing and executing power measurement strategies, correlating silicon data with pre-silicon models, and driving improvements in power architecture and methodologies. The role requires deep understanding of silicon power domains and lab measurement techniques, with a focus on cross-functional collaboration. | — | 0 |
| Staff Engineer, Software Release and Packaging - RISC V Tenstorrent is seeking a Staff Engineer for Software Release and Packaging, focusing on RISC-V and system IP products. The role involves building, packaging, and releasing software that combines Linux and open-source packages with proprietary software to enable customer success. This is a remote or hybrid position in North America or Australia, with compensation ranging from $100k to $500k. A key requirement is eligibility to access U.S. export-controlled technology. | — | 0 |
| Physical Design Engineer: Die-to-Die Interface (RTL to GDSII) Tenstorrent is seeking a Physical Design Engineer to drive the Die-to-Die (D2D) Physical Implementation from RTL to GDSII for multi-die/chiplet architectures. The role involves full physical design flow, including synthesis, floorplanning, place-and-route, CTS, and sign-off, with a focus on high-speed interfaces. | — | 0 |
| Chiplet Physical Design Engineer Tenstorrent is seeking a Senior Chiplet Physical Design Engineer to design and integrate chiplets into a System-in-Package (SiP) for AI silicon. The role involves synthesis, place-and-route, and timing closure for high-speed CPU cores on advanced process nodes, collaborating with global teams and external partners. | — | 0 |
| Senior Tax Manager Senior Tax Manager responsible for leading all aspects of Tenstorrent’s tax function including federal, state, and international income tax filings, annual audits, sales tax reporting and remittance, and strategic tax planning. This role will report to the VP of Finance and key external partners. | — | 0 |
| SoC Physical Design Verification Engineer Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes. Responsibilities include leading physical verification closure, debugging issues, and collaborating with cross-functional teams to achieve successful tapeouts. | — | 0 |
| Engineering Program Manager, RISCV Tenstorrent is seeking an Engineering Program Manager to lead their RISC-V CPU team, driving the full lifecycle of high-performance CPUs from spec to tapeout and post-silicon debug. This role involves cross-functional collaboration across architecture, design, verification, and DFT, with a focus on program management, risk management, and milestone delivery. Experience with Functional Safety standards like ISO 26262 is desirable. The role is hybrid and open to various experience levels. | — | 0 |
| Staff Technical Program Manager, Physical Design This role is for a Technical Program Manager with physical design expertise to drive the execution of AI/ML and CPU processor projects. The TPM will lead cross-functional teams, manage complex schedules across multiple chiplets, and interface between internal teams and external partners, focusing on the delivery of next-generation AI silicon. | — | 0 |
| Staff Physical Design Engineer – EMIR This role focuses on the physical design and EMIR (Electromigration and IR-drop) analysis for high-performance ICs, specifically for AI chips and RISC-V CPUs. The engineer will ensure robust power delivery, signal integrity, and long-term reliability, working with RTL and physical design teams on advanced technology nodes. | — | 0 |