AMD currently has 35 active AI-related job listings. The majority of these roles, 66%, are focused on serving infrastructure. Engineering is the dominant function, with 32 positions. Frequent technical tags include model_serving, inference_infra, and evals, suggesting a focus on the deployment and evaluation of AI models. In the last 30 days, AMD posted 37 new AI roles.
AMD currently has 59 active AI-related roles in our index. The most common open titles are: DC-GPU Performance Modeling Engineer (3), Sr. Software Development Engineer (3), Data Center Engineer (2), MTS Software Development Engineer (2), Software Development Engineer (2). Most positions are in Engineering and Research.
AMD's active AI hiring is concentrated in: serving infrastructure (78%), data (10%), agents (5%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
AMD is hiring AI talent in: United States (30 roles), India (13 roles), Poland (5 roles), China (5 roles).
Job postings at AMD most frequently mention: GPU Computing, Computer Architecture, Python, C++, PyTorch.
In the past 30 days, AMD has posted 70 new AI-related roles.
| Title | Stage | AI score |
|---|---|---|
| Software Development Engineer - Contract Software Development Engineer at AMD focused on developing and customizing diagnostics solutions for CPU, APU, and dGPU platforms. The role involves system-level validation, hardware-software intersection, and collaboration with cross-functional teams. While AI/ML methodologies are mentioned as a potential area for efficiency improvements, the core function of the role is not AI/ML development. | — | 0 |
| Principal Linux Systems Architect This role is for a Principal Linux Systems Architect at AMD, focusing on x86 computing architecture and Linux system software. The architect will drive end-to-end platform and software architecture, set technical direction, and solve complex system-level challenges across hardware, firmware, OS, virtualization, and application layers. Responsibilities include defining system software and platform architecture, driving technical strategy, leading architecture reviews, architecting Linux kernel and low-level system software, providing technical leadership for system bring-up and performance optimization, and leading root-cause analysis. The role also involves interfacing with open-source communities and external partners. |
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| RTL/Logic Design Engineer This role is for an RTL/Logic Design Engineer at AMD, focusing on the Graphics Memory Controller (GMC) IP for Discrete GPUs and Instinct accelerators. The engineer will participate in architecture and micro-architecture specifications, perform RTL coding for new features, and work with verification engineers. The role requires experience in digital design, high-speed memory interfaces (HBM, GDDR), Verilog, and industry-standard CAD tools, with a focus on meeting timing, power, and area requirements. | — | 0 |
| DFx Methodology Architect AMD is seeking an experienced DFx Architecture, Methodology and Logic Design Expert to own and drive DFx Architecture definition, RTL implementation, and methodology development for FPGA-SoCs and custom ASICs. The role involves defining and implementing DFx features in RTL, co-owning timing and design quality checks, and working cross-functionally with various engineering teams. Experience with Siemens Tessent DFT flows and strong logic design/timing fundamentals are preferred. | — | 0 |
| HSIO Validation Execution Engineer This role focuses on the post-silicon validation of high-speed IO for AMD's datacenter CPU and AI GPU systems. The engineer will develop and execute test plans, create test content, develop validation infrastructure, and collaborate with cross-functional teams to debug platform and SoC issues. The role requires expertise in high-speed IO interfaces like PCIe and CXL, server platform components, and strong debug skills. While the role supports AI GPU systems, the core function is validation engineering for hardware infrastructure, not AI model development or deployment. | — | 0 |
| Lead Analog Mixed-Signal Design Engineer Lead Analog Mixed-Signal Design Engineer at AMD in Bangalore, India, with 8+ years of experience in semiconductor IP design and development. Responsibilities include leading a design team, schedule planning, cross-functional collaboration, and contributing to analog circuit architecture. Requires hands-on experience in high-speed PHY/IO designs, FinFET nodes, and AMS EDA tools. Master's degree in electrical engineering required, PhD preferred. | — | 0 |
| DFT Verification Engineer This role is for a DFT Verification Engineer focused on SoC design verification for server programs. The responsibilities include developing testbenches, debugging complex issues, and ensuring the quality of silicon designs. While the company mentions AI and uses AI in its hiring process, the core craft of this role is not AI/ML model development or deployment. | — | 0 |
| Principal Physical Design Lead - CPU This role is for a Principal Physical Design Lead focused on CPU design at AMD. The responsibilities include driving the physical design of critical CPU units from RTL to GDSII, including synthesis, floor-planning, place and route, timing closure, and signoff. The role requires deep expertise in physical design methodologies, PPA tradeoffs, and various PNR tools, with a focus on high-performance designs and advanced sub-7nm nodes. While the company mentions AI and next-generation computing, the core function of this role is traditional CPU physical design engineering, not AI/ML model development or deployment. | — | 0 |
| Design Verification Engineers This role is for a Design Verification Engineer at AMD, focusing on high-performance x86 microprocessor cores. The responsibilities include architecting and developing testbenches, test plans, and ensuring functional coverage for complex designs. The role requires experience in ASIC design verification, SystemVerilog, and microprocessor ISAs. | — | 0 |
| Physical Design Engineer Seeking a Senior Silicon Design Engineer to join the GPU design team, focusing on the physical design of high-speed microprocessors using advanced CMOS technologies. Responsibilities include driving design implementation, executing PnR, analyzing design results, and collaborating with cross-functional teams. | — | 0 |
| SR Design Verification Engineer This role is for a Senior Design Verification Engineer at AMD, focusing on advanced data center networking technology. The engineer will be responsible for developing and executing verification strategies for complex ASIC designs, including IP, subsystem, and SoC levels. Key responsibilities involve UVM-based testbench development, execution, debugging, and collaboration with cross-functional teams. The role requires strong SystemVerilog and UVM expertise, experience with industry protocols, and scripting skills. | — | 0 |
| Executive Assistant Executive Assistant role supporting the AI SW group leadership team at AMD. Responsibilities include calendar management, travel arrangements, expense reporting, interfacing with management and customers, handling inquiries, maintaining files, preparing reports, ordering supplies, and supporting financial processes. Requires strong organizational, multi-tasking, and confidentiality skills, with the ability to gather information and make decisions independently. Experience with AI-assisted solutions for data analysis and trend identification is preferred, along with a willingness to adapt to new AI technologies. | — | 0 |
| Post Silicon Validation Application Engineer This role is for a Post Silicon Validation Application Engineer at AMD, focusing on technical customer interface, SoC/IP bring-up, validation, debug, and issue resolution. It requires significant experience in post-silicon validation, lab equipment, scripting, and system architecture. The role involves collaborating with internal teams and supporting customer environments, with preferred skills in customer-facing roles and high-speed interfaces. | — | 0 |
| DFT Engineer DFT engineer will lead a strong engineering team on Scan, MBIST, iJTAG test development of latest AMD products. The IPs range from complex processors, AI computation blocks, to state-of-the-art controller IPs which provide automotive, data center, machine learning and high-speed communication solutions. You will work closely with designers to make sure DFT structures are correctly implemented, with test engineers to make sure ATE test programs can be generated from the DFT (ATPG, MBIST) tools, with product engineers to make sure scan/MBIST production test can run seamlessly and stable, and with yield engineers to debug and root-cause failures/defects. You will get the opportunity to expand technical knowledge beyond DFT into embedded processor firmware, complex chip simulation, RTL implementation for ASIC & FPGA and deep silicon debug works all the way to high-volume production requirement. This is the role to oversee complete silicon cycle from design to production phases. | — | 0 |
| Data Center Technician This role supports servers in customer data centers, focusing on hardware setup, diagnostics, troubleshooting, and decommissioning. It involves following standard procedures, ensuring quality checks, and contributing to documentation and team environment. The role requires strong technical skills in hardware, IT, and cabling management, with a focus on attention to detail and results-driven attitude. | — | 0 |
| Senior Compiler Engineer, GPU Code Object Rewriting & Tooling This role focuses on building next-generation infrastructure for predicting, explaining, and improving AMD GPU kernel performance. It involves creating performance-estimation systems using various data sources like ISA, compiler output, and simulator traces. The engineer will model key performance drivers, validate predictions against hardware and simulators, and partner with other teams to optimize hardware, compilers, and kernels. While ML-assisted modeling is mentioned as an exploration area, the core of the role is in GPU performance modeling, compiler analysis, and microarchitecture, not direct AI/ML model development as the primary output. | — | 0 |
| SoC Architect AMD is seeking a SoC Architect to join their AECG x86 Embedded Team. This role will focus on defining and driving cutting-edge SoC designs for embedded and commercial applications, working across silicon, firmware, and software. Responsibilities include leading SoC architecture, owning platform power and reset, defining SOC features, static timing analysis, high-speed I/O architecture, performance/power/reliability modeling, functional safety, and cross-functional leadership. The ideal candidate will have experience in X86, GPU, interconnect, HSIO, and Memory subsystems architecture, with a background in embedded markets and SOC design. | — | 0 |
| SoC Security Architect AMD is seeking a Security Architect to design and develop system security architectures for their client and gaming products. The role involves defining security specifications, conducting threat modeling, and collaborating with hardware, software, and firmware teams. Experience with secure boot, confidential computing, and cryptography is preferred, with a mention of AI/ML security implications in hardware systems. | — | 0 |
| Field Application Lead Engineer Field Application Lead Engineer responsible for technical support of AMD's embedded products (FPGA, embedded x86) to customers in India. Focus on pre-sales and development support, building technical relationships, and resolving technical escalations. Requires strong technical knowledge in embedded systems, microprocessors, and FPGAs, with excellent communication and problem-solving skills. | — | 0 |
| Sr. Test Engineer This role is for a Senior Test Engineer at AMD, focusing on developing wafer sort test solutions for AECG products. The engineer will lead pre-silicon test planning, drive post-silicon bring-up and debug, and own wafer sort test solution development from concept to high-volume manufacturing. Responsibilities include developing test programs, defining test flows, executing silicon bring-up, performing failure analysis, and optimizing test efficiency. The role requires strong fundamentals in digital/analog circuits, semiconductor test engineering, programming/scripting, and data analysis. | — | 0 |
| Sr. Manufacturing Engineer - Thermal This role is for a Sr. Manufacturing Engineer focused on thermal aspects of ASIC testing and assembly. It involves managing test equipment, analyzing hardware performance, debugging failures, optimizing maintenance, and driving continuous improvement in collaboration with global teams and OSAT partners. While the company mentions AI as a future direction, this specific role is in manufacturing operations and does not directly involve building or researching AI/ML models. | — | 0 |
| Staff Product Development Engineer – ATE Test Engineering Staff Product Development Engineer focused on ATE Test Engineering for Enterprise New Product Introduction (NPI) of next-generation processors for high-performance computing, data centers, and enterprise servers. Responsibilities include developing ATE test programs and hardware, ensuring content development and bring-up, evaluating and releasing robust test programs for production, and improving key performance indicators like test time and yield. | — | 0 |
| Failure Analysis Engineer - Power & Design Failure Analysis Engineer - Power & Design at AMD, focusing on GPU accelerators. Responsibilities include PCB triage, power delivery debug, board-level fault isolation, developing debug strategies, running diagnostics, and collaborating with design, validation, FW, and manufacturing teams to accelerate root cause analysis and corrective actions. The role requires strong electrical engineering fundamentals, hardware design, board bring-up, and electrical debug expertise. | — | 0 |
| Operations Manager Operations Manager role at AMD focused on leading warehouse and operational execution, ensuring performance, compliance, and scalability. The role involves structured problem solving, process standardization, continuous improvement, and managing material flows across inbound, internal, and outbound activities. It requires compliance with safety and shipping regulations and collaboration with cross-functional teams and external logistics providers. | — | 0 |
| CPU Tools and Diagnostics Development Engineer Develop, enhance, and maintain stress tools for AMD CPUs, collaborating with design teams and participating in silicon validation efforts. This role focuses on software engineering for hardware development tools. | — | 0 |
| Failure Analysis Engineer - Power & Thermal AMD is seeking a Failure Analysis Engineer focused on Power and Thermal issues for GPU accelerators. This role involves PCB triage, board-level fault isolation, developing debug strategies, running tests, and collaborating with design, validation, FW, and manufacturing teams to identify root causes and implement corrective actions. The engineer will analyze power behavior, thermal analysis, and liquid-cooling performance, documenting findings and presenting them to stakeholders. Experience with hardware debug, power/thermal analysis, liquid cooling, PCB triage, scripting (Python), and firmware is preferred. | — | 0 |
| System Performance Modeling Engineer Develop high-performance models for ASIC verification, architecture validation, and software development acceleration. Requires C/C++, SystemC, and ARM fast models expertise. | — | 0 |
| Senior DevOps/SRE Engineer AMD is seeking a Senior DevOps/SRE Engineer to improve developer experience and release quality builds for their open-source software stack, which supports inference and training workloads. The role involves developing and maintaining CI/CD pipelines, leading SRE activities, modernizing developer workflows, and contributing to release packaging. The engineer will work with the latest hardware and software technology and lead a small team. | — | 0 |
| IOMMU Design Verification Engineer AMD is seeking an ASIC Design Verification Engineer to join their IOHUB Team. The role involves all aspects of IP verification, including architecture, test plans, environment development, and closure. The engineer will work on leading-edge I/O connectivity and virtualization technologies for data center and machine learning workloads. | — | 0 |
| MPM for Mechanical Engineer This role focuses on supplier quality management, NPI readiness, manufacturing process control, and reliability validation for AI server platform components, specifically cables, connectors, mechanical parts, and liquid cooling technologies. It involves working with engineering, manufacturing, and suppliers to ensure product qualification and mass production readiness. | — | 0 |
| Electrical Characterization Engineer This role is for a Senior Systems Design Engineer at AMD, focusing on improving AMD's capabilities in product development, validation, and root cause resolution. The engineer will drive technical innovation, develop tools and scripts, enhance methodologies, and work with multiple teams to ensure features are validated and optimized. The role involves debugging issues across different phases of SOC programs and engaging with software/hardware modeling frameworks. Programming/scripting skills and experience with lab equipment and board-level debug are preferred. | — | 0 |
| Senior Lead Verification Engineer This role is for a Senior Lead Verification Engineer at AMD, focusing on verifying complex design blocks at the IP, Sub-system, or SoC level using System Verilog/UVM. The engineer will develop and enhance testbenches, interact with various design teams, and mentor junior engineers. Experience in ASIC verification, developing verification environments, and scripting is preferred. | — | 0 |
| Senior Lead Verification Engineer Senior Lead Verification Engineer at AMD, focusing on verifying complex designs for client, server, graphics, and semi-custom interconnects using System Verilog/UVM. The role involves developing and enhancing testbenches, collaborating with design and validation teams, and mentoring junior engineers. Requires strong ASIC verification experience and architectural understanding of verification environments. | — | 0 |
| Senior Lead Verification Engineer Senior Lead Verification Engineer at AMD, focusing on front-end design/integration for cutting-edge hardware, including AI and data centers. Responsibilities include developing and enhancing System Verilog/UVM testbenches, collaborating with various engineering teams, and mentoring junior engineers. Requires extensive experience in ASIC verification and testbench development. | — | 0 |
| Sr. Snowflake Data Engineer - Finance Lead Snowflake Data Engineer for AMD's CFO organization, responsible for designing and evolving the Finance data ecosystem. This role involves building scalable data products for financial reporting and decision-making, partnering with business and IT teams, mentoring Citizen Data Engineers, and maturing the data product portfolio. The candidate needs strong Snowflake expertise, SQL skills, and understanding of Finance data, with experience integrating enterprise data environments. | — | 0 |
| UEFI/BIOS Firmware Engineer This role is for a UEFI/BIOS Firmware Engineer at AMD, focusing on server products and the EPYC line. The engineer will develop and deploy firmware solutions, collaborate with cross-functional teams, and ensure customers can leverage EPYC designs. Responsibilities include designing and developing platform BIOS, participating in triage and debug processes, and writing high-quality C/ASM code. Experience with x86 system architecture, server hardware interfaces, and AMI AptioV BIOS is preferred. | — | 0 |
| Failure Analysis Engineering Manager, GPU ASIC and PCBA Debug AMD is seeking an experienced Failure Analysis Engineering Manager for their GPU ASIC and PCBA Debug team. This role involves leading and developing a team of FA engineers, overseeing customer and factory failure investigations, and driving root cause analysis and corrective actions. The manager will provide technical leadership for debug and triage of complex GPU and PCBA failures, drive debug automation, and ensure clear documentation of findings. The role requires strong people management skills, technical expertise in GPU ASIC and board-level failure analysis, and experience in hardware verification and system integration. | — | 0 |
| Memory Subsystem Architect and Design Engineer This role focuses on the hardware architecture and design of memory subsystems for next-generation network hardware, particularly within an AI-driven roadmap. Responsibilities include leading architecture, bring-up, root cause analysis, debugging of memory issues (DDR5/DDR4), collaborating with IP vendors and board designers, and identifying hardware improvements. While the roadmap is AI-driven, the core function is hardware engineering, not AI/ML model development. | — | 0 |
| SENIOR ARCHITECT SOFTWARE DEVELOPMENT ENGINEER This role is for a Senior Architect Software Development Engineer at AMD, focusing on improving the performance of key applications and benchmarks. The responsibilities include leading the development of automation frameworks, designing APIs, deploying applications in containerized environments, managing cloud solutions, and supporting post-silicon validation efforts. The role requires strong programming skills in Java or Python, experience with web services, CI/CD, and cloud platforms like Azure. While the company mentions AI and data centers, the core responsibilities of this specific role are in general software development and engineering, not directly building or researching AI models. | — | 0 |
| Customer Quality Engineer (CQE) Experienced Customer Quality Engineer (CQE) to manage customer-facing quality, drive resolution of product/field issues, and act as a technical interface between customers and internal teams, ensuring product quality and reliability throughout the product lifecycle. Responsibilities include managing customer communications for nonconformances, leading structured problem-solving (8D), monitoring key metrics, and partnering with engineering teams for root cause analysis. | — | 0 |
| Product Development Engineer This role is for a Product Development Engineer in AMD's New Product Introduction (NPI) test engineering team, focusing on defining and providing test solutions for AMD's Data Center Graphics (DCG). The engineer will be responsible for defining and driving System Level Test (SLT) solutions to meet business milestones, cost, and quality targets, collaborating with various engineering teams to ensure product quality and cost-effectiveness. The role involves complex problem-solving, developing SLT logging and data collection flows, and potentially providing technical supervision. | — | 0 |
| Strategic Sourcing Manager This role is for a Strategic Sourcing Manager at AMD, focusing on New Product Introduction (NPI) for Datacenter Platform Engineering. The manager will be responsible for procurement of power solutions (AC-DC, BBU, PWR-Rack) and ensuring supply chain readiness, risk mitigation, and collaboration with engineering teams. The role requires strong analytical and communication skills, proficiency in supply chain principles, and experience with NPI management. | — | 0 |
| STA Lead This role is for a Full Chip SoC Timing Lead responsible for ASIC/SoC design implementation and timing closure. The candidate will lead timing activities from synthesis through place-and-route, signoff, and tapeout for complex SoCs in advanced technology nodes. This requires deep expertise in STA, timing constraints, MMMC flows, SI/crosstalk analysis, and ECO closure. | — | 0 |
| Senior Server System Platform Hardware Architect This role is for a Senior Server System Platform Hardware Architect at AMD. The primary focus is on defining and driving platform level socket pinout and floor planning, developing product specifications, and collaborating with internal teams, customers, and ecosystem vendors. While the company mentions AI acceleration as a goal, the core responsibilities are in hardware architecture and system design, not AI/ML model development or deployment. | — | 0 |
| Fullchip Floorplan Design Engineer This role is for a Fullchip Floorplan Design Engineer at AMD, focusing on translating SoC RTL into a full-chip floorplan. The engineer will define chip-level structure, manage partitioning, macro placement, integration, and collaborate with various design teams. The role requires expertise in full-chip floorplanning and physical design, using tools like Fusion Compiler/Innovus, and building automation scripts. | — | 0 |
| HSIO Validation Lead - Data Center GPU Lead/Principal Systems Design Engineer for AMD's Data Center GPU products, focusing on validation, tool development, and technical innovation to ensure high-quality product delivery. | — | 0 |
| Compiler Performance Engineer This role is for a Senior Compiler Performance Engineer at AMD, focusing on improving the performance of applications and benchmarks on AMD platforms by analyzing compiler-generated code, refactoring code for optimizations, and working with compiler specialists. The role involves identifying performance bottlenecks, researching efficient methods, and contributing to open-source projects. While the company mentions AI and its own AI policy, this specific role is centered on general compiler performance engineering, not AI model development or research. | — | 0 |
| Performance Modeling Architect This role focuses on analyzing and optimizing high-performance memory subsystem designs for various computing applications, including AI acceleration. The responsibilities include micro-benchmarking, workload characterization, competitive analysis, bottleneck identification, and optimization, as well as developing tools and methodologies for performance analysis. Experience with CPU, GPU, or computer system microarchitecture and performance models is preferred. | — | 0 |
| CPU Architecture and RTL Design Lead Engineer This role is for a CPU Core Architect/RTL Design Engineer focused on Clocking, Reset, and Power for next-generation AMD CPUs. The engineer will drive the definition, implementation, and integration of these components, working collaboratively with a skilled engineering team. Responsibilities include microarchitecture definition, design delivery from concept to tapeout, static timing, CDC/Gate CDC, and static power analysis, as well as identifying customer challenges and making technical contributions for performance, frequency, and power efficiency. | — | 0 |
| Executive Assistant This role is for an Executive Assistant at AMD, supporting a Corporate Vice President. The responsibilities include managing the executive's calendar, coordinating travel and meetings, handling correspondence, maintaining files, and supporting financial processes. The ideal candidate has significant experience in a C-suite environment, strong organizational and multi-tasking skills, and the ability to work independently. The role is hybrid and can be based in Austin, TX or Santa Clara, CA. | — | 0 |