Intel

Process and Equipment Engineer at Intel in Malaysia, responsible for optimizing high-volume manufacturing equipment and processes for integrated circuit production. This role involves ensuring precision, quality, cost efficiency, and technology scaling, with opportunities for global process transfer and continuous improvement.

Process and Equipment Engineer at Intel in Malaysia, focusing on optimizing high-volume manufacturing equipment and processes for integrated circuits. Responsibilities include testing, defect minimization, implementing process modifications, building capacity, executing maintenance, developing excursion prevention systems, managing equipment installation, and collaborating with cross-functional teams for technology transfer.

This role is for a Graduate Talent (Physical Design Engineer) at Intel, focusing on Foundational IP (FIP) integration QA within the Foundry Technology Development group. The responsibilities include using industry standard tools for RTL to GDS design flow, scripting and automation, developing new IP-level quality checks, and interacting with EDA tool vendors and internal IP development teams. A key aspect involves applying data analytics and AI/ML techniques to optimize processes and improve quality.

Industrial Engineer specializing in automation for semiconductor manufacturing, focusing on designing and implementing solutions to enhance operational efficiency. The role involves programming (Python), data management (SQL, NoSQL), data analysis, process optimization, and utilizing visualization tools.

Develops and executes product qualification strategies and plans, ensuring adherence to release criteria. Performs risk assessments, defines quality and reliability goals, and contributes to the development and validation of components, boards, and systems. Analyzes specifications, ensures manufacturability, and resolves quality issues. Monitors post-silicon quality results and drives improvements for future products.

Internship role supporting the design, development, and validation of platform hardware and board-level solutions, focusing on component evaluation, PCB layout reviews, and electrical analysis. Requires collaboration with cross-functional teams and application of signal integrity and hardware design principles.

This role focuses on the functional verification of CPU logic, ensuring design specifications are met. Responsibilities include developing IP verification plans, test benches, and simulation models, debugging issues in the presilicon environment, and collaborating with design and architecture teams. The role requires experience with hardware modeling languages and validation/debug experience.

Facilities Mechanical and Controls Engineer responsible for ensuring the reliability, performance, and safety of mechanical, HVAC, and control systems in critical environments. This role involves system design, analysis, troubleshooting, project development, and oversight of integrated facilities management partners and external vendors. Requires a Bachelor's degree in Mechanical Engineering and 5+ years of experience with mechanical and control systems.

Designs, develops, and executes power and performance plans for IPs and SoCs. Identifies, builds, and maintains power, thermal, performance/watt optimizations, and characterizations for IPSoC power and performance goals. Conducts feature analysis from power and performance standpoint and drives to close any gaps between observed behavior and target on platforms in development. Provides recommendations for future architectures. Develops and enhances innovative tools for architectural performance analysis. Develops methodologies and models to drive continuous improvements in optimization of power and performance configurations to meet market requirements. Ensures platform and its components are optimized for performance and power balance. Identifies power activity zones and works with design, architecture, binning/technology, and manufacturing teams on ways to meet power consumption goals. Works cross functionally on analysis, validation, and tuning of architectures and features that advance the state of art in performance and efficiency.

RTL Design & Micro-Architecture Engineer for next-generation scalable data centers supporting AI workloads. Responsibilities include RTL design, coding, simulation, integration, and verification of SoC designs. Requires System Verilog, digital design fundamentals, and simulation tools.

This role involves performing technical power and voltage regulator validation, conducting engineering tests, and supporting engineering activities for Intel's data center innovations. Responsibilities include using lab instrumentation, reading schematics, and maintaining lab operations. The role requires an Associate's degree or higher in Electronics or a similar technical discipline, with at least 1 year of experience in platform rework, soldering, and using oscilloscopes. Intermediate English proficiency is also required.

Experienced Facilities Electrical Engineer responsible for the reliability and continuous improvement of Mega plant electrical systems, including electrical distribution, Medium Voltage systems, low voltage Centre, UPSs, Emergency Generator, and VFDs, supporting safe, reliable, and efficient plant operations. Collaborates with local and global teams to ensure consistency with global standards.

This role focuses on developing and supporting Process Design Kits (PDKs) for Intel Foundry, specifically involving physical layout verification (DRC, LVS, RC extraction) and ESD protection verification using industry-standard EDA tools. The engineer will work on runset development, QA plans, debugging, and enhancing runset quality and usability for advanced Intel process technologies.

This role focuses on developing and supporting Process Design Kits (PDKs) for Intel Foundry, specifically involving physical layout verification (DRC, LVS, RC extraction) and ESD protection verification using industry-standard EDA tools. The engineer will work on runset development, QA plans, debugging, and enhancing runset quality and usability for advanced Intel process technologies.

Senior CPU Physical Design Engineer responsible for the design and delivery of high-performance CPU blocks from RTL to GDS, including synthesis, floorplanning, place and route, CTS, timing closure, and verification. Requires 10+ years of experience with industry-standard EDA tools.

This role is for a CPU Physical Design Engineer at Intel, focusing on the design and delivery of high-performance CPU blocks from RTL to GDS. Responsibilities include executing the full physical design flow, leading verification and sign-off, and optimizing designs for power, performance, and area using industry-standard EDA tools. The role requires a BSc or MSc degree in Electrical or Computer Engineering and at least 7 years of experience in physical design.

The role involves designing, executing, and analyzing experiments in a semiconductor cleanroom to meet engineering specifications for advanced device development. Responsibilities include setting performance targets, assessing silicon readiness, defining test structures, and using data analysis techniques (statistics, data mining) on electrical-test, yield, and fab data to guide future development. Experience with semiconductor materials, fabrication, device physics, and electrical characterization is required, with preferred experience in advanced transistor structures, simulation, SPC/DOE, and analytics/scripting languages.

This role is for a pre-silicon verification engineer on the E-Core CPU team. The primary responsibility is to verify new and existing features for Intel's next-generation CPU IP by developing test plans, test scenarios, simulation components, and functional coverage, and debugging digital simulations. The role requires in-depth computer architecture knowledge and experience with hardware description languages and test bench development.

The Director of US Government Affairs will manage outreach to the Executive Branch and Congressional Republicans to advocate and shape policies that advance American semiconductor manufacturing and technology leadership. This role involves federal lobbying efforts, advocating for Intel's positions on critical policy issues, and leading lobbying efforts on technology issues like Quantum Computing, Cybersecurity, and Data.

This role is for a Director of US Government Affairs at Intel, focusing on lobbying the Executive Branch and Congressional Republicans to advocate for policies supporting American semiconductor manufacturing and technology leadership. The responsibilities include crafting and executing federal lobbying efforts, advocating for Intel's positions on critical policy issues, leading lobbying efforts on export controls and investment restrictions, and building relationships with policymakers. The role requires at least 7 years of experience in federal government affairs, with a focus on manufacturing policy, and a strong legislative background.

Senior Facilities Electrical Engineer to lead electrical infrastructure projects and maintain critical electrical systems across Intel's facilities in Malaysia. Responsibilities include designing, implementing, and optimizing electrical systems, ensuring safety, reliability, and compliance with codes and standards. Requires a Bachelor's degree in Electrical Engineering and 7-10 years of experience.

Senior/Staff VLSI Verification Engineer with 11-15 years of experience in complex SoC/ASIC verification, focusing on UVM/System Verilog testbench architecture, Mix signal IP verification strategy, and post-silicon debug. Responsibilities include defining verification plans, mentoring junior engineers, ensuring coverage closure, and collaborating with architects. Experience with formal verification methods is also required.

Intern position focused on platform debug engineering for silicon products, involving functional, power, and performance validation, debugging, and potentially test automation and infrastructure development. Requires familiarity with Python, C/C++, and IA-based PC knowledge. AI experience is preferred but not core.

This role is for a Graduate Talent (Physical Design Engineer) at Intel, focusing on Foundational IP (FIP) integration QA within the Foundry Technology Development group. The responsibilities include using industry standard tools for RTL to GDS design flow, scripting and automation, developing new IP-level quality checks, and interacting with EDA tool vendors and internal IP development teams. A key aspect involves applying data analytics and AI/ML techniques to optimize processes and improve quality.

Lead a team responsible for pre-Silicon functional verification of Intel's latest CPUs, developing test plans, simulation models, and test benches to ensure design requirements are met. Focus on driving strategic tool/flow/methodology initiatives to reduce validation cycle time and ensure first-pass silicon success. Requires technical leadership and managerial experience in pre-Silicon verification environments.

This role focuses on owning and optimizing high-volume manufacturing equipment and processes in the semiconductor industry. Responsibilities include recommending modifications for efficiency, managing maintenance and repair, driving continuous improvement for key performance indicators, and participating in technology transfer to global sites. The role also involves developing excursion prevention systems and managing equipment installation and qualification during factory ramps.

This role focuses on designing, deploying, and managing enterprise-grade Public Key Infrastructure (PKI) solutions, including certificate lifecycle management and automation. It involves integrating PKI with Active Directory and other identity solutions, and ensuring compliance with regulatory requirements. The role requires a strong understanding of X.509 certificates and related protocols.

This role focuses on the Design Technology Platform (DTP) within Intel Foundry Technology Development, specifically in enabling and optimizing EDA reference flow and design flow for advanced process technology. The engineer will work on front-end and back-end design aspects (RTL to GDS, digital/analog, physical design, verification, signoff) and apply AI/ML, CAD software, and data analytics to solve complex problems. The role requires proficiency in Python, C++, TCL, and SKILL, with a background in Electrical Engineering, Computer Engineering, or related STEM fields, and knowledge of VLSI Physical Digital or Custom Design implementation concepts.

Senior Member of Technical Staff (CMP) Engineer at Intel Foundry responsible for driving module ownership and technical leadership in Chemical Mechanical Planarization (CMP) process development for advanced logic technologies. This role involves leading process development from concept to HVM implementation, cross-node standardization, problem resolution, and customer-centric delivery.

This role is a Chief of Staff/Technical Assistant for Intel's Central Engineering Group (CEG), focusing on strategic initiatives, operational excellence, and stakeholder management. It requires strong business acumen, program management skills, and a deep understanding of Intel's technology and business strategies, but is not directly involved in AI/ML development.

Senior Network Systems and Solutions Engineer to support Intel Ethernet products, focusing on technical enablement, debug, and issue resolution for discrete Ethernet controllers and integrated Ethernet IP on SOC. Requires strong analytical, problem-solving, and customer management skills, with experience in high-speed IO debug methods like PCIe or Ethernet.

System Firmware Engineer responsible for developing, maintaining, and optimizing reusable components for seamless integration across Intel's client technology ecosystem. This role involves partnering with customers and vendors, establishing architecture standards, researching and prototyping firmware, evangelizing tools, and driving product improvements. Requires expertise in system firmware, software debug, and low-level software engineering.

Senior Process Engineer - Dry Etch role focused on technology development and manufacturing of semiconductor fabrication processes, specifically dry etch for advanced nodes like 18A and GAA FETs. Responsibilities include process integration, optimization, feasibility studies, and collaboration with development and manufacturing teams to support foundry customers.

Senior Metals Deposition Engineer role focused on driving process performance and manufacturability for advanced metals deposition modules in semiconductor manufacturing. This role involves bridging Technology Development, High Volume Manufacturing, and Customer Engineering, requiring technical problem-solving, collaboration across teams, and staying current with industry trends.

Program Manager for Advanced Packaging technology, focusing on supplier capacity expansion and qualification to meet foundry customer demand for EMIB-T technology. Requires project management, technical risk assessment, and supplier management skills.

Senior Manager role in Intel's Capital Markets Group, managing a $50B debt portfolio, asset liability management, shareholder distributions, credit facilities, and relationships with credit rating agencies and banking partners. Responsibilities include capital structure planning, board presentations, and ensuring regulatory compliance in collaboration with legal, tax, and accounting teams. Requires strong financial analysis, problem-solving, and communication skills.

This is an account sales role focused on driving Intel product adoption, building customer partnerships, and generating revenue. Responsibilities include account planning, identifying growth opportunities, converting design wins to revenue, and gathering customer feedback. It requires understanding customer technology and business strategies, and translating needs into technical value propositions. The role is commissioned and directly tied to revenue generation and customer success.

Senior Account Sales Manager responsible for leading a sales team, understanding customer technology needs, building partnerships, and securing design wins to drive revenue and expand Intel's product adoption. This role focuses on account planning, revenue generation, customer feedback analysis, and influencing customer decisions for long-term growth.

Director of Analog Design & Infrastructure Design Automation to lead the development, deployment, and governance of analog/mixed-signal design environments and CAD infrastructure. This role owns EDA tool ecosystems, PDK integration, compute infrastructure, design data governance, and tapeout manifest management to ensure high productivity, reproducibility, and audit readiness across silicon programs.

This role focuses on optimizing Intel's new Graphics Processing Units (GPUs) for modern workloads, emphasizing 3D graphics rendering, workload analysis, hardware/software debugging, and performance bottleneck identification within a multi-disciplinary team.

This role involves the design, development, verification, and delivery of standard cell libraries for Intel's next-generation SoCs and Intel Foundry customers, utilizing leading-edge process technologies. Responsibilities include circuit design, parasitic extraction and optimization, automation flow development, library characterization, and supporting library releases for product teams and external customers. The ideal candidate will have a degree in Electrical Engineering or a related field, knowledge of digital circuit design, familiarity with EDA tools, and scripting experience.

This role involves the design, development, verification, and delivery of standard cell libraries for Intel's next-generation SoCs and Intel Foundry customers, utilizing leading-edge process technologies. Responsibilities include circuit design, parasitic extraction and optimization, automation flow development, library characterization, and supporting library releases for product teams and external customers. The ideal candidate will have a degree in Electrical Engineering or a related field, knowledge of digital circuit design, familiarity with EDA tools, and scripting experience.

This role involves the physical design implementation of custom IP and SoC designs from RTL to GDS, covering synthesis, place and route, timing analysis, power distribution, reliability, and verification/signoff. It also includes optimizing designs for power, frequency, and area, and contributing to the development of physical design methodologies and flow automation.

Designs, develops, and builds custom digital circuits for a CPU, including memory and caches. This involves floorplanning, schematic entry, simulation, and verification to optimize for power, performance, area, timing, and yield. The role also includes creating DFT models, developing memory test tools, and collaborating cross-functionally to resolve design issues. Familiarity with EDA tools and advanced CMOS technology is required.

The GPU Validation Engineer role at Intel focuses on the pre-silicon validation of GPUs, including their interaction with media, display, and system-level features. The role involves defining, developing, and performing functional validation, applying various tools and techniques to meet performance, power, and area goals. Responsibilities include reviewing design changes, developing validation methodologies, executing validation plans, debugging pre-silicon issues, influencing validation infrastructure, publishing reports, and collaborating with architecture, design, verification, and platform teams.

The Accounting Technical Specialist role at Intel in Malaysia focuses on end-to-end statutory audit processes, governmental filings, ensuring compliance with accounting standards (IFRS, US GAAP), managing month-end/quarter-end close activities, and acting as a technical advisor for complex accounting issues and upcoming regulations. The role also involves supporting legal entity restructuring, collaborating with internal stakeholders, leading projects, and potentially participating in SAP S4 system design and implementation.

Senior CPU Verification Engineer responsible for ensuring the functional correctness of CPU logic designs through pre-silicon verification methodologies, including developing UVM-based testbenches, running simulations, debugging issues, and collaborating with architects and designers.

Memory Design Graduate Talent role at Intel, focusing on pathfinding, development, and optimization of advanced memory technology and circuits. Responsibilities include DTCO, product enablement, IC layout, memory array/IP design, circuit innovation, and pre/post-Si validation.

Practical Engineering student role in a semiconductor manufacturing facility, focusing on operating and supporting advanced equipment, learning maintenance, and assisting engineering teams with troubleshooting and process improvement. Requires enrollment in a Mechanical or Mechatronics Practical Engineering program with at least three semesters remaining.

Seeking a Thermal Intern to support thermal engineers with lab testing, data collection, and documentation. Responsibilities include assisting with thermal modeling setup, analyzing airflow and temperature data, and documenting results. The role involves working within a cross-functional Architecture/Engineering team focused on Co-Engineering Custom Design Systems with strategic customers and driving new platform-level innovations.