Currently tracking 440 active AI roles, down 53% versus the prior 4 weeks. Primary focus: Serve · Engineering. Salary range $100k–$575k (avg $262k).
NVIDIA currently has 496 active AI-related job listings. The majority of these roles, 52%, are focused on serving infrastructure, with agents representing another significant segment at 23%. Engineering is the dominant function, with 441 positions. The United States leads hiring geographies with 287 roles, followed by China with 64. Frequent tech tags include model_serving, inference_infra, and agent_orchestration, suggesting a focus on deployment and management of AI models. Over the last 30 days, NVIDIA posted 214 new AI roles, a 27% decrease compared to the previous 30-day period.
NVIDIA currently has 487 active AI-related roles in our index. The most common open titles are: Deep Learning Performance Architect (4), Senior Deep Learning Performance Architect (4), AI Research Scientist (3), Developer Technology Engineer - AI (3), Manager, Deep Learning Algorithms (3). Most positions are in Engineering and Research.
NVIDIA's active AI hiring is concentrated in: serving infrastructure (54%), agents (21%), application (8%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
NVIDIA is hiring AI talent in: United States (286 roles), China (59 roles), Israel (50 roles), Germany (21 roles).
Job postings at NVIDIA most frequently reference: model serving, inference infra, agent orchestration, llm observability, multimodal.
In the past 30 days, NVIDIA has posted 110 new AI-related roles. That is a -50% change versus the prior 30 days (218 → 110).
| Title | Stage | AI score |
|---|---|---|
| SOC Methodology Engineer NVIDIA is seeking an SOC Methodology Engineer to focus on SOC design automation, RTL integration, and chip build and assembly. The role involves defining and developing system-level methodologies and tools, with an emphasis on using AI to solve SOC design challenges. Requires 3+ years of experience in chip design, specialization in SOC integration and methodology, and strong scripting skills (Perl, Python). | — | 0 |
| MCU Firmware Engineer NVIDIA is seeking an MCU Firmware Engineer to develop and deploy MCU firmware/software for next-generation GPU modules on DGX servers and Tesla boards. The role involves defining, designing, and developing security firmware, performing threat modeling, and recommending MCU solutions. Requires a Bachelor's degree in EE/CS/CE or equivalent, 3+ years of experience in firmware design and development, and strong programming skills in C/C++ within a Linux environment. Experience with specific MCU standards and embedded OS like FreeRTOS/Zephyr is a plus. | — | 0 |
| Physical Design Engineer Physical Design Engineer role for NVIDIA GPU and Mobile chips, involving full chip floorplanning, power/clock distribution, timing optimization, place & route, timing closure, power/signal integrity analysis, and physical verification. Requires experience with advanced EDA tools and design implementation. | — | 0 |
| Staff Systems Software Engineer- Server NVIDIA is seeking a Staff Systems Software Engineer to design, implement, and integrate GPU diagnostics for their next-generation GPU products. The role involves developing tests, integrating them into manufacturing and datacenter workflows, debugging issues across HW/FW/SW boundaries, and analyzing data to improve diagnostics. Requires strong C/C++, Python, and Linux system software experience, with a focus on server platforms and debugging skills. | — | 0 |
| Senior Mixed Signal Design Verification Engineer NVIDIA is seeking a Senior Mixed Signal Design Verification Engineer to verify the design and implementation of GPUs and SoCs. The role involves working with advanced verification methodologies for mixed-signal CMOS circuits, defining verification scope, developing infrastructure, and collaborating with multi-functional teams. Requires a Bachelor's degree in EE, CS, or CE, 5+ years of experience in deep sub-micron process design, and expertise in System Verilog. Experience with analog/mixed-signal circuit design, simulation tools, and Perl/C/C++ is desirable. | — | 0 |
| Digital Circuit Design Engineer Digital Circuit Design Engineer role at NVIDIA, focusing on mixed-signal high-speed I/O SerDes for cutting-edge technologies like AI, deep learning, and autonomous driving. Responsibilities include RTL design in SystemVerilog, verification, synthesis, timing closure, and collaboration with analog designers and system architects. | — | 0 |
| Senior System BIOS Firmware Developer, Client Product Senior System BIOS Firmware Developer role at NVIDIA, focusing on designing, implementing, and delivering innovations for client products with a focus on firmware development, client architecture, and building systems for laptop or small form factor products. Requires expertise in System BIOS (UEFI) Firmware development on X86 or ARM Platforms, experience with AMI/Insyde or EDK2 Firmware architecture, and strong C/C++ development skills. | — | 0 |
| IC Test Engineer NVIDIA is seeking a Test & Product Engineer to manage IC production test programs, optimize factory test plans, and drive yield improvements for networking silicon products. This role involves hands-on execution, debug, root-cause analysis, and collaboration with global design, validation, and manufacturing teams. | — | 0 |
| Senior Manager, Hardware Engineering Senior Manager, Hardware Engineering at NVIDIA leading teams in Taipei responsible for memory validation, IO characterization, reliability, and system-level manufacturing tests for NVIDIA's datacenter, consumer, professional, and automotive markets. Focus on first silicon power-on and silicon validation, NPI ramp-to-mass production, and lab operations. | — | 0 |
| Senior Design Verification Engineer - PCIE Senior Design Verification Engineer for PCI Express controllers for GPUs, SOCs, and DPUs. Requires expertise in verification methodologies like UVM and Specman/e, and knowledge of industry standard IP or interconnect protocols. | — | 0 |
| Senior Factory Support Firmware Engineer NVIDIA is seeking a Senior Factory Support Firmware Engineer to work with a global team on server designs, focusing on BIOS and BMC firmware development. The role involves writing and automating unit tests, collaborating with hardware teams on design and issue triage, and developing test tools for system software and firmware qualification. Requires domain expertise in BIOS/BMC firmware, experience with server architectures (AMI/Insyde/OpenBMC/UEFI), and strong C/C++ development skills in an embedded Linux environment. | — | 0 |
| Senior Mask Layout Design Engineer Senior Mask Layout Design Engineer to perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, general I/O's, ESD structures designs in state-of-the-art sub-micron CMOS technologies using Cadence tools. Work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products. Job duties will include floor planning, custom layout and verifying against design rules and schematics. | — | 0 |
| Senior Mixed Signal Circuit Design Engineer Senior engineer for mixed-signal circuit design of next-generation NVLINK, focusing on high-speed interfaces (TX/RX/Clocking/PLL) from concept to silicon characterization. Responsibilities include schematic design, architecture, transistor design, verification, and post-silicon support. | — | 0 |
| Senior Hardware Engineer – Ethernet Switch NVIDIA is seeking a Senior Hardware Engineer to support the development, bring up, and testing of Ethernet switch hardware. The role involves collaborating with partners, customers, and internal R&D teams to address technical issues and provide solutions, as well as contributing feedback on product requirements and improvements. The ideal candidate will have a BSc/MSc in Electrical or Computer Engineering, 5+ years of HW development experience including high-speed PCBs, and experience in electro-optics and photonics. | — | 0 |
| Senior HSIO Validation Engineer NVIDIA is seeking a Senior HSIO Validation Engineer to architect and build system and platform level features for silicon validation. This role involves collaborating with various teams, defining roadmaps, supporting silicon bring-up, and coordinating the implementation of interfaces for GPUs, SOCs, and CPUs. The ideal candidate will have a strong understanding of PCIe protocols, signal integrity, and hands-on experience with lab equipment and scripting for validation. | — | 0 |
| Senior System Software Engineer, SOC Senior System Software Engineer role at NVIDIA focusing on GPU System Software, SOC platforms, and kernel drivers. The role involves defining, designing, developing, and verifying features for new SOC platforms, collaborating with hardware and software engineers, and following products through the development process. Requires strong C/C++ programming, low-level driver, and SOC system platform experience, with kernel experience in Linux, Android, Chrome, or Windows. Experience with complex SOC system debugging is invaluable. Background in AI & GPU computing system architecture design is a plus. | — | 0 |
| Senior ASIC Verification Engineer, Coherent High Speed Interconnect NVIDIA is seeking a Senior ASIC Verification Engineer to verify the design and implementation of high-speed coherent interconnects for their mobile SoCs and GPUs. The role involves architecting test bench environments, developing verification infrastructure, and collaborating with cross-functional teams. Experience with industry-standard protocols like PCIE, CXL, and CHI is useful, as is expertise in System Verilog and UVM methodology. | — | 0 |
| Senior Mixed Signal Circuit Design Engineer NVIDIA is seeking a Senior Mixed Signal Design Engineer to join their Mixed Signal design team building next generation NVLINK. This role involves the design, simulation, verification, and characterization of high-speed interface circuits and analog circuits, with a focus on transceivers and PLLs for data rates of 100Gbps and higher. The engineer will lead mask designers, mentor junior engineers, and take designs from concept through silicon characterization and productization. Experience with deep submicron CMOS processes, Cadence tools, and silicon bring-up is required. | — | 0 |
| Senior Packaging Technical Engineer - Hardware NVIDIA is seeking a Senior Packaging Technical Engineer to define chip pad ring, substrate interconnect scheme, and lead the package layout design process. This role involves collaboration with various engineering teams and requires a minimum of 5 years in board/system design, with package design experience being preferred. Strong programming and scripting skills in Perl, Python, Tcl are desired. | — | 0 |
| Senior Package Layout Engineer NVIDIA is seeking a Senior Package Layout Engineer to design state-of-the-art high-speed interconnect systems for Supercomputers and Datacenters. The role involves collaborating on high-speed and PDN design for ASIC packages, developing symbols, pad stacks, and performing substrate package routing, placement, and power distribution using APD or SiP tools. Responsibilities include optimizing package pin-out, developing methodologies to improve layout productivity and reliability, and leading projects from start to finish. Requires a B.Sc. in Electrical Engineering or equivalent, 5+ years of experience in Package or PCB Layout with high-speed design, signal integrity, and PDN planning, and experience with substrate layout for wire bond and flip chip packages. | — | 0 |
| Senior Design Verification Engineer - PCIE Senior Design Verification Engineer for PCI Express controllers used in GPUs, SOCs, and DPUs. Requires expertise in verification methodologies like UVM and Specman/e, and knowledge of industry standard protocols. | — | 0 |
| Senior Manufacturing Test Engineer | — | — |
| ATE Test Engineer | — | — |
| Manufacturing Test Engineer | — | — |
| Manufacturing Test Engineer, ICT | — | — |
| Manufacturing Test Engineer - Board | — | — |
| Memory Solution Engineer | — | — |
| ICT Test Engineer | — | — |