C++ Machine Learning Engineer focused on extending and optimizing the ML training framework for custom silicon, debugging model performance, and supporting production integration.

The role involves architecting, integrating, and deploying AI/ML-driven solutions into production physical design flows for advanced semiconductor nodes. This includes creating custom CAD tools and optimizing EDA tools using data-driven and ML-based techniques to improve PPA and runtime. The engineer will also develop and enhance RTL-to-GDS methodologies.

Software Engineer on the Metal Runtime team working on low-level software for AI accelerators, focusing on scheduling, memory movement, and efficient execution across parallel processors. The role involves building and optimizing high-performance runtime systems close to the hardware.

The role focuses on optimizing the energy efficiency of RISC-V based CPUs and AI Data Centers for Tenstorrent, a company at the forefront of AI technology. The Power Architect will be responsible for power management, SoC power architecture, power delivery networks, thermal analysis, and performance trade-offs, with a specific emphasis on analyzing AI and ML workloads for performance and efficiency. This is a hybrid role based in Santa Clara, CA, with opportunities for growth and impact in the AI hardware design space.

Software Engineer role focused on developing and scaling an MLIR-based AI compiler (TT-Forge) for Tenstorrent, involving graph transformations, lowering passes, and kernel optimizations to support both training and inference on custom chip architectures.

Software Engineer role focused on developing and optimizing distributed software systems for AI and HPC clusters, specifically for distributed inference and training infrastructure. Requires strong C/C++ systems programming, distributed computing principles, and experience with MPI-based technologies.

Software Engineer role focused on building and optimizing TT-Fabric, a low-level networking library for Tenstorrent's AI compute clusters. The role involves architecting, implementing, and maintaining the networking layer that connects thousands of AI processors for distributed training and inference, optimizing protocols and data movement for maximum hardware performance.

Lead a team of Verification Engineers to validate the functionality and performance of next-generation AI hardware, focusing on AI-specific data types, compute patterns, and on-chip network validation.

Tenstorrent is seeking a Physical Design Engineer to implement high-performance partitions for an AI SOC. The role involves owning the complete implementation flow from synthesis to tapeout, working with architects, RTL designers, and DFT engineers to resolve issues and ensure signoff.

Physical Design Engineer to implement high-performance blocks for CPU and AI/ML architectures, owning the complete implementation flow from synthesis to tapeout. Requires expertise in SOC/ASIC physical design, synthesis, PnR, timing closure, and industry-standard tools.

Develop and optimize the software stack for AI and RISC-V hardware IP customers, including firmware, drivers, system tools, and APIs, ensuring seamless integration and customer experience. Partner with hardware, IP delivery, customer support, and product teams.

Field Application Engineer role focused on customer success and driving adoption of Tenstorrent's AI products and solutions. Requires strong technical knowledge in AI/ML, customer-facing skills, and experience with AI technologies and frameworks, embedded systems, and AI accelerators. The role involves collaborating with sales and product teams, understanding customer challenges, and providing solutions. Experience with hardware/software co-optimization for edge inference is important.

This role focuses on designing and operating Kubernetes-based platforms on on-prem data centers, enabling engineers and customers to run workloads efficiently on Tenstorrent hardware. The team builds platforms that power internal development, workload orchestration, and hardware allocation across large-scale AI systems.

Software Engineer on the Metal Runtime team at Tenstorrent, working on low-level software for AI accelerators. Designs runtime systems close to hardware and defines host/device APIs. Focuses on API design, abstraction, performance, and developer experience.

This role supports hardware emulation infrastructure and internal chip design teams by integrating transactors, developing Python test frameworks, and providing technical support. It requires proficiency in Python, C++, and SystemVerilog, with experience in chip design, verification, or emulation. The role also involves using AI tools for code generation and debugging.

This role focuses on Static Timing Analysis (STA) methodology for advanced-node, high-performance, low-power semiconductor designs. The engineer will lead the development and optimization of STA methodologies and flows, drive data- and ML-assisted timing automation, and collaborate with various teams and EDA vendors to solve complex timing challenges. The role involves improving PPA (Power, Performance, Area) and runtime efficiency through automation and data-driven techniques.

Seeking a Senior High Speed Interconnect / Signal Integrity Engineer to design and validate high-bandwidth links for large-scale AI systems, focusing on interconnect solutions across copper and optical technologies for next-generation AI inference and training clusters.

This role focuses on designing and building next-generation CPU networking architecture for AI/ML workloads, targeting both datacenter and robotics/automotive applications. The primary focus is on the interconnect and compute aspects that enable AI systems, rather than directly building AI models.

Staff Software Engineer focused on cloud infrastructure, SRE, and DevOps to support AI technology development. Responsibilities include infrastructure automation, integration, operations, backend development, and IaC, leveraging tools like Python, Ansible, Prometheus, and Kubernetes. The role will utilize AI tools and collaborate with AI/ML experts.

Field Applications Engineer for Tenstorrent's RISC-V CPU and AI accelerator IP products. Responsible for end-to-end technical engagements with customers, translating architectural advantages into wins, and shaping product roadmap with market feedback. Requires deep technical expertise in semiconductors and customer engagement skills.

This role focuses on porting and enabling AI workloads on RISC-V architectures, requiring expertise in DevOps, workload migration, and systems software to optimize hardware performance for AI applications. It involves bridging the gap between IT, DevOps, and AI teams.

This role focuses on performance architecture for AI/HPC platforms, bridging software execution and silicon design. The architect will work on ML software stacks, compilers, CPU design, cache coherency, and interconnect fabrics to optimize SoC performance. Familiarity with ML/AI traffic patterns is a plus.

This role focuses on validating and qualifying die-to-die (D2D) subsystems, AI, and Processor IP testchips for the chiplet ecosystem. Responsibilities include developing hardware infrastructure for validation platforms, performing electrical characterization, and supporting customer silicon bring-up. The role requires expertise in silicon test and characterization, lab environments, and high-speed measurements.

Tenstorrent is seeking a Risc-V Architect to analyze AI workloads and architect custom RISC-V CPU cores optimized for performance, power, and area. The role involves designing custom instructions and collaborating across teams to co-design the company's next-gen compute architecture, focusing on improving programmability and developer experience for AI compute.

Tenstorrent is seeking a Developer Relations Engineer, Tools to build and contextualize tools, demos, and interfaces for developers to utilize Tenstorrent hardware and software. This role focuses on improving the developer experience by reducing friction and improving education around AI platform capabilities.

Developer Relations Engineer focused on advocating for Tenstorrent's AI hardware and software platform, engaging with developers online and at events, and fostering community relationships. The role involves understanding developer needs and promoting an open AI future.

Tenstorrent is seeking a RISC-V CPU Microarchitecture/RTL owner to develop next-generation CPU designs. This role involves defining microarchitecture specifications, designing RTL, and performing unit verification for CPU components like branch predictors and vector execution units. The candidate will also use AI tools to accelerate the design process and potentially mentor junior engineers. Experience with high-performance CPU RTL design for architectures like x86, Arm, or RISC-V is required.

Tenstorrent is seeking a SoC Chiplet Design Lead to drive the design and development of advanced System-on-Chip (SoC) architectures targeting AI, HPC, and automotive markets. This role involves leading cross-functional teams through the entire SoC lifecycle, from concept to tape-out, focusing on performance, scalability, and efficiency. The ideal candidate will have deep expertise in SoC and chiplet design, RTL design, and digital architecture, with proven experience in leading end-to-end SoC development and verification.

Tenstorrent is seeking a GCC Compiler Engineer to design, develop, and optimize compilers for next-generation RISC-V and AI compute architectures. The role involves working across hardware and software teams to improve performance and integration of custom toolchains for both traditional compute and machine learning workloads.

Senior Design Verification Engineer for AI hardware, focusing on custom AI compute cores, RISC-V CPUs, and chiplet-based architectures. The role involves validating compute IP and subsystems, building scalable DV infrastructure, and contributing to verification environments, agents, and scoreboards using SystemVerilog and Python. The position requires experience in modern verification methodologies, scripting, and coverage-driven verification, with a focus on AI-native compute architectures.

This role focuses on formal verification of CPUs and chiplets, applying advanced methods to ensure rigorous quality standards. While the company works on AI technology and the role involves applying AI techniques to improve verification processes, the core craft of the engineer is formal verification of hardware, not direct AI/ML model development.

Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes. This role involves leading physical verification closure, debugging issues, and collaborating with various teams to achieve successful tapeouts.

Tenstorrent is seeking an experienced EDA/PDK CAD Engineer to build and maintain design infrastructure for AI silicon innovation. The role involves installing and optimizing PDKs, managing EDA tool flows, and collaborating with various engineering teams to improve design efficiency. Responsibilities include troubleshooting CAD issues and supporting physical verification and simulation flows.

This role is for a Mixed-Signal IC Layout Design Engineer at Tenstorrent, an AI technology company. The engineer will be responsible for full-custom physical layout of analog and mixed-signal integrated circuits, ensuring they meet performance, power, area, and reliability targets in advanced FinFET processes. The role involves developing floorplans, placement, and routing, applying best-known layout practices, and supporting post-layout extraction and simulation. Experience with Synopsys Custom Compiler/Cadence Virtuoso and Synopsys ICV/Siemens Calibre is required. The company emphasizes collaboration, curiosity, and solving hard problems.

Staff Engineer focused on CPU core-level verification for out-of-order RISC-V CPUs, involving RTL, UVM, C/C++ stimulus development, debug, and collaboration across design and validation teams.

This role focuses on the physical design of AI and CPU System-on-Chip (SOC) designs, including floorplanning, power grids, and clock networks, to ensure chip-level closure. It involves collaboration with cross-disciplinary teams and optimization for power, performance, and area.

Tenstorrent is seeking a Staff Engineer, Emulation Technical Lead to lead technical efforts and strategy around their emulation infrastructure for high-performance CPUs that power AI products. This role involves leading technical strategy, enabling emulation infrastructure, driving debug efforts, and optimizing performance with design verification teams and tool vendors. The role is hybrid and based in Austin, TX.

The role focuses on CPU design infrastructure for performance analysis, correlation, and verification, working with RISC-V ISA and collaborating with core architects and RTL teams to deliver efficient and performant designs. It involves enhancing the design environment, tools, and methodologies, and optimizing power, performance, and area.

Tenstorrent is seeking a Lead Engineer to own post-silicon power characterization and correlation for AI semiconductor products. Responsibilities include developing and executing power measurement strategies, correlating silicon data with pre-silicon models, and driving improvements in power architecture and methodologies. The role requires deep understanding of silicon power domains and lab measurement techniques, with a focus on cross-functional collaboration.

Tenstorrent is seeking a Layout Engineer with expertise in board layout for high-performance computing and AI hardware. This role requires direct experience with multi-layer boards, HDI vias, blind vias, back drilling, DFM, DFA and routing / layout of interfaces like GDDR, LPDDR, DDR, PCIe Gen 5 & 6, Ethernet IEEE 802.3bj, cd, cf, USB, etc. The ideal candidate will work closely with cross-functional teams consisting of engineers from systems, power, signal integrity and mechanical to ensure that our products meet the layout margins and cutting-edge specifications for mass production boards for data centers, workstations, and consumer computing applications.

Tenstorrent is seeking a Staff Engineer for Software Release and Packaging, focusing on RISC-V and system IP products. The role involves building, packaging, and releasing software that combines Linux and open-source packages with proprietary software to enable customer success. This is a remote or hybrid position in North America or Australia, with compensation ranging from $100k to $500k. A key requirement is eligibility to access U.S. export-controlled technology.

Tenstorrent is seeking a Sr Staff Engineer, CPU System Microarchitect to define and implement CPU system RTL, combining cores, clusters, fabrics, and subsystem components. The role involves collaboration with DV, PD, architecture, and performance teams to deliver a functional, timing, and power-converged design. Experience with microarchitecture definition, RTL coding, and debugging is required.

Tenstorrent is seeking a Physical Design Engineer to drive the Die-to-Die (D2D) Physical Implementation from RTL to GDSII for multi-die/chiplet architectures. The role involves full physical design flow, including synthesis, floorplanning, place-and-route, CTS, and sign-off, with a focus on high-speed interfaces.

Develops production test programs for high-performance AI/ML silicon on ATE test platforms, translating DFT/ATPG content into optimized ATE solutions and implementing Streaming Scan Network architectures. Focuses on reducing test cost, optimizing test time for chiplet/multi-die architectures, and enabling yield learning.

Tenstorrent is seeking a Senior Chiplet Physical Design Engineer to design and integrate chiplets into a System-in-Package (SiP) for AI silicon. The role involves synthesis, place-and-route, and timing closure for high-speed CPU cores on advanced process nodes, collaborating with global teams and external partners.

Staff Design for Test STA Engineer at Tenstorrent, a company focused on AI technology. The role involves ensuring testability, quality, and performance of AI processors through DFT and STA expertise. Responsibilities include defining and implementing DFT methodology, owning timing constraints and sign-off for DFT modes, and collaborating with RTL, Physical Design, and Product Engineering teams.

This role focuses on advancing ASIC design infrastructure and flows for RTL development, verification, and physical implementation, aiming to improve design quality, enable scalability, and automate methodologies. It involves developing and maintaining ASIC design methodologies, owning static code analysis, developing synthesis timing constraints, and supporting the RTL-to-GDS flow.

Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes. Responsibilities include leading physical verification closure, debugging issues, and collaborating with cross-functional teams to achieve successful tapeouts.