AMD currently has 35 active AI-related job listings. The majority of these roles, 66%, are focused on serving infrastructure. Engineering is the dominant function, with 32 positions. Frequent technical tags include model_serving, inference_infra, and evals, suggesting a focus on the deployment and evaluation of AI models. In the last 30 days, AMD posted 37 new AI roles.
AMD currently has 62 active AI-related roles in our index. The most common open titles are: DC-GPU Performance Modeling Engineer (3), Data Center Engineer (2), Lead Packaging Automation Engineer (2), 3D IC and ADVANCED PACKAGING CAD ENGINEER , AI Framework Engineer. Most positions are in Engineering and Research.
AMD's active AI hiring is concentrated in: serving infrastructure (73%), agents (13%), application (6%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
AMD is hiring AI talent in: United States (27 roles), India (13 roles), China (7 roles), Canada (6 roles).
Job postings at AMD most frequently mention: GPU Computing, Computer Architecture, Compiler Design, Python, Performance Profiling.
In the past 30 days, AMD has posted 55 new AI-related roles.
| Title | Stage | AI score |
|---|---|---|
| Senior Program Manager This role is for a Senior Program Manager at AMD, focusing on leading end-to-end execution of complex System-on-Chip (SoC/ASIC) development programs. The role involves planning, tracking, reporting, and risk management across all phases from architecture through tapeout and post-silicon. While the role mentions leveraging AI for execution efficiency and using AI tools, the core function is program management for SoC development, not direct AI/ML model development or research. The primary deliverable is the successful execution of the SoC program, which can be considered a shipped product (L6). | — | 0 |
| Senior Program Manager This role is for a Senior Program Manager at AMD, focusing on leading end-to-end execution of complex System-on-Chip (SoC/ASIC) development programs. The role involves planning, tracking, reporting, and risk management across all phases from architecture through tapeout and post-silicon. While the role mentions leveraging AI for execution efficiency and using AI tools, the core function is program management for SoC development, not direct AI/ML model development or research. The primary deliverable is the successful execution of the SoC program, which can be considered a shipped product (L6). |
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| Senior/Lead Linux Kernel Development Engineer This role focuses on performance and benchmarking of CPU, GPU, and NPU on Linux-based systems, involving kernel programming, system-level debugging, and automation of performance analysis. The engineer will analyze kernel logs, profiling data, and optimize OS and kernel behavior for repeatable performance insights. | — | 0 |
| Validation Lead This role is for a Lead / Principal Systems Design Engineer at AMD, focusing on driving and improving the quality and delivery of AMD's technologies. The engineer will be responsible for technical innovation in validation, tool and script development, methodology enhancement, debugging issues, tracking test execution, and collaborating with various teams. Experience in programming, debugging, lab equipment, and system architecture is preferred. | — | 0 |
| Lead IP Block level Verification Engineer This role is for a Lead IP Block level Verification Engineer at AMD, focusing on Network on Chip (NOC) IPs and Subsystems. The engineer will architect, develop, and use verification environments (simulation and formal) to ensure the functional correctness of NOC IPs, subsystems, and SOC designs. Responsibilities include planning verification, designing testbenches in System Verilog and UVM, debugging, and coverage analysis. Experience with verification techniques, ASIC development phases, and specific protocols like AXI/DDR/PCIe is preferred. | — | 0 |
| ASIC Sub system / Block Level Verification Engineer This role is for an ASIC Subsystem/Block Level Verification Engineer at AMD, focusing on Network on Chip (NOC) IPs and Subsystems. The engineer will architect, develop, and use simulation and formal verification environments to ensure the functional correctness of NOC IPs, subsystems, and SOC designs. Responsibilities include planning verification, designing testbenches in System Verilog and UVM, debugging, and coverage analysis. While the company mentions AI and data centers, this specific role is in hardware verification, not AI model development. | — | 0 |
| IP/Subsystem Verification Lead The role is for an IP/Subsystem Verification Lead responsible for verifying cutting-edge FPGA and ASICs for various customers. This involves collaborating with architects and engineers, developing test plans, coding UVM-based testbenches, running regressions, and debugging failures to ensure high design quality. | — | 0 |
| Director Front-end SoC Design Lead the Front-end SoC Design team in India for AMD's flagship Instinct GPU SoC, overseeing the entire front-end process from micro-architecture to netlist. This role requires extensive leadership experience in complex SoC design, including IP integration, verification, power management, and post-silicon support. | — | 0 |
| DFT Lead - ATPG This role is for a Silicon Design Engineer focused on Design for Test (DFT) for AMD's Radeon Technologies Group. The engineer will be responsible for implementing and verifying DFT architecture, scan insertion, ATPG pattern generation, and post-silicon support to ensure successful bring-up and yield learning. The role requires a strong understanding of DFT methodologies and experience with relevant tools and scripting languages. | — | 0 |
| Emulation Engineer AMD is seeking an Emulation Engineer for their CPU Silicon Emulation team in Bangalore, India. This role involves deep understanding of AMD X86 CPU architecture and microarchitecture, debugging emulation issues of RTL, and providing feedback to the design team in a pre-silicon and emulation environment. The position requires experience in emulation environments, debugging low-level software and hardware issues, CPU and SoC architectures, Verilog/SystemVerilog, and scripting languages like Python and TCL. Experience with FPGA expertise and processor/ASIC design verification is also important. | — | 0 |
| STA Engineer This role is for an MTS Silicon Design Engineer at AMD, focusing on the development and signoff of complex multi-mode/multi-corner timing constraints for RTL and signoff. The engineer will ensure constraint quality, drive pre-route timing checks, and perform timing closure for chip subsystems or full chips. The role requires strong knowledge of SDC, EDA timing tools, and Tcl scripting. | — | 0 |
| Senior Field Applications Engineer This role serves as a technical interface for AMD's commercial products, providing pre-sales and development support to end customers in India. The Field Applications Engineer will build technical relationships, demonstrate AMD technology's value, and offer post-sales support, troubleshooting, and technical escalations. The position requires a strong understanding of client CPUs/GPUs, platform architecture, and common applications on AMD hardware, with a focus on winning commercial client and workstation opportunities. | — | 0 |
| Lead Analog Mixed-Signal Design Engineer Lead Analog Mixed-Signal Design Engineer at AMD in Bangalore, India, with 8+ years of experience in semiconductor IP design and development. Responsibilities include leading a design team, schedule planning, cross-functional collaboration, and contributing to analog circuit architecture. Requires hands-on experience in high-speed PHY/IO designs, FinFET nodes, and AMS EDA tools. Master's degree in electrical engineering required, PhD preferred. | — | 0 |
| DFT Verification Engineer This role is for a DFT Verification Engineer focused on SoC design verification for server programs. The responsibilities include developing testbenches, debugging complex issues, and ensuring the quality of silicon designs. While the company mentions AI and uses AI in its hiring process, the core craft of this role is not AI/ML model development or deployment. | — | 0 |
| Principal Physical Design Lead - CPU This role is for a Principal Physical Design Lead focused on CPU design at AMD. The responsibilities include driving the physical design of critical CPU units from RTL to GDSII, including synthesis, floor-planning, place and route, timing closure, and signoff. The role requires deep expertise in physical design methodologies, PPA tradeoffs, and various PNR tools, with a focus on high-performance designs and advanced sub-7nm nodes. While the company mentions AI and next-generation computing, the core function of this role is traditional CPU physical design engineering, not AI/ML model development or deployment. | — | 0 |
| Design Verification Engineers This role is for a Design Verification Engineer at AMD, focusing on high-performance x86 microprocessor cores. The responsibilities include architecting and developing testbenches, test plans, and ensuring functional coverage for complex designs. The role requires experience in ASIC design verification, SystemVerilog, and microprocessor ISAs. | — | 0 |
| Post Silicon Validation Application Engineer This role is for a Post Silicon Validation Application Engineer at AMD, focusing on technical customer interface, SoC/IP bring-up, validation, debug, and issue resolution. It requires significant experience in post-silicon validation, lab equipment, scripting, and system architecture. The role involves collaborating with internal teams and supporting customer environments, with preferred skills in customer-facing roles and high-speed interfaces. | — | 0 |
| Field Application Lead Engineer Field Application Lead Engineer responsible for technical support of AMD's embedded products (FPGA, embedded x86) to customers in India. Focus on pre-sales and development support, building technical relationships, and resolving technical escalations. Requires strong technical knowledge in embedded systems, microprocessors, and FPGAs, with excellent communication and problem-solving skills. | — | 0 |
| Electrical Characterization Engineer This role is for a Senior Systems Design Engineer at AMD, focusing on improving AMD's capabilities in product development, validation, and root cause resolution. The engineer will drive technical innovation, develop tools and scripts, enhance methodologies, and work with multiple teams to ensure features are validated and optimized. The role involves debugging issues across different phases of SOC programs and engaging with software/hardware modeling frameworks. Programming/scripting skills and experience with lab equipment and board-level debug are preferred. | — | 0 |
| Senior Lead Verification Engineer This role is for a Senior Lead Verification Engineer at AMD, focusing on verifying complex design blocks at the IP, Sub-system, or SoC level using System Verilog/UVM. The engineer will develop and enhance testbenches, interact with various design teams, and mentor junior engineers. Experience in ASIC verification, developing verification environments, and scripting is preferred. | — | 0 |
| Senior Lead Verification Engineer Senior Lead Verification Engineer at AMD, focusing on verifying complex designs for client, server, graphics, and semi-custom interconnects using System Verilog/UVM. The role involves developing and enhancing testbenches, collaborating with design and validation teams, and mentoring junior engineers. Requires strong ASIC verification experience and architectural understanding of verification environments. | — | 0 |
| Senior Lead Verification Engineer Senior Lead Verification Engineer at AMD, focusing on front-end design/integration for cutting-edge hardware, including AI and data centers. Responsibilities include developing and enhancing System Verilog/UVM testbenches, collaborating with various engineering teams, and mentoring junior engineers. Requires extensive experience in ASIC verification and testbench development. | — | 0 |
| SENIOR ARCHITECT SOFTWARE DEVELOPMENT ENGINEER This role is for a Senior Architect Software Development Engineer at AMD, focusing on improving the performance of key applications and benchmarks. The responsibilities include leading the development of automation frameworks, designing APIs, deploying applications in containerized environments, managing cloud solutions, and supporting post-silicon validation efforts. The role requires strong programming skills in Java or Python, experience with web services, CI/CD, and cloud platforms like Azure. While the company mentions AI and data centers, the core responsibilities of this specific role are in general software development and engineering, not directly building or researching AI models. | — | 0 |
| STA Lead This role is for a Full Chip SoC Timing Lead responsible for ASIC/SoC design implementation and timing closure. The candidate will lead timing activities from synthesis through place-and-route, signoff, and tapeout for complex SoCs in advanced technology nodes. This requires deep expertise in STA, timing constraints, MMMC flows, SI/crosstalk analysis, and ECO closure. | — | 0 |
| Senior Lead Verification Engineer (Leadership role) Senior Lead Verification Engineer at AMD in Bangalore, India, focusing on pre-silicon verification of Infinity Fabric transport layer, configurable switches, and die-to-die interconnects for client, server, graphics, and semi-custom markets. Responsibilities include developing and enhancing System Verilog/UVM testbenches, mentoring junior engineers, and collaborating with design and validation teams. | — | 0 |
| SOC Debug tools validation Engineer This role is for a SOC Debug tools validation Engineer at AMD, focusing on the validation and debugging of Silicon Debug Tools products. The engineer will be responsible for creating test strategies, executing test plans, coordinating debug efforts, and ensuring product quality across various engineering teams. While AI is mentioned in the company's mission and a general statement about AI use in screening, the core responsibilities of this specific role are not AI/ML-centric. | — | 0 |
| IP Verification Lead This role focuses on planning, building, and executing the verification of new and existing features for AMD's graphics processor IP, ensuring no bugs in the final design. It involves collaborating with architects, hardware, and firmware engineers, building test plans, writing directed and random verification tests, debugging failures, and reviewing coverage metrics. | — | 0 |
| SOC verification Manager/Lead Seeking an experienced SOC Verification Manager/Lead with deep expertise in SoC-level verification, power management verification, low-power verification methodologies, and SoC verification architecture development. The role involves defining verification strategies, architecting verification environments, driving functional and power-aware verification closure, and mentoring teams. Responsibilities include leading end-to-end verification planning, execution, coverage closure, and sign-off activities, collaborating with cross-functional teams, and supporting various verification environments (simulation, emulation, FPGA, post-silicon). | — | 0 |
| Senior Design Verification Engineer – Security IP This role is for a Senior Design Verification Engineer focused on Security IP (SECIP) development at AMD. The engineer will be responsible for block-level functional verification and subsystem-level integration and verification of embedded micro-processor subsystems and hardware accelerators. The role involves developing verification architectures, testbenches, and test plans using SystemVerilog/UVM, C-DPI, and formal verification methodologies. Key responsibilities include debugging simulations, analyzing coverage, collaborating with design teams, and providing technical leadership in verification methodology and problem resolution. While the company mentions AI and its role in computing experiences, this specific position is centered on hardware verification, not AI model development or deployment. | — | 0 |
| Product Engineer - FPGA/Emulation & ACAP Compilation Tools Product Engineer at AMD focusing on FPGA/Emulation & ACAP Compilation Tools. This role involves owning emulation and prototyping product areas, driving customer escalations, triaging issues, exploring innovative methodologies, and developing training materials. Requires MS or equivalent experience with 8+ years in Electrical Engineering or similar, with strong knowledge of RTL design flows, pre-silicon validation, emulation/prototyping, and scripting. | — | 0 |
| Lab Engineer (Post Silicon Validation) The Lab Engineer (Post Silicon Validation) role at AMD is responsible for managing, maintaining, assembling, and supporting a large volume of compute systems used for platform bring-up, validation, and firmware development. This includes system assembly, firmware flashing, remote access enablement, boot failure triage, and thermal setup management, ensuring the reliable operation of lab systems. The role also involves meticulous record-keeping of hardware assets and coordinating with various teams for lab readiness and safety. | — | 0 |
| Lead IP Verification Engineer Lead IP Verification Engineer at AMD, responsible for planning, building, and executing verification of graphics processor IP features to ensure no bugs in the final design. This role involves collaboration with architects and engineers, test plan development, test building, debugging, and coverage analysis. | — | 0 |
| Lead DPDK Optimization Engineer Lead DPDK Optimization Engineer at AMD in Bangalore, India. Focuses on performance optimization and benchmarking of DPDK-based data plane applications across CPU/GPU/NPU platforms. Requires mandatory DPDK development experience and strong Linux systems knowledge. | — | 0 |
| Sr. Lead IP/RTL Design Engineer This role is for a Sr. Lead IP/RTL Design Engineer focused on Data Fabric and NoC architecture within AMD. The engineer will micro-architect, design, and deliver RTL components, manage power, performance, and area targets, and collaborate with architecture, verification, and physical design teams. The role involves defining features, driving technical specifications, leading discussions on core interfacing, and supporting various design and verification stages, including post-silicon debug. While the company mentions AI and data centers, the core responsibilities are in hardware design (RTL, NoC, IP) rather than AI model development or deployment. | — | 0 |
| Senior UEFI/BIOS Firmware Engineer This role is for a Senior UEFI/BIOS Firmware Engineer at AMD, focusing on designing, developing, and debugging firmware for internal and external systems using AMD APUs/CPUs. The position involves C language programming, power management, security features, and collaboration with various internal and external teams. While AMD's broader mission includes AI, this specific role is centered on traditional firmware engineering. | — | 0 |
| C++ Lead Software System Design Eng Lead Software System Design Engineer with C++ expertise to develop validation SW tools for next-generation AMD microprocessors, focusing on platform validation and cross-functional collaboration. | — | 0 |
| HSIO Enablement Lead This role is for a HSIO Enablement Lead at AMD, focusing on the post-silicon enablement of High Speed interfaces (Ethernet, PCIe, Display, USB). The responsibilities include end-to-end enablement, feature coverage, debug, and developing validation plans. While the company mentions AI and its use in screening, this specific role is not directly involved in AI/ML development. | — | 0 |
| Senior Emulation Engineer AMD is seeking a Senior Emulation Engineer to join their growing team. This role involves building and bringing up emulation models, developing transactors/BFMs, bringing up PCIe and Ethernet interfaces, and debugging emulation failures. The ideal candidate will have hands-on experience with Mentor Veloce and familiarity with Synopsys ZeBu, strong C/C++ programming skills, and a good understanding of PCIe, Ethernet, or RISC-V processors, along with Verilog/SystemVerilog RTL and verification flows. A Bachelor's or Master's degree in Electrical/Electronics Engineering and 5+ years of relevant experience are required. | — | 0 |
| Senior BIOS & Firmware Applications Engineer Senior BIOS & Firmware Applications Engineer at AMD in Bangalore, India. This role focuses on UEFI BIOS, EDK2, Coreboot, and system-level understanding of embedded systems. Responsibilities include defining customer demos, supporting customers with BIOS issues, developing and running tests for system performance, and investigating hardware protocols. Requires strong programming skills in Python and C/C++ and experience with bootloaders and operating systems like Linux. | — | 0 |
| Pre-silicon Validation Engineer - Emulation This role focuses on pre-silicon validation engineering for complex System-on-Chip (SoC) programs, involving emulation platforms, debugging, and developing test content for hardware features. It is not directly involved in building or researching AI/ML models. | — | 0 |
| Lead Automative Use Cases Validation Engineer Lead Automative Use Cases Validation Engineer at AMD, focusing on validating Automotive Virtualization on AMD platforms. The role involves validating Xen-based virtualization, multi-OS domains, IVI features, graphics, and Ryzen AI workloads across hypervisor, OS domains, drivers, and system level performance. | — | 0 |
| Senior RTL Design Engineer This role is for a Senior RTL Design Engineer at AMD, focusing on the front-end design and integration of Server SoC chips. The engineer will work with architects and IP design teams to define micro-architecture, implement SoC features, and ensure RTL quality. Experience with Verilog, scripting, and SoC design aspects is preferred. | — | 0 |
| SoC Physical Design Lead Seeking a seasoned SoC Physical Design Lead with expertise in delivering high-quality physical design implementations for high-performance, low-power SoCs. Responsibilities include floorplanning, placement, clock tree synthesis, routing, timing closure, PnR strategy optimization for advanced nodes, and leading technical reviews. The role requires collaboration with RTL, architecture, CAD, and verification teams, and influencing design partitioning and hierarchical strategies. Experience with EDA tools and SoC architecture is preferred. | — | 0 |
| Physical Design Lead – Full Chip & Chiplet SoC This role is for a Physical Design Lead at AMD, focusing on the physical design of complex chiplets for advanced technology nodes. The responsibilities include full chip floorplan, PnR closure, timing targets, and signoff functions, while collaborating with various internal and external teams. The role emphasizes PPA (Power, Performance, Area) optimization and schedule adherence. Although the company mentions AI in its mission and for applicant screening, the core of this role is in hardware/silicon design, not AI/ML model development. | — | 0 |
| Senior Low Power Engineer – Physical Design & PnR Flows This role is for a Senior Low Power Engineer focused on Physical Design & Place and Route (PnR) flows at AMD. The engineer will be responsible for developing and automating low-power PnR flows for advanced technology nodes (3nm & 2nm), collaborating with design teams and EDA vendors, and supporting global design teams on P&R and ECO implementations. The role requires expertise in power grid construction, low-power implementation methodologies, and scripting for automation. | — | 0 |
| DFT Engineer Senior Manager Silicon Design Engineer (SOC Lead) at AMD, responsible for driving end-to-end SOC/ASIC execution from concept to tape-out and productization. This role involves leading cross-functional teams, managing project planning, schedule, and deliverables, and ensuring successful silicon checkout and debug. The position requires extensive experience in SOC development, integration, and implementation, with a strong emphasis on leadership, problem-solving, and stakeholder management. | — | 0 |
| QEMU Lead Software Development Eng. Software Development Engineer focused on QEMU based virtual platforms, debugging, optimization, and improving future products. Requires C/C++ and virtual platform experience. | — | 0 |
| EDA Software Development Eng. Software engineer to work on core logic synthesis and optimization technologies within the Vivado FPGA toolchain, improving performance, scalability, and quality of results for AMD's FPGA implementation software. | — | 0 |
| Power and Performance Engineer AMD is looking for a Power and Performance Engineer to drive next-generation power architecture, firmware, algorithms, and software interfaces across AMD client and handheld SoCs. This role involves defining power-management architecture, collaborating with various teams, and optimizing power efficiency, performance-per-watt, and battery life. The ideal candidate will have strong technical, problem-solving, and communication skills, with experience in profiling, tuning, and algorithm development for complex datasets, as well as system and SoC control firmware. | — | 0 |
| Power and Performance Engineer AMD is seeking a technical leader for their Computing and Graphics business unit to drive next-generation power architecture, firmware, algorithms, and software interfaces across AMD client and handheld SoCs. This role involves defining power-management architecture, collaborating with various engineering teams, and driving innovation from concept to post-silicon validation. The ideal candidate will have strong technical, problem-solving, and communication skills, with experience in profiling software workloads, defining low-level software interfaces, SOC hardware design, and algorithm development. | — | 0 |