Intel
- HQ
- Santa Clara, US
- Founded
- 1968
- Size
- 120,000+
- Website
- intel.com
Currently tracking 56 active AI roles, down 27% versus the prior 4 weeks. Primary focus: Serve · Engineering. Salary range $122k–$414k (avg $253k).
Intel currently has 84 active job listings related to artificial intelligence. The majority of these roles, 51%, are focused on serving infrastructure, with agents representing another significant portion at 24%. Engineering is the most frequent function for these positions. The company is actively hiring in the United States, China, and Mexico. Frequent technical tags include model serving, inference infrastructure, and agent orchestration. In the last 30 days, Intel has added 73 new AI roles, representing a 52% increase compared to the previous 30-day period.
Intel currently has 59 active AI-related roles in our index. The most common open titles are: AI Software Engineering Intern (3), AI Software Engineer Intern (2), GenAI Software Solutions Engineer (2), Graduate Talent (GenAI Software Solutions Engineer) (2), AI Algorithm Engineer. Most positions are in Engineering and Research.
Intel's active AI hiring is concentrated in: serving infrastructure (49%), agents (29%), application (8%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
Intel is hiring AI talent in: United States (28 roles), China (7 roles), Mexico (6 roles), Malaysia (6 roles).
Job postings at Intel most frequently reference: model serving, inference infra, agent orchestration, rag, tool use.
In the past 30 days, Intel has posted 28 new AI-related roles. That is a -63% change versus the prior 30 days (75 → 28).
| Title | Stage | AI score |
|---|---|---|
| FVCTO - Formal Verification Engineer This role focuses on formal verification of IP and/or SoC microarchitecture using model checking and equivalence checking algorithms. The engineer will create verification plans, abstraction models, develop formal proofs, and maintain verification infrastructure. Collaboration with RTL developers and architects is key. | — | 0 |
| Board and System Debug Engineer This role is for a Board and System Debug Engineer at Intel, focusing on supporting ODM operations during NPI and HVM ramp. Responsibilities include providing debug support, delivering technical training, testing production failed parts, managing documentation, and collaborating with cross-functional teams. Requires a degree in Electrical/Electronic/Computer Engineering or equivalent, with strong debugging skills and familiarity with debug tools. Scripting knowledge (Python) is a plus. | — | 0 |
| CPU–SoC Mask Layout Designer (Diploma Level Contract role) - Silicon Engineering Group (SiG) |
| — |
| 0 |
| Manufacturing Operation Manager Manufacturing Operations Manager role at Intel in Malaysia, focused on leading teams to ensure factory operations, equipment maintenance, and repair for optimal performance. Responsibilities include managing workflow, responding to issues, collaborating with engineering, and developing long-term strategies for manufacturing capabilities. Requires a Bachelor's degree and 2 years of experience in manufacturing operations, with expertise in semiconductor manufacturing principles and factory floor planning. | — | 0 |
| Sr. Infrastructure Engineer - Observability and Monitoring This role focuses on deploying, configuring, and managing enterprise observability and monitoring infrastructure, specifically Elastic, Logstash, Kibana, and Kafka environments. It involves implementing automation scripts for efficiency and reliability, optimizing Elasticsearch performance, designing data ingestion pipelines, and creating dashboards for operational insights. The position requires expertise in infrastructure engineering and scripting languages. | — | 0 |
| Senior Phase Gates Engineer This role is for a Senior Phase Gate Engineer at Intel Foundry, focusing on managing and improving the phase gate process for semiconductor manufacturing. The role involves driving strategic outcomes, orchestrating cross-functional teams, optimizing performance, enabling innovation, and solving complex technical and business problems within the semiconductor industry. While the company emphasizes its role in the 'AI-Era', the core responsibilities are in program and process management for semiconductor production, not direct AI/ML model development or deployment. | — | 0 |
| IP Design Verification Engineer Intel is seeking an IP Design Verification Engineer with 6+ years of experience in Pre-Si verification. The role involves developing IP verification plans, test benches, and simulation models to ensure design specifications are met. Responsibilities include debugging issues, collaborating with cross-functional teams, and maintaining verification infrastructure. Requires strong skills in Specman “e” / System Verilog and understanding of verification methodologies. | — | 0 |
| Sr. Substrates Development and Ramp Engineer This role supports management in improving Intel's supply chain and logistics strategy, focusing on process and quality improvements, cost control, production yield, and exploring emerging technologies. The engineer will define material inspection methodology, support product long-range planning, lead supplier selections, perform risk mitigation, establish control standards, monitor KPIs, drive supplier process validation, and manage quality excursions. | — | 0 |
| Manufacturing Operators Manufacturing Operators at Intel in Malaysia are responsible for performing product manufacturing and assembly tasks, operating equipment, collecting and evaluating operating data, and driving process improvements to meet industry standards and customer specifications. The role involves working in shifts and requires basic computer literacy and problem-solving skills. | — | 0 |
| Advanced Packaging Materials Supply Chain Engineer Supply Chain Engineer at Intel responsible for developing and executing supply chain strategies, ensuring supplier process and product readiness, and managing supplier relationships to meet cost, quality, availability, technology, and environmental goals within the semiconductor industry. | — | 0 |
| Power and Performance Architect This role focuses on defining and optimizing power and performance targets for Intel's products, collaborating with various engineering teams. Responsibilities include driving SoC PnP projections, developing power and performance models, and defining targets across development phases. The role requires strong system-level thinking, technical judgment, and leadership skills. | — | 0 |
| Lead Design Verification Engineer Lead Design Verification Engineer for Intel's Silicon Chassis team, responsible for defining and executing verification strategy for critical chassis and interconnect IP programs. Requires deep DV expertise, protocol and memory subsystem knowledge, and collaboration across design, software, and methodology teams. The role involves leading the development of verification environments, driving functional signoffs, and mentoring engineers. AI-assisted workflows are integrated into daily development. | — | 0 |
| Factory Automation Support Engineer - Shift 5 Support Engineer for Factory Automation Applications, Databases, or Platforms/Infrastructure in semiconductor manufacturing factories. Requires troubleshooting, project work, and development in Java, Python, C#, or other object-oriented programming languages. Experience in Semiconductor Process Engineering, Semiconductor Manufacturing, or Factory Automation is required. | — | 0 |
| Graduate Talent (Memory Design) This role is for a Graduate Talent in Memory Design at Intel, focusing on the pathfinding and development of advanced memory technology and circuits. Responsibilities include PPA optimization, product/design enablement, IC layout, memory array/IP design, circuit innovation, testchip design, and pre/post-Si validation. The role requires a Bachelor/Master/PhD in Electrical Engineering or related STEM field, proficiency in programming languages like Python, and familiarity with Unix/Linux. | — | 0 |
| Graduate Talent (PDK QA Engineer) This role is for a Graduate Talent (PDK QA Engineer) within Intel's Design Technology Platform (DTP) organization, focusing on the Process Design Kit (PDK) group. Responsibilities include validating PDK quality for custom design components and developing regression test suites to ensure PDK accuracy across various EDA flows and process nodes. The role requires knowledge of VLSI semiconductor devices, electronic circuits, and familiarity with EDA tools. | — | 0 |
| Graduate Talent (Platform Hardware Design Engineer) Seeking a Graduate Talent Platform Hardware Engineer to support the architecture, bring-up, validation, and execution of platform hardware for test chip and validation programs. Responsibilities include board-level execution, power-on, debug, test plan execution, data collection, and documentation. The role involves collaboration with cross-functional teams and support for sustaining activities. | — | 0 |
| Reliability Verification Technical Manager This role manages a team of engineers responsible for developing, validating, and optimizing Process Design Kits (PDKs) and design methodologies for Intel's advanced process nodes. The focus is on ensuring the quality and robustness of PDK collateral for internal and external design communities, particularly in ASIC EM/IR, ESD PERC, and High Voltage domains. The manager will drive innovation in tools and flows, collaborate with manufacturing and design teams, and conduct root cause analyses for issues. | — | 0 |
| Graduate Talent (PDK QA Engineer) This role is for a Graduate Talent (PDK QA Engineer) at Intel, focusing on the Quality validation of ASIC Design components within the Design Technology Platform/Process Design Kit (PDK) group. Responsibilities include developing regression test suites, executing them to validate PDK elements like pcells and techfiles, developing layout designs for verification, and developing circuit designs for simulations. The role requires proficiency in programming languages like TCL, Perl, or Python, and Unix/Linux knowledge. | — | 0 |
| Analog and Mixed Signal Design Engineer Designs and develops analog and mixed-signal circuits for Intel's Advanced Design Foundational IP Organization, focusing on pathfinding and development of advanced logic, memory, and analog/mixed-signal circuits for Intel's process technology. | — | 0 |
| Accountant Accountant role at Intel in Malaysia, focusing on preparing, analyzing, and validating financial records, ensuring compliance with global financial standards (IFRS, US GAAP), managing auditor interactions, and driving process improvements. Requires proficiency in accounting principles, financial systems (SAP S4, SQL, Power BI), and SOX compliance. | — | 0 |
| Graduate Talent (Memory Design) This role is for a Graduate Talent in Memory Design at Intel, focusing on the pathfinding and development of advanced memory technology and circuits. Responsibilities include PPA optimization, product/design enablement, IC layout, memory array/IP design, circuit innovation, testchip design, and pre/post-Si validation. The role requires a Bachelor/Master/PhD in Electrical Engineering or related STEM field, proficiency in programming languages like Python, and familiarity with Unix/Linux. | — | 0 |
| Graduate Talent (Memory Design) This role is for a Graduate Talent in Memory Design at Intel, focusing on the pathfinding and development of advanced memory technology and circuits. Responsibilities include PPA optimization, product/design enablement, IC layout, memory array/IP design, circuit innovation, testchip design, and pre/post-Si validation. The role requires a Bachelor/Master/PhD in Electrical Engineering or related STEM field, proficiency in programming languages like Python, and familiarity with Unix/Linux. | — | 0 |
| Formal Verification Lead Lead formal verification efforts for complex CPU designs, developing environments, creating models and properties, analyzing failures, and guiding team members. Requires Master's degree and 8+ years of experience in formal verification, with proficiency in relevant tools and languages. | — | 0 |
| CPU Formal Verification Lead Lead formal verification efforts for complex CPU designs (i9, i7, i5, Xeon processors). Develop environments, create models and properties, analyze failures, and guide team members. Stay updated on formal verification technologies and develop new methodologies. | — | 0 |
| Semiconductor Manufacturing Engineer Semiconductor Manufacturing Engineer responsible for operational support, process optimization, and new product introduction in a fabrication facility. This role involves analyzing factory metrics, developing manufacturing plans, and collaborating with engineering and automation teams to ensure efficient production and delivery schedules. | — | 0 |
| Process and Equipment Engineer Process and Equipment Engineer at Intel in Malaysia, responsible for optimizing high-volume manufacturing equipment and processes for integrated circuit production. This role involves ensuring precision, quality, cost efficiency, and technology scaling, with opportunities for global process transfer and continuous improvement. | — | 0 |
| Process and Equipment Engineer Process and Equipment Engineer at Intel in Malaysia, focusing on optimizing high-volume manufacturing equipment and processes for integrated circuits. Responsibilities include testing, defect minimization, implementing process modifications, building capacity, executing maintenance, developing excursion prevention systems, managing equipment installation, and collaborating with cross-functional teams for technology transfer. | — | 0 |
| Graduate Talent (Physical Design Engineer) This role is for a Graduate Talent (Physical Design Engineer) at Intel, focusing on Foundational IP (FIP) integration QA within the Foundry Technology Development group. The responsibilities include using industry standard tools for RTL to GDS design flow, scripting and automation, developing new IP-level quality checks, and interacting with EDA tool vendors and internal IP development teams. A key aspect involves applying data analytics and AI/ML techniques to optimize processes and improve quality. | — | 0 |
| Industrial Engineer (Data Analytics) (Contract role) Industrial Engineer specializing in automation for semiconductor manufacturing, focusing on designing and implementing solutions to enhance operational efficiency. The role involves programming (Python), data management (SQL, NoSQL), data analysis, process optimization, and utilizing visualization tools. | — | 0 |
| Graduate Talent (Product Development QRE) Develops and executes product qualification strategies and plans, ensuring adherence to release criteria. Performs risk assessments, defines quality and reliability goals, and contributes to the development and validation of components, boards, and systems. Analyzes specifications, ensures manufacturability, and resolves quality issues. Monitors post-silicon quality results and drives improvements for future products. | — | 0 |
| Signal Integrity Intern Internship role supporting the design, development, and validation of platform hardware and board-level solutions, focusing on component evaluation, PCB layout reviews, and electrical analysis. Requires collaboration with cross-functional teams and application of signal integrity and hardware design principles. | — | 0 |
| CPU Verification Engineer This role focuses on the functional verification of CPU logic, ensuring design specifications are met. Responsibilities include developing IP verification plans, test benches, and simulation models, debugging issues in the presilicon environment, and collaborating with design and architecture teams. The role requires experience with hardware modeling languages and validation/debug experience. | — | 0 |
| Facilities Mechanical and Controls Engineer Facilities Mechanical and Controls Engineer responsible for ensuring the reliability, performance, and safety of mechanical, HVAC, and control systems in critical environments. This role involves system design, analysis, troubleshooting, project development, and oversight of integrated facilities management partners and external vendors. Requires a Bachelor's degree in Mechanical Engineering and 5+ years of experience with mechanical and control systems. | — | 0 |
| Senior Technical Lead -Power & BatteryLife Designs, develops, and executes power and performance plans for IPs and SoCs. Identifies, builds, and maintains power, thermal, performance/watt optimizations, and characterizations for IPSoC power and performance goals. Conducts feature analysis from power and performance standpoint and drives to close any gaps between observed behavior and target on platforms in development. Provides recommendations for future architectures. Develops and enhances innovative tools for architectural performance analysis. Develops methodologies and models to drive continuous improvements in optimization of power and performance configurations to meet market requirements. Ensures platform and its components are optimized for performance and power balance. Identifies power activity zones and works with design, architecture, binning/technology, and manufacturing teams on ways to meet power consumption goals. Works cross functionally on analysis, validation, and tuning of architectures and features that advance the state of art in performance and efficiency. | — | 0 |
| RTL Design & Micro-Architecture Engineer RTL Design & Micro-Architecture Engineer for next-generation scalable data centers supporting AI workloads. Responsibilities include RTL design, coding, simulation, integration, and verification of SoC designs. Requires System Verilog, digital design fundamentals, and simulation tools. | — | 0 |
| Lad Engineering Technician- Temporary Position This role involves performing technical power and voltage regulator validation, conducting engineering tests, and supporting engineering activities for Intel's data center innovations. Responsibilities include using lab instrumentation, reading schematics, and maintaining lab operations. The role requires an Associate's degree or higher in Electronics or a similar technical discipline, with at least 1 year of experience in platform rework, soldering, and using oscilloscopes. Intermediate English proficiency is also required. | — | 0 |
| Experienced Facilities Electrical Engineer - Kiryat Gat Experienced Facilities Electrical Engineer responsible for the reliability and continuous improvement of Mega plant electrical systems, including electrical distribution, Medium Voltage systems, low voltage Centre, UPSs, Emergency Generator, and VFDs, supporting safe, reliable, and efficient plant operations. Collaborates with local and global teams to ensure consistency with global standards. | — | 0 |
| Graduate Talent (PDK Development Engineer) This role focuses on developing and supporting Process Design Kits (PDKs) for Intel Foundry, specifically involving physical layout verification (DRC, LVS, RC extraction) and ESD protection verification using industry-standard EDA tools. The engineer will work on runset development, QA plans, debugging, and enhancing runset quality and usability for advanced Intel process technologies. | — | 0 |
| Graduate Talent (PDK Development Engineer) This role focuses on developing and supporting Process Design Kits (PDKs) for Intel Foundry, specifically involving physical layout verification (DRC, LVS, RC extraction) and ESD protection verification using industry-standard EDA tools. The engineer will work on runset development, QA plans, debugging, and enhancing runset quality and usability for advanced Intel process technologies. | — | 0 |
| Senior CPU Physical Design Engineer Senior CPU Physical Design Engineer responsible for the design and delivery of high-performance CPU blocks from RTL to GDS, including synthesis, floorplanning, place and route, CTS, timing closure, and verification. Requires 10+ years of experience with industry-standard EDA tools. | — | 0 |
| CPU Physical Design Engineer This role is for a CPU Physical Design Engineer at Intel, focusing on the design and delivery of high-performance CPU blocks from RTL to GDS. Responsibilities include executing the full physical design flow, leading verification and sign-off, and optimizing designs for power, performance, and area using industry-standard EDA tools. The role requires a BSc or MSc degree in Electrical or Computer Engineering and at least 7 years of experience in physical design. | — | 0 |
| Intel Foundry Advanced Device Development Engineer The role involves designing, executing, and analyzing experiments in a semiconductor cleanroom to meet engineering specifications for advanced device development. Responsibilities include setting performance targets, assessing silicon readiness, defining test structures, and using data analysis techniques (statistics, data mining) on electrical-test, yield, and fab data to guide future development. Experience with semiconductor materials, fabrication, device physics, and electrical characterization is required, with preferred experience in advanced transistor structures, simulation, SPC/DOE, and analytics/scripting languages. | — | 0 |
| CPU Pre-Si Verification Engineer This role is for a pre-silicon verification engineer on the E-Core CPU team. The primary responsibility is to verify new and existing features for Intel's next-generation CPU IP by developing test plans, test scenarios, simulation components, and functional coverage, and debugging digital simulations. The role requires in-depth computer architecture knowledge and experience with hardware description languages and test bench development. | — | 0 |
| Director Government Affairs The Director of US Government Affairs will manage outreach to the Executive Branch and Congressional Republicans to advocate and shape policies that advance American semiconductor manufacturing and technology leadership. This role involves federal lobbying efforts, advocating for Intel's positions on critical policy issues, and leading lobbying efforts on technology issues like Quantum Computing, Cybersecurity, and Data. | — | 0 |
| Director Government Affairs This role is for a Director of US Government Affairs at Intel, focusing on lobbying the Executive Branch and Congressional Republicans to advocate for policies supporting American semiconductor manufacturing and technology leadership. The responsibilities include crafting and executing federal lobbying efforts, advocating for Intel's positions on critical policy issues, leading lobbying efforts on export controls and investment restrictions, and building relationships with policymakers. The role requires at least 7 years of experience in federal government affairs, with a focus on manufacturing policy, and a strong legislative background. | — | 0 |
| Senior Facilities Electrical Engineer Senior Facilities Electrical Engineer to lead electrical infrastructure projects and maintain critical electrical systems across Intel's facilities in Malaysia. Responsibilities include designing, implementing, and optimizing electrical systems, ensuring safety, reliability, and compliance with codes and standards. Requires a Bachelor's degree in Electrical Engineering and 7-10 years of experience. | — | 0 |
| Mixed Signal Logic Verification Engineer Senior/Staff VLSI Verification Engineer with 11-15 years of experience in complex SoC/ASIC verification, focusing on UVM/System Verilog testbench architecture, Mix signal IP verification strategy, and post-silicon debug. Responsibilities include defining verification plans, mentoring junior engineers, ensuring coverage closure, and collaborating with architects. Experience with formal verification methods is also required. | — | 0 |
| Platform Debug Engineer- Intern Intern position focused on platform debug engineering for silicon products, involving functional, power, and performance validation, debugging, and potentially test automation and infrastructure development. Requires familiarity with Python, C/C++, and IA-based PC knowledge. AI experience is preferred but not core. | — | 0 |
| Graduate Talent (Physical Design Engineer) This role is for a Graduate Talent (Physical Design Engineer) at Intel, focusing on Foundational IP (FIP) integration QA within the Foundry Technology Development group. The responsibilities include using industry standard tools for RTL to GDS design flow, scripting and automation, developing new IP-level quality checks, and interacting with EDA tool vendors and internal IP development teams. A key aspect involves applying data analytics and AI/ML techniques to optimize processes and improve quality. | — | 0 |
| CPU Pre-Silicon Verification Lead Lead a team responsible for pre-Silicon functional verification of Intel's latest CPUs, developing test plans, simulation models, and test benches to ensure design requirements are met. Focus on driving strategic tool/flow/methodology initiatives to reduce validation cycle time and ensure first-pass silicon success. Requires technical leadership and managerial experience in pre-Silicon verification environments. | — | 0 |