Currently tracking 56 active AI roles, down 27% versus the prior 4 weeks. Primary focus: Serve · Engineering. Salary range $122k–$414k (avg $253k).
Intel currently has 84 active job listings related to artificial intelligence. The majority of these roles, 51%, are focused on serving infrastructure, with agents representing another significant portion at 24%. Engineering is the most frequent function for these positions. The company is actively hiring in the United States, China, and Mexico. Frequent technical tags include model serving, inference infrastructure, and agent orchestration. In the last 30 days, Intel has added 73 new AI roles, representing a 52% increase compared to the previous 30-day period.
Intel currently has 59 active AI-related roles in our index. The most common open titles are: AI Software Engineering Intern (3), AI Software Engineer Intern (2), GenAI Software Solutions Engineer (2), Graduate Talent (GenAI Software Solutions Engineer) (2), AI Algorithm Engineer. Most positions are in Engineering and Research.
Intel's active AI hiring is concentrated in: serving infrastructure (49%), agents (29%), application (8%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
Intel is hiring AI talent in: United States (28 roles), China (7 roles), Mexico (6 roles), Malaysia (6 roles).
Job postings at Intel most frequently reference: model serving, inference infra, agent orchestration, rag, tool use.
In the past 30 days, Intel has posted 28 new AI-related roles. That is a -63% change versus the prior 30 days (75 → 28).
| Title | Stage | AI score |
|---|---|---|
| Linux Development Engineer Develops and integrates software across the Linux stack, including drivers, OS, frameworks, and applications, with a focus on Bluetooth SW and tools. Requires experience in C/C++, embedded systems, Linux kernel, RTOS, and Linux device drivers. | — | 0 |
| Memory Validation Manager Seeking a Senior PC Memory Module and Storage Validation Engineer to lead validation and qualification for next-generation memory and storage solutions in PC and IoT platforms. Responsibilities include leading validation activities, debugging system-level failures, characterizing performance, developing automation, ensuring compliance with industry standards, and managing contractor engineers. | — | 0 |
| Mechanical Tooling Engineer Mechanical Tooling Engineer responsible for developing and enabling Intel's next-generation advanced packaging and test technologies. This role involves the definition, design, and deployment of tooling and hardware solutions for semiconductor packaging, including process integration, equipment solutions, and feasibility studies. Responsibilities include leading the design and development of manufacturing processes, optimizing operating equipment, and collaborating with suppliers. |
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| 0 |
| Silicon Packaging Design Engineer This role is for a Silicon Packaging Design Engineer at Intel Foundry Services, focusing on the end-to-end development of advanced substrate designs. Responsibilities include physical layout, routing, substrate fit studies, defining design rules, and collaborating with cross-functional teams to optimize designs for performance, cost, and manufacturability. The role requires experience with package design tools and physical layout aspects of substrate design. | — | 0 |
| GPU Thermal Management Design Engineer Seeking a Thermal Management Design Engineer to architect, simulate, and validate thermal management and fan control features for Intel dGPU products. The role involves designing and optimizing thermal solutions and platform designs, influencing upstream teams, and collaborating with various engineering disciplines and partners to ensure product delivery to technical and schedule requirements. | — | 0 |
| Liquid Industrial Waste Systems Technology Development and Transfer Engineer This role focuses on the development, operation, and maintenance of liquid industrial wastewater and water systems. It involves ensuring safety, quality, environmental compliance, and managing system capacity. The engineer will troubleshoot water and chemical related issues, interpret analytical instrument data, prepare technical reports, manage budgets, and implement new analysis methods to improve accuracy and efficiency. The role also includes managing the Model Of Record and Technology Transfer for global manufacturing sites. | — | 0 |
| EDA Design Flow Development Engineer Develop and maintain transistor-level electromigration (EM) and IR drop analysis flows for custom IPs, embedded memories, SRAMs, analog/mixed-signal interfaces, and high-performance custom macros across advanced semiconductor technologies. Focuses on CAD methodology, automation infrastructure, power integrity analysis flows, and silicon correlation for transistor-level reliability verification. | — | 0 |
| EDA Tools Hardware Engineer This role focuses on developing and maintaining transistor-level timing characterization flows for custom IPs and memories across advanced semiconductor technologies. The engineer will work with EDA vendors and design teams to enable scalable and silicon-accurate timing, power, and noise modeling flows, requiring expertise in SPICE-based characterization and Liberty model generation. | — | 0 |
| EDA Tools Hardware Engineer This role focuses on developing and maintaining full-chip physical implementation flows for hardware design tools, including floor planning, integration, placement, routing, and power grid analysis. It involves enabling scalable SoC assembly and defining methodologies for hierarchical design reuse. | — | 0 |
| Business Development Manager Business Development Manager at Intel, focusing on driving strategic business opportunities, complex transactions, and fostering partner relationships within the wireless and PC OEM/IoT ecosystem. Responsibilities include market research, building business cases, contract negotiation, and influencing platform/product portfolio decisions. Requires extensive experience in business development, deal negotiation, and stakeholder management, with a strong technical understanding and business acumen. | — | 0 |
| Accountant Accountant role focused on financial accuracy, compliance, and operational excellence within Intel's global finance group. Responsibilities include preparing and analyzing financial records, supporting close processes, conducting financial data analysis, collaborating with auditors, ensuring internal controls (including SOX), and identifying process improvement/automation opportunities. Requires a Bachelor's degree in Accounting and 1-2 years of experience, with proficiency in ERP systems and US GAAP. | — | 0 |
| Mask Manufacturing Technician This role is for a Mask Manufacturing Technician at Intel, responsible for operating and maintaining mask manufacturing modules, ensuring safety, quality, and output goals. It involves process improvement, troubleshooting, and training others in a high-volume manufacturing environment. | — | 0 |
| Mask Manufacturing Technician This role is for a Mask Manufacturing Technician at Intel, responsible for operating and maintaining mask manufacturing modules, ensuring safety, quality, and output goals. The technician will also be involved in process improvement, troubleshooting, and training. | — | 0 |
| Software Engineering Manager Lead a team of software engineers and architects developing and validating cutting-edge software solutions for Intel's product segments or technologies, driving success across the stack from firmware to applications and platforms. Foster collaboration, set goals, and enable professional growth to ensure high-quality deliverables in a productive, inclusive environment. | — | 0 |
| Manufacturing Training Technician This role focuses on designing, organizing, and delivering technical training for manufacturing and process engineering employees at Intel. It involves developing training materials, coordinating logistics, tracking training records, and evaluating training effectiveness. The goal is to equip the workforce with the necessary skills for manufacturing operations. | — | 0 |
| Power Delivery Design Engineer Designs and Validates Power delivery solutions for Reference/Validation boards, including low voltage DC-DC regulators and power management circuits for CPU/SOC based platforms. Involves schematics capture, PCB layout review, component selection, BOM release, and lab validation. | — | 0 |
| E-core CPU Layout Design Engineer This role is for an E-Core (Atom) CPU Layout Design Engineer responsible for the physical implementation of memory compilers and RF custom IP blocks for Intel Atom microprocessors. The engineer will work on transistor/device and cell level planning, layout, assembly, and routing, utilizing CAD tools for layout editing, verification, DFM, and quality. Responsibilities include bridging circuit engineering, design automation, and mask design, performing analysis for IR drop and reliability, and driving methodology refinement for memory compilers. The role requires strong programming skills in UNIX shell script, Tcl, and Perl. | — | 0 |
| Platform Integration Engineer Intel is seeking an experienced Platform Integration Engineer for the Intel Chassis Group. The role involves understanding SoC chassis requirements, designing and developing high-performance networks-on-chip using chassis foundation library components, and coordinating with the foundation IP development team. Requires 6+ years of experience in SOC and/or IP design, with preferred experience in microarchitecture, design IP systems, and fabric design/integration. | — | 0 |
| Accountant Accountant role supporting monthly financial close processes, including posting payroll entries, reconciliations, and reporting, with a focus on US GAAP compliance and process improvement. | — | 0 |
| Manufacturing Failure Analysis Engineer Manufacturing Failure Analysis Engineer at Intel, focusing on identifying and resolving failures in semiconductor manufacturing processes, products, and technologies for advanced packaging. Responsibilities include conducting failure analysis, developing methodologies, investigating failure mechanisms, recommending corrective actions, and collaborating with cross-functional teams. Requires experience in failure analysis techniques and analytical tools like SEM, FTIR, Xray. | — | 0 |
| Senior Mixed Signal Validation and Debug Engineer Senior Mixed Signal Validation and Debug Engineer responsible for developing leadership IPs for Server, Client, Networking SOCs and Intel Foundry Customers. The role involves pre-silicon to post-silicon IP characterization, test plan generation using AI driven tools and Python scripting, SOC board design reviews, Signal and Power Integrity simulations, and hands-on debug of IP related issues. Requires BS/MS/PhD in EE/CE and 6+ years of experience in post-silicon validation and debug of serial or parallel IOs, with proficiency in lab hardware and software. | — | 0 |
| PCB Layout Engineer PCB Layout Engineer responsible for the design, placement, and routing of CPU/FPGA based hardware boards, ensuring adherence to design guidelines and product specifications. Involves collaboration with mechanical teams and understanding architecture requirements. | — | 0 |
| Senior SoC Network Subsystem Architect This role is for a Senior SoC Network Subsystem Architect at Intel, focusing on defining and leading the architecture of high-performance network subsystems for next-generation IPU/DPU platforms. The role involves designing scalable, programmable networking pipelines for hyperscale and cloud data centers, with responsibilities including packet processing, QoS, scheduling, and observability features. It requires cross-functional leadership and collaboration with hardware, software, and systems teams. While the role mentions supporting AI workloads and AI/HPC scale-out networking, the core function is in network silicon architecture, not AI model development or deployment. | — | 0 |
| Senior Yield Development Engineer - Intel Foundry Senior Yield Development Engineer at Intel Foundry focused on optimizing semiconductor process technology and driving yield improvements across next-generation technology nodes. Responsibilities include identifying and resolving yield-limiting factors, developing innovative solutions, conducting advanced statistical analysis, creating data visualizations, building process development roadmaps, and collaborating with cross-functional teams (design, test, process development). Requires a Master's degree in a STEM field with 3+ years of experience in yield development or process technology, and 2+ years of experience with external customer advanced node semiconductor devices and process flow concepts. Experience with yield projection using EOL signals and in-line parameters is required. Preferred qualifications include a Ph.D., experience with data analysis systems, advanced semiconductor equipment, process development, defect density analysis, data analytics methodologies, and project management. | — | 0 |
| Senior SoC Chiplet Architect Senior SoC Chiplet Architect to define and lead the architecture strategy for multi-generation, chiplet-based SoC platforms targeting next-generation data center workloads, including AI workloads. Responsibilities include chiplet partitioning, die-to-die interconnect architecture, and system-level tradeoff analysis across performance, power, area, cost/yield, and software complexity. | — | 0 |
| Advanced Packaging Materials Sr. Commodity Manager This role is a Sr. Commodity Manager focused on advanced packaging materials within Intel's supply chain. The responsibilities include developing commodity strategies, optimizing cost, ensuring supply continuity, managing supplier relationships, leading contract negotiations, and mitigating supply chain risks. The role requires experience in supply chain/commodity management, sourcing, and negotiation, with a preference for semiconductor industry knowledge. | — | 0 |
| GPU Software Development Engineer Develops and validates software for Intel GPUs, including firmware, drivers, and APIs, optimizing performance for graphics and compute workloads, with applications in AI and data centers. | — | 0 |
| IP Logic Design Engineer Intel is seeking an IP Logic Design Engineer to develop logic designs for high-performance IPs integrated into SoC products for Client, Graphics, and Data Center markets. Responsibilities include RTL implementation, architecture specification, optimization, verification support, and post-silicon validation. | — | 0 |
| Manufacturing Technical Supervisor (Operations) This role manages a team of technicians overseeing manufacturing operations, equipment maintenance, and repair. It focuses on safety, quality, scheduling, and process streamlining to meet production goals. The role requires technical knowledge of manufacturing equipment and problem-solving skills, with a preference for experience in semiconductor manufacturing and data science tools. | — | 0 |
| Manufacturing Technical Supervisor (Operations) This role manages a team of technicians overseeing manufacturing operations, equipment maintenance, and repair. It focuses on safety, quality, scheduling, and process streamlining to meet production goals. The role requires technical knowledge of manufacturing equipment and problem-solving skills, with a preference for experience in semiconductor manufacturing and data science tools. | — | 0 |
| Senior SoC Compute/Memory Subsystem Architect Intel is seeking a Senior SoC Compute/Memory Subsystem Architect to define and drive the architecture of compute complexes and high-performance memory subsystems for next-generation IPU/DPU platforms. This role involves end-to-end architecture of CPU clusters, cache hierarchies, coherency models, and memory subsystems, optimizing for performance, scalability, power efficiency, and programmability in hyperscale environments. Responsibilities include defining compute and memory strategies, IO memory and virtualization architecture, system-level integration, and developing a multi-generation architecture roadmap, collaborating with cross-functional teams. | — | 0 |
| Physical Design Methodology Engineer This role focuses on physical design methodology for semiconductor manufacturing, specifically in design-technology co-optimization (DTCO) and system-design co-optimization (STCO). The engineer will create methodologies, models, and flows for advanced design rules, characterize these models through silicon validation, and optimize silicon designs for power, performance, and area (PPA). The role involves working with EDA tools and ensuring IP and SoC designs meet manufacturing process technology requirements. | — | 0 |
| Senior Infrastructure and DevOps Engineer This role focuses on designing, deploying, and maintaining Linux-based infrastructure for large-scale modeling, simulation, and data analysis workflows. The engineer will manage CI/CD pipelines, automation for build systems, and ensure efficient execution of compute-intensive workloads. Key responsibilities include monitoring performance, reliability, and observability of these systems, and collaborating with architects and developers to improve tooling and scalability. | — | 0 |
| PERC ESD EDA Engineer Develops PERC ESD rule decks for latest Intel technologies, enabling design teams to get to market faster. Collaborates with internal and external teams, defines QA requirements, and leads innovation initiatives for ESD/LU verification automation. | — | 0 |
| Medium Voltage Distribution Electrician This role involves assembling, evaluating, testing, and maintaining electrical or electronic wiring, equipment, appliances, and apparatus. The electrician will troubleshoot and repair malfunctioning equipment, advise on management of equipment, review wiring blueprints, conduct maintenance repairs, and rectify system failures. They will operate medium voltage electrical systems, inspect electrical systems, interpret technical drawings, run tests on generators and backup systems, and ensure adherence to safety and performance standards. The position also involves installing and preserving the functionality of wires, plugs, panel boards, switchgear, and switchboards, responding to fault requests, providing reliability suggestions, and commissioning new electrical facilities equipment. | — | 0 |
| Medium Voltage Distribution Electrician The role of a Medium Voltage Distribution Electrician at Intel involves assembling, evaluating, testing, and maintaining electrical wiring, equipment, and apparatus. Responsibilities include troubleshooting and repairing malfunctioning equipment, advising on equipment management, reviewing blueprints, conducting maintenance, and rectifying system failures. The electrician will operate medium voltage electrical systems, inspect electrical systems for faults, interpret technical drawings, run tests on generators, and ensure adherence to safety standards. This is a hands-on role requiring physical work in potentially challenging conditions and adherence to specific safety protocols. | — | 0 |
| CAD/EDA Tools Automation Engineer This role focuses on designing, developing, testing, and debugging software tools and flows for hardware design automation, process design, and manufacturing. It involves capturing requirements, writing functional and test code, automating builds and deployments, and performing various levels of testing. The role requires a Master's or PhD in a technical engineering discipline with experience in programming languages like Python, Tcl, or C++, and Linux environments. | — | 0 |
| IAO Change Manager Intel Contract Employee This role is for a Change Management Practitioner supporting the IAO IF Intel Foundry transformation, focusing on people, process, and technology changes, particularly around ERP and Supply Chain Planning tools. The goal is to foster engagement, drive adoption, and ensure successful execution of transformational change. | — | 0 |
| Post-silicon Validation and Debug Engineer This role is for a Post-Silicon Validation and Debug Engineer focused on CPU/SOC products for consumer devices. The responsibilities include developing and executing validation plans, designing and debugging tests, collaborating with cross-functional teams, analyzing issues, and driving automation. The role requires experience in post-silicon validation, pre-silicon verification, or design, particularly in CPU/SOC domains, and familiarity with silicon validation tools and scripting languages. | — | 0 |
| Senior Staff Analog Circuit Design Engineer - SerDes Senior Staff Analog Circuit Design Engineer focused on validating SerDes technologies, ensuring reliability, functionality, and performance of mixed signal designs. Responsibilities include developing validation plans, methodologies, root cause analysis, and maintaining post-silicon validation workflows. | — | 0 |
| Operations Research Engineer Designs, develops, and applies advanced engineering and mathematical models, including simulation and optimization frameworks, to solve complex Intel manufacturing and supply chain challenges. Focuses on fabrication and assembly/test environments, building and deploying decision algorithms, heuristics, optimization models, and simulation tools. | — | 0 |
| Mask Manufacturing Technician Manufacturing technician responsible for operating and maintaining production equipment, ensuring product quality, and supporting process improvements in a semiconductor mask manufacturing environment. | — | 0 |
| Mask Manufacturing Technician This role involves performing manufacturing and assembly tasks in a production process, operating equipment, collecting and evaluating operating data for optimization, and conducting quality control evaluations on raw materials and final products. It also supports developing and testing new products and processes, and maintaining production logs. The role requires a High School Diploma or GED with relevant experience or an Associate's degree in STEM. | — | 0 |
| Senior Analog Design Engineer This role is for a Senior Analog Design Engineer at Intel, focusing on designing, developing, and optimizing analog and mixed-signal integrated circuits for high-speed serial IO and die-to-die interfaces. Responsibilities include circuit design, simulation, layout, technical leadership, and silicon validation. The role requires expertise in analog circuit design, collaboration with cross-functional teams, and experience with industry-standard tools and advanced process technologies. | — | 0 |
| Analog IP Design Execution Manager Technical execution manager for Hard IP and Test Chip Development team, responsible for delivering industry-defining analog and mixed signal IP for Intel's customers. This role involves leading technical teams through the entire IP lifecycle, from planning and pre-silicon execution to post-silicon validation and launch, ensuring timely delivery with committed content and quality. Requires strong problem-solving, communication, and program management skills, with familiarity in AI/ML-driven design productivity techniques. | — | 0 |
| Foundry Site Quality Program Manager The Quality Program Manager for the Chandler Assembly site will be responsible for measuring and reporting on site quality, generating and implementing factory quality improvement programs, supporting quality meetings and improvement teams, and acting as a site auditor for ISO9K/IATF Cert and internal audit programs. This role focuses on leading initiatives aligned with Intel's Foundry Quality Pyramid, identifying risks, preventing excursions, and implementing fixes across the factory, while also supporting QMS elements for new technology certification and continuous improvement of quality metrics and systems. | — | 0 |
| Senior Supply Chain Business Analyst This role is for a Senior Supply Chain Business Analyst at Intel, focusing on managing technology projects and programs within the supply chain. The responsibilities include developing project plans, managing implementation processes, ensuring alignment with business objectives, monitoring schedules, assessing dependencies, and communicating project status. The role requires a Bachelor's degree and 6+ years of experience in technology project/program management, with proficiency in Agile and Waterfall methodologies. | — | 0 |
| Strategic/Development Industrial Engineer This role focuses on developing and executing long-term capacity and capital strategies within a foundry organization, optimizing factory resources and capital investment through advanced data analysis and modeling. It involves collaborating with cross-functional teams to drive continuous improvement and influence business strategies. | — | 0 |
| Senior SoC Architect – Unified Intel Chassis (UIC) IP and Platform Architecture Senior SoC Architect role focused on defining and driving architecture specifications for Unified Intel Chassis (UIC) IP components and subsystems. Responsibilities include power optimization, scalability, platform performance analysis, and collaboration with cross-functional teams. The role requires expertise in SoC IP architecture, AMBA protocols, and architecture specification writing. Familiarity with AI tools for developing machine-readable specifications is mentioned as a plus. | — | 0 |
| RTL Design Engineer Senior RTL Design Engineer with 5+ years of experience in logic design and integration of high-speed Mixed-Signal IP, focusing on digital blocks for SerDes components. Responsibilities include RTL development, mixed-signal interface design, IP compliance, front-end implementation, and collaboration with analog and verification teams. | — | 0 |