Intel
- HQ
- Santa Clara, US
- Founded
- 1968
- Size
- 120,000+
- Website
- intel.com
Currently tracking 56 active AI roles, down 27% versus the prior 4 weeks. Primary focus: Serve · Engineering. Salary range $122k–$414k (avg $253k).
Intel currently has 84 active job listings related to artificial intelligence. The majority of these roles, 51%, are focused on serving infrastructure, with agents representing another significant portion at 24%. Engineering is the most frequent function for these positions. The company is actively hiring in the United States, China, and Mexico. Frequent technical tags include model serving, inference infrastructure, and agent orchestration. In the last 30 days, Intel has added 73 new AI roles, representing a 52% increase compared to the previous 30-day period.
Intel currently has 59 active AI-related roles in our index. The most common open titles are: AI Software Engineering Intern (3), AI Software Engineer Intern (2), GenAI Software Solutions Engineer (2), Graduate Talent (GenAI Software Solutions Engineer) (2), AI Algorithm Engineer. Most positions are in Engineering and Research.
Intel's active AI hiring is concentrated in: serving infrastructure (49%), agents (29%), application (8%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
Intel is hiring AI talent in: United States (28 roles), China (7 roles), Mexico (6 roles), Malaysia (6 roles).
Job postings at Intel most frequently reference: model serving, inference infra, agent orchestration, rag, tool use.
In the past 30 days, Intel has posted 28 new AI-related roles. That is a -63% change versus the prior 30 days (75 → 28).
| Title | Stage | AI score |
|---|---|---|
| Defect Review Technician This role is for a Defect Review Technician at Intel's Advanced Packaging Command Center (APCC). The technician will be responsible for classifying, validating, and disposing of defects identified by inspection systems in wafer packaging manufacturing. The goal is to maintain quality excellence, minimize defect noise, and support systematic defect reduction initiatives. | — | 0 |
| Yield Defect Metrology Technician This role supports defect review activities in semiconductor manufacturing, focusing on defect classification, validation, and hold lot disposition to improve yield and manufacturing efficiency. The technician will analyze defect images, classify defects, verify classifications, and manage hold lot dispositions, feeding data to improve Automatic Defect Classification (ADC) accuracy. | — | 0 |
| Intel Foundry Module Development Engineer This role focuses on scientific research and development for semiconductor process technologies within Intel Foundry. The engineer will design, execute, and analyze experiments to develop manufacturing processes for next-generation technologies, integrate manufacturing steps, and ramp processes to manufacturing volumes. The role requires a strong background in scientific STEM fields with a focus on hands-on experimental research, particularly in semiconductor processing or related areas. |
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| Student Worker – Software Development Software Applications Engineering Undergraduate Intern role at Intel in Costa Rica. Responsibilities include developing, optimizing, and integrating software applications that interface with Intel products, assisting with performance optimization, and collaborating with cross-functional teams. Requires proficiency in C#, .NET, REST API principles, SQL, and Git, with foundational knowledge of cloud basics. This is an internship role focused on general software development, not AI/ML. | — | 0 |
| Silicon Architecture Graduate Intern Internship role focused on silicon architecture, performance analysis, and ISA evaluation. Involves running benchmarks, analyzing instruction patterns, and evaluating experimental ISA features using simulators and tracing techniques. Requires graduate studies in computer science or engineering with a focus on computer architecture. | — | 0 |
| Pre SIlicon Engineering Intern Internship role focused on pre-silicon engineering, specifically contributing to the functional logic verification of silicon designs. Responsibilities include developing verification plans, test benches, and supporting emulation/simulation. Requires coursework in logic design, verification, architecture, and scripting (Python, Shell). | — | 0 |
| Manufacturing Equipment Technician (MTE) - Night Shift - Shift 6 Manufacturing Equipment Technician role focused on maintaining and troubleshooting electromechanical equipment in a semiconductor cleanroom environment. Responsibilities include performing repairs, calibration, preventive maintenance, and collaborating with engineering teams to improve tool performance and yield. Requires strong problem-solving skills and ability to work in a fast-paced manufacturing setting. | — | 0 |
| Qubit Control Physical Design Engineer Intel is seeking a Qubit Control Physical Design Engineer to drive RTL-to-GDS design convergence using logic synthesis and place-and-route tools, focusing on PPA goals and backend flows. The role involves block-level physical design delivery, closure of backend flows, electrical requirements, and improving silicon yield. Responsibilities include working with CAD and PD methodology teams on industry-standard tools and their adoption in cryogenic control design, driving physical implementation through various stages (synthesis, verification, floor planning, PNR, power/clock distribution, timing closure, physical verification, ECO, sign-off), and collaborating with custom IP teams to optimize memory macros and standard cells. The engineer will also contribute to developing physical design methodologies. | — | 0 |
| Supplier Program Manager This role is for a Supplier Program Manager at Intel, focused on managing the supply chain for new product introductions (NPI) to high volume manufacturing (HVM). The responsibilities include risk mitigation, inventory optimization, supplier collaboration, and cross-functional team coordination. While the role mentions experience with AI and advanced analytics as a preferred qualification for process optimization, the core function of the job is supply chain management, not AI/ML development or research. | — | 0 |
| Quantum Error Correction Software Engineer The Quantum Error Correction Software Engineer will join the Quantum System Architecture & Software team to lead the creation, implementation, and optimization of software codes for Intel quantum hardware, and lead research and development of quantum error correction protocols for fully fault tolerant quantum computing systems. | — | 0 |
| Intel Costa Rica LE247 Compliance Integration Engineer This role focuses on the technical contract employee responsible for ensuring the safe, efficient, and effective disposal of factory equipment and assets, adhering to Intel's safety, quality, and compliance standards. It involves managing project timelines, troubleshooting technical issues related to data and databases, and identifying process improvements within semiconductor manufacturing environments. | — | 0 |
| Supply Chain Operational Lead Supply Chain Operational Lead responsible for translating business requirements into actionable strategies for risk assessment, inventory optimization, and supply chain streamlining. This role coordinates material acquisition for NPI programs, manages supplier relationships, and ensures BOM integrity, material availability, cost, and quality goals are met. The lead analyzes data, develops solutions for complex processes, and drives efficiencies through systems and tools. They also manage supplier performance, cost benchmarking, and ensure alignment with business unit production requirements. | — | 0 |
| Post Silicon Validation Engineer Intel is seeking a Post Silicon Validation Engineer to ensure the quality and performance of their cutting-edge System-on-Chip (SoC) products. This role involves developing and executing innovative validation methodologies, conducting silicon debug to resolve functional issues, and testing interactions between various SoC features. The engineer will also develop post-silicon validation infrastructure, collaborate with multidisciplinary teams, and create comprehensive validation reports. The position requires experience in post-silicon validation, proficiency with FPGA/emulation tools, and technical expertise in SoC domains like Graphics, PCIe, and Memory. | — | 0 |
| Senior Materials Program Manager - Direct Material Senior Materials Program Manager responsible for direct material procurement, supply chain optimization, inventory health, and cost efficiency for New Product Introduction (NPI) and High-Volume Manufacturing (HVM) at Intel. | — | 0 |
| Bluetooth Phy System Student Student role focused on Bluetooth PHY systems, involving pre- and post-silicon system design, RFIC architecture, calibration algorithms, system performance, and multidisciplinary problem-solving across HW, SW, RF, and Modem domains. Requires knowledge of communication systems, modulation, RFIC impairments, and link budgets. | — | 0 |
| Software Enabling and Optimization Engineer This role is for a Software Enabling and Optimization Engineer in Intel's Global Product Support team. The engineer will be responsible for customer experience, acting as a point of contact for clients, responding to inquiries, analyzing needs, and resolving platform issues. The role involves collaborating with cross-functional teams, managing support databases, and analyzing customer data to recommend process improvements. Key qualifications include experience in troubleshooting, system diagnosis, debugging, and proficiency in customer support software. Preferred qualifications include experience in Embedded Linux, Windows OS, driver development/debugging, power states, performance tuning, and Intel x86 platform architecture. | — | 0 |
| Package and PCB Layout Eng Seeking an RF Design Engineer with 6+ years of experience to design, develop, and verify RF integrated circuits and systems, including PCB and Package Layout, for wireless communication products like WLAN and Bluetooth. Responsibilities include defining floorplans, layouts, and physical designs, collaborating with cross-disciplinary teams, and ensuring compliance with design rules and manufacturing constraints. | — | 0 |
| Senior RF Integration Engineer Senior RF Integration Engineer at Intel, responsible for leading integration activities for advanced wireless connectivity silicon, working with RF circuits, developing automation tools in C#, and performing post-silicon validation. Requires B.Sc. in Electrical/Electronic Engineering and 8-12 years of experience in wireless communication systems and RF engineering. | — | 0 |
| GPU Performance Verification Engineer This role focuses on the performance verification of graphics logic components (3D graphics, media, and display) within Intel's Data Center Group. The engineer will define and develop verification plans, test benches, and simulation models, debug issues in a presilicon environment, and collaborate with cross-functional teams to ensure design specifications are met. Experience with GPU/CPU subsystems, UVM, and graphics pipelines is required. | — | 0 |
| Sr. Data Center Facilities Engineer The Sr. Facilities Engineer - Critical Environments provides senior technical leadership to ensure the reliability, safety, and performance of critical mechanical systems supporting Mission Campus data centers, critical laboratories. This role serves as the Intel technical authority for mechanical systems, while maintaining working familiarity with electrical infrastructure to support integrated decision-making across critical environments. | — | 0 |
| Ocotillo Technology Fabrication Administrative Partner Administrative Partner role supporting the OTF Planning organization at Intel, focusing on calendar management, meeting coordination, travel arrangements, expense reports, and general office support. Requires strong organizational skills, attention to detail, and proficiency with Microsoft tools. | — | 0 |
| Facilities Electrical Engineer Facilities Electrical Engineer responsible for the analysis, design, and maintenance of electrical systems within Intel's facilities, ensuring operational excellence, safety, and compliance. This includes managing projects, developing specifications, monitoring system performance, and collaborating with various teams and external partners. | — | 0 |
| Product Development Engineer - Scan Diagnostics This role focuses on the product development and manufacturing of integrated circuits, specifically involving scan diagnostics, fault identification, and yield improvement throughout the semiconductor product lifecycle. It requires expertise in DFT, diagnostic tools, and scripting for optimizing testing and analysis processes. | — | 0 |
| Packaging Module Development Engineer Develops and optimizes semiconductor packaging technologies, including interconnects and metrology, for high-volume manufacturing. Involves process development, characterization using SPC/DOE, and collaboration with cross-functional teams and suppliers. | — | 0 |
| Silicon Packaging Engineering Manager Lead a team of IC Packaging Engineers responsible for delivering advanced packaging solutions for customer programs, focusing on technical leadership, project management, and innovation in IC package design, chiplet/SOC design, and heterogeneous integration. | — | 0 |
| Ocotillo Technology Fabrication Thin Films Module Engineer This role is for a Module Engineer in a semiconductor fabrication facility, focusing on managing and improving 300mm toolsets for thin films processes. Responsibilities include ensuring safety, cleanliness, copy-exactness, monitoring control charts, achieving availability and matching targets, and driving continuous improvement in tool health, cycle time, and defect densities. The role also involves process development support, defining roadmaps, establishing procedures, selecting equipment, conducting experiments, developing solutions, establishing process control systems, and training other engineers. Experience in manufacturing, particularly semiconductor foundry, is preferred. | — | 0 |
| Analog Engineer Analog Circuit Design Engineer at Intel, focusing on designing and developing analog and mixed-signal circuits in advanced process nodes for client, server, and networking technologies. Responsibilities include circuit design, simulation, optimization, tape-out, and post-silicon validation. | — | 0 |
| Module Development Engineer This role focuses on technology development and enablement for high-volume semiconductor manufacturing, providing process integration and equipment solutions. It involves designing and developing manufacturing processes, optimizing equipment, and performing feasibility studies. The role also involves pathfinding activities for future technology roadmaps and partnering with suppliers. Qualifications include a Bachelor's degree in a relevant engineering or science field, 3+ years of experience, expertise in semiconductor processing or mechanical systems, SPC/DOE proficiency, Python/MATLAB programming, and hands-on experience with robotics, automation, vision systems, and image processing. | — | 0 |
| Construction Project Manager Construction Project Manager for Intel Foundry Construction and Sourcing (FCS) to build semiconductor manufacturing factories. Responsibilities include planning and delivering construction projects, managing scope, schedules, budgets, contracting, EHS, quality, and change management. Requires experience in major industrial facilities and large-scale construction projects, with specific experience in contract management, schedule/budget development, change control, cleanroom, mechanical/process systems, and semiconductor construction. | — | 0 |
| APTD SWA Module Engineer On-Shift (Dayshift) Module Engineer On Shift (MEOS) responsible for real-time factory support in advanced packaging technology development, addressing equipment, process, and product issues to ensure continuous manufacturing operations. Requires problem-solving, communication, and adaptability in a 24x7 environment. | — | 0 |
| Facilities Mechanical and Controls Engineer - Data Center This role is for a Facilities Mechanical and Controls Engineer focused on ensuring the reliability, performance, and safety of mechanical, HVAC, and control systems within data centers and critical facilities. Responsibilities include system design, analysis, troubleshooting, project development, and overseeing maintenance operations. The role requires a Bachelor's degree in mechanical engineering and 3+ years of experience with mechanical and control systems. | — | 0 |
| Package Assembly Integration Engineer This role drives systems development, business processes, and tactical execution for EMIB package assembly and CH factories. It involves feasibility studies, FMEA, integrated process solutions, material/equipment selection, process characterization, new product qualification, technology transfers, and leveraging big data analysis to identify and solve process/tool issues. Collaboration with suppliers and development teams is key to meeting technology roadmaps. | — | 0 |
| Linux Development Engineer Develops and integrates software across the Linux stack, including drivers, OS, frameworks, and applications, with a focus on Bluetooth SW and tools. Requires experience in C/C++, embedded systems, Linux kernel, RTOS, and Linux device drivers. | — | 0 |
| Memory Validation Manager Seeking a Senior PC Memory Module and Storage Validation Engineer to lead validation and qualification for next-generation memory and storage solutions in PC and IoT platforms. Responsibilities include leading validation activities, debugging system-level failures, characterizing performance, developing automation, ensuring compliance with industry standards, and managing contractor engineers. | — | 0 |
| Mechanical Tooling Engineer Mechanical Tooling Engineer responsible for developing and enabling Intel's next-generation advanced packaging and test technologies. This role involves the definition, design, and deployment of tooling and hardware solutions for semiconductor packaging, including process integration, equipment solutions, and feasibility studies. Responsibilities include leading the design and development of manufacturing processes, optimizing operating equipment, and collaborating with suppliers. | — | 0 |
| Silicon Packaging Design Engineer This role is for a Silicon Packaging Design Engineer at Intel Foundry Services, focusing on the end-to-end development of advanced substrate designs. Responsibilities include physical layout, routing, substrate fit studies, defining design rules, and collaborating with cross-functional teams to optimize designs for performance, cost, and manufacturability. The role requires experience with package design tools and physical layout aspects of substrate design. | — | 0 |
| GPU Thermal Management Design Engineer Seeking a Thermal Management Design Engineer to architect, simulate, and validate thermal management and fan control features for Intel dGPU products. The role involves designing and optimizing thermal solutions and platform designs, influencing upstream teams, and collaborating with various engineering disciplines and partners to ensure product delivery to technical and schedule requirements. | — | 0 |
| EDA Design Flow Development Engineer Develop and maintain transistor-level electromigration (EM) and IR drop analysis flows for custom IPs, embedded memories, SRAMs, analog/mixed-signal interfaces, and high-performance custom macros across advanced semiconductor technologies. Focuses on CAD methodology, automation infrastructure, power integrity analysis flows, and silicon correlation for transistor-level reliability verification. | — | 0 |
| EDA Tools Hardware Engineer This role focuses on developing and maintaining transistor-level timing characterization flows for custom IPs and memories across advanced semiconductor technologies. The engineer will work with EDA vendors and design teams to enable scalable and silicon-accurate timing, power, and noise modeling flows, requiring expertise in SPICE-based characterization and Liberty model generation. | — | 0 |
| EDA Tools Hardware Engineer This role focuses on developing and maintaining full-chip physical implementation flows for hardware design tools, including floor planning, integration, placement, routing, and power grid analysis. It involves enabling scalable SoC assembly and defining methodologies for hierarchical design reuse. | — | 0 |
| Mask Manufacturing Technician This role is for a Mask Manufacturing Technician at Intel, responsible for operating and maintaining mask manufacturing modules, ensuring safety, quality, and output goals. It involves process improvement, troubleshooting, and training others in a high-volume manufacturing environment. | — | 0 |
| Mask Manufacturing Technician This role is for a Mask Manufacturing Technician at Intel, responsible for operating and maintaining mask manufacturing modules, ensuring safety, quality, and output goals. The technician will also be involved in process improvement, troubleshooting, and training. | — | 0 |
| Software Engineering Manager Lead a team of software engineers and architects developing and validating cutting-edge software solutions for Intel's product segments or technologies, driving success across the stack from firmware to applications and platforms. Foster collaboration, set goals, and enable professional growth to ensure high-quality deliverables in a productive, inclusive environment. | — | 0 |
| Manufacturing Training Technician This role focuses on designing, organizing, and delivering technical training for manufacturing and process engineering employees at Intel. It involves developing training materials, coordinating logistics, tracking training records, and evaluating training effectiveness. The goal is to equip the workforce with the necessary skills for manufacturing operations. | — | 0 |
| Power Delivery Design Engineer Designs and Validates Power delivery solutions for Reference/Validation boards, including low voltage DC-DC regulators and power management circuits for CPU/SOC based platforms. Involves schematics capture, PCB layout review, component selection, BOM release, and lab validation. | — | 0 |
| E-core CPU Layout Design Engineer This role is for an E-Core (Atom) CPU Layout Design Engineer responsible for the physical implementation of memory compilers and RF custom IP blocks for Intel Atom microprocessors. The engineer will work on transistor/device and cell level planning, layout, assembly, and routing, utilizing CAD tools for layout editing, verification, DFM, and quality. Responsibilities include bridging circuit engineering, design automation, and mask design, performing analysis for IR drop and reliability, and driving methodology refinement for memory compilers. The role requires strong programming skills in UNIX shell script, Tcl, and Perl. | — | 0 |
| Platform Integration Engineer Intel is seeking an experienced Platform Integration Engineer for the Intel Chassis Group. The role involves understanding SoC chassis requirements, designing and developing high-performance networks-on-chip using chassis foundation library components, and coordinating with the foundation IP development team. Requires 6+ years of experience in SOC and/or IP design, with preferred experience in microarchitecture, design IP systems, and fabric design/integration. | — | 0 |
| Manufacturing Failure Analysis Engineer Manufacturing Failure Analysis Engineer at Intel, focusing on identifying and resolving failures in semiconductor manufacturing processes, products, and technologies for advanced packaging. Responsibilities include conducting failure analysis, developing methodologies, investigating failure mechanisms, recommending corrective actions, and collaborating with cross-functional teams. Requires experience in failure analysis techniques and analytical tools like SEM, FTIR, Xray. | — | 0 |
| Senior Mixed Signal Validation and Debug Engineer Senior Mixed Signal Validation and Debug Engineer responsible for developing leadership IPs for Server, Client, Networking SOCs and Intel Foundry Customers. The role involves pre-silicon to post-silicon IP characterization, test plan generation using AI driven tools and Python scripting, SOC board design reviews, Signal and Power Integrity simulations, and hands-on debug of IP related issues. Requires BS/MS/PhD in EE/CE and 6+ years of experience in post-silicon validation and debug of serial or parallel IOs, with proficiency in lab hardware and software. | — | 0 |
| PCB Layout Engineer PCB Layout Engineer responsible for the design, placement, and routing of CPU/FPGA based hardware boards, ensuring adherence to design guidelines and product specifications. Involves collaboration with mechanical teams and understanding architecture requirements. | — | 0 |