Intel
- HQ
- Santa Clara, US
- Founded
- 1968
- Size
- 120,000+
- Website
- intel.com
Currently tracking 56 active AI roles, down 27% versus the prior 4 weeks. Primary focus: Serve · Engineering. Salary range $122k–$414k (avg $253k).
Intel currently has 84 active job listings related to artificial intelligence. The majority of these roles, 51%, are focused on serving infrastructure, with agents representing another significant portion at 24%. Engineering is the most frequent function for these positions. The company is actively hiring in the United States, China, and Mexico. Frequent technical tags include model serving, inference infrastructure, and agent orchestration. In the last 30 days, Intel has added 73 new AI roles, representing a 52% increase compared to the previous 30-day period.
Intel currently has 59 active AI-related roles in our index. The most common open titles are: AI Software Engineering Intern (3), AI Software Engineer Intern (2), GenAI Software Solutions Engineer (2), Graduate Talent (GenAI Software Solutions Engineer) (2), AI Algorithm Engineer. Most positions are in Engineering and Research.
Intel's active AI hiring is concentrated in: serving infrastructure (49%), agents (29%), application (8%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
Intel is hiring AI talent in: United States (28 roles), China (7 roles), Mexico (6 roles), Malaysia (6 roles).
Job postings at Intel most frequently reference: model serving, inference infra, agent orchestration, rag, tool use.
In the past 30 days, Intel has posted 28 new AI-related roles. That is a -63% change versus the prior 30 days (75 → 28).
| Title | Stage | AI score |
|---|---|---|
| Senior SoC Network Subsystem Architect This role is for a Senior SoC Network Subsystem Architect at Intel, focusing on defining and leading the architecture of high-performance network subsystems for next-generation IPU/DPU platforms. The role involves designing scalable, programmable networking pipelines for hyperscale and cloud data centers, with responsibilities including packet processing, QoS, scheduling, and observability features. It requires cross-functional leadership and collaboration with hardware, software, and systems teams. While the role mentions supporting AI workloads and AI/HPC scale-out networking, the core function is in network silicon architecture, not AI model development or deployment. | — | 0 |
| Senior Yield Development Engineer - Intel Foundry Senior Yield Development Engineer at Intel Foundry focused on optimizing semiconductor process technology and driving yield improvements across next-generation technology nodes. Responsibilities include identifying and resolving yield-limiting factors, developing innovative solutions, conducting advanced statistical analysis, creating data visualizations, building process development roadmaps, and collaborating with cross-functional teams (design, test, process development). Requires a Master's degree in a STEM field with 3+ years of experience in yield development or process technology, and 2+ years of experience with external customer advanced node semiconductor devices and process flow concepts. Experience with yield projection using EOL signals and in-line parameters is required. Preferred qualifications include a Ph.D., experience with data analysis systems, advanced semiconductor equipment, process development, defect density analysis, data analytics methodologies, and project management. |
| — |
| 0 |
| Senior SoC Chiplet Architect Senior SoC Chiplet Architect to define and lead the architecture strategy for multi-generation, chiplet-based SoC platforms targeting next-generation data center workloads, including AI workloads. Responsibilities include chiplet partitioning, die-to-die interconnect architecture, and system-level tradeoff analysis across performance, power, area, cost/yield, and software complexity. | — | 0 |
| GPU Software Development Engineer Develops and validates software for Intel GPUs, including firmware, drivers, and APIs, optimizing performance for graphics and compute workloads, with applications in AI and data centers. | — | 0 |
| IP Logic Design Engineer Intel is seeking an IP Logic Design Engineer to develop logic designs for high-performance IPs integrated into SoC products for Client, Graphics, and Data Center markets. Responsibilities include RTL implementation, architecture specification, optimization, verification support, and post-silicon validation. | — | 0 |
| Manufacturing Technical Supervisor (Operations) This role manages a team of technicians overseeing manufacturing operations, equipment maintenance, and repair. It focuses on safety, quality, scheduling, and process streamlining to meet production goals. The role requires technical knowledge of manufacturing equipment and problem-solving skills, with a preference for experience in semiconductor manufacturing and data science tools. | — | 0 |
| Manufacturing Technical Supervisor (Operations) This role manages a team of technicians overseeing manufacturing operations, equipment maintenance, and repair. It focuses on safety, quality, scheduling, and process streamlining to meet production goals. The role requires technical knowledge of manufacturing equipment and problem-solving skills, with a preference for experience in semiconductor manufacturing and data science tools. | — | 0 |
| Senior SoC Compute/Memory Subsystem Architect Intel is seeking a Senior SoC Compute/Memory Subsystem Architect to define and drive the architecture of compute complexes and high-performance memory subsystems for next-generation IPU/DPU platforms. This role involves end-to-end architecture of CPU clusters, cache hierarchies, coherency models, and memory subsystems, optimizing for performance, scalability, power efficiency, and programmability in hyperscale environments. Responsibilities include defining compute and memory strategies, IO memory and virtualization architecture, system-level integration, and developing a multi-generation architecture roadmap, collaborating with cross-functional teams. | — | 0 |
| Physical Design Methodology Engineer This role focuses on physical design methodology for semiconductor manufacturing, specifically in design-technology co-optimization (DTCO) and system-design co-optimization (STCO). The engineer will create methodologies, models, and flows for advanced design rules, characterize these models through silicon validation, and optimize silicon designs for power, performance, and area (PPA). The role involves working with EDA tools and ensuring IP and SoC designs meet manufacturing process technology requirements. | — | 0 |
| PERC ESD EDA Engineer Develops PERC ESD rule decks for latest Intel technologies, enabling design teams to get to market faster. Collaborates with internal and external teams, defines QA requirements, and leads innovation initiatives for ESD/LU verification automation. | — | 0 |
| Medium Voltage Distribution Electrician This role involves assembling, evaluating, testing, and maintaining electrical or electronic wiring, equipment, appliances, and apparatus. The electrician will troubleshoot and repair malfunctioning equipment, advise on management of equipment, review wiring blueprints, conduct maintenance repairs, and rectify system failures. They will operate medium voltage electrical systems, inspect electrical systems, interpret technical drawings, run tests on generators and backup systems, and ensure adherence to safety and performance standards. The position also involves installing and preserving the functionality of wires, plugs, panel boards, switchgear, and switchboards, responding to fault requests, providing reliability suggestions, and commissioning new electrical facilities equipment. | — | 0 |
| Medium Voltage Distribution Electrician The role of a Medium Voltage Distribution Electrician at Intel involves assembling, evaluating, testing, and maintaining electrical wiring, equipment, and apparatus. Responsibilities include troubleshooting and repairing malfunctioning equipment, advising on equipment management, reviewing blueprints, conducting maintenance, and rectifying system failures. The electrician will operate medium voltage electrical systems, inspect electrical systems for faults, interpret technical drawings, run tests on generators, and ensure adherence to safety standards. This is a hands-on role requiring physical work in potentially challenging conditions and adherence to specific safety protocols. | — | 0 |
| CAD/EDA Tools Automation Engineer This role focuses on designing, developing, testing, and debugging software tools and flows for hardware design automation, process design, and manufacturing. It involves capturing requirements, writing functional and test code, automating builds and deployments, and performing various levels of testing. The role requires a Master's or PhD in a technical engineering discipline with experience in programming languages like Python, Tcl, or C++, and Linux environments. | — | 0 |
| Post-silicon Validation and Debug Engineer This role is for a Post-Silicon Validation and Debug Engineer focused on CPU/SOC products for consumer devices. The responsibilities include developing and executing validation plans, designing and debugging tests, collaborating with cross-functional teams, analyzing issues, and driving automation. The role requires experience in post-silicon validation, pre-silicon verification, or design, particularly in CPU/SOC domains, and familiarity with silicon validation tools and scripting languages. | — | 0 |
| Senior Staff Analog Circuit Design Engineer - SerDes Senior Staff Analog Circuit Design Engineer focused on validating SerDes technologies, ensuring reliability, functionality, and performance of mixed signal designs. Responsibilities include developing validation plans, methodologies, root cause analysis, and maintaining post-silicon validation workflows. | — | 0 |
| Operations Research Engineer Designs, develops, and applies advanced engineering and mathematical models, including simulation and optimization frameworks, to solve complex Intel manufacturing and supply chain challenges. Focuses on fabrication and assembly/test environments, building and deploying decision algorithms, heuristics, optimization models, and simulation tools. | — | 0 |
| Mask Manufacturing Technician Manufacturing technician responsible for operating and maintaining production equipment, ensuring product quality, and supporting process improvements in a semiconductor mask manufacturing environment. | — | 0 |
| Mask Manufacturing Technician This role involves performing manufacturing and assembly tasks in a production process, operating equipment, collecting and evaluating operating data for optimization, and conducting quality control evaluations on raw materials and final products. It also supports developing and testing new products and processes, and maintaining production logs. The role requires a High School Diploma or GED with relevant experience or an Associate's degree in STEM. | — | 0 |
| Senior Analog Design Engineer This role is for a Senior Analog Design Engineer at Intel, focusing on designing, developing, and optimizing analog and mixed-signal integrated circuits for high-speed serial IO and die-to-die interfaces. Responsibilities include circuit design, simulation, layout, technical leadership, and silicon validation. The role requires expertise in analog circuit design, collaboration with cross-functional teams, and experience with industry-standard tools and advanced process technologies. | — | 0 |
| Analog IP Design Execution Manager Technical execution manager for Hard IP and Test Chip Development team, responsible for delivering industry-defining analog and mixed signal IP for Intel's customers. This role involves leading technical teams through the entire IP lifecycle, from planning and pre-silicon execution to post-silicon validation and launch, ensuring timely delivery with committed content and quality. Requires strong problem-solving, communication, and program management skills, with familiarity in AI/ML-driven design productivity techniques. | — | 0 |
| Foundry Site Quality Program Manager The Quality Program Manager for the Chandler Assembly site will be responsible for measuring and reporting on site quality, generating and implementing factory quality improvement programs, supporting quality meetings and improvement teams, and acting as a site auditor for ISO9K/IATF Cert and internal audit programs. This role focuses on leading initiatives aligned with Intel's Foundry Quality Pyramid, identifying risks, preventing excursions, and implementing fixes across the factory, while also supporting QMS elements for new technology certification and continuous improvement of quality metrics and systems. | — | 0 |
| Senior Supply Chain Business Analyst This role is for a Senior Supply Chain Business Analyst at Intel, focusing on managing technology projects and programs within the supply chain. The responsibilities include developing project plans, managing implementation processes, ensuring alignment with business objectives, monitoring schedules, assessing dependencies, and communicating project status. The role requires a Bachelor's degree and 6+ years of experience in technology project/program management, with proficiency in Agile and Waterfall methodologies. | — | 0 |
| Strategic/Development Industrial Engineer This role focuses on developing and executing long-term capacity and capital strategies within a foundry organization, optimizing factory resources and capital investment through advanced data analysis and modeling. It involves collaborating with cross-functional teams to drive continuous improvement and influence business strategies. | — | 0 |
| Senior SoC Architect – Unified Intel Chassis (UIC) IP and Platform Architecture Senior SoC Architect role focused on defining and driving architecture specifications for Unified Intel Chassis (UIC) IP components and subsystems. Responsibilities include power optimization, scalability, platform performance analysis, and collaboration with cross-functional teams. The role requires expertise in SoC IP architecture, AMBA protocols, and architecture specification writing. Familiarity with AI tools for developing machine-readable specifications is mentioned as a plus. | — | 0 |
| Post Silicon Validation Student Student/Intern position in Intel's Silicon and Platform Engineering Group (SPE) in Haifa, Israel. The role involves learning and applying knowledge, building skills, and exploring future career opportunities through hands-on experience and projects. Requires a Bachelor's degree in Electrical/Computer Engineering, strong analytical and problem-solving skills, and the ability to work in unstructured environments and drive new model path finding. | — | 0 |
| Tech Contract Employee This role involves performing product manufacturing and assembly tasks in a factory setting, operating and optimizing equipment, ensuring quality standards, and maintaining production logs. It requires basic computer literacy, problem-solving skills, and the ability to work in shifts. The role is for a Tech Contract Employee at Intel's manufacturing facility in Penang, Malaysia. | — | 0 |
| Silicon Design Verification Engineer This role focuses on the functional logic verification of integrated SoCs, ensuring they meet specifications. Responsibilities include developing verification plans, test benches, and environments, executing these plans using emulation and simulation, debugging issues, and collaborating with design and architecture teams. The role also involves leveraging post-silicon learnings to improve future products. | — | 0 |
| Connectivity Systems Validation Engineer This role focuses on developing, executing, and automating Bluetooth and Wi-Fi connectivity tests for hardware and software products. It involves creating validation environments, identifying and reporting issues, developing test plans, and collaborating with cross-functional teams. The role requires experience with test automation (Python) and network protocol analyzers, with a mention of integrating Gen AI Agents into validation tasks. | — | 0 |
| Mfg Systems Software Development Engineer Software Development Engineer role focused on supporting, developing, and optimizing technical solutions, performing technical analysis, testing, and troubleshooting, and contributing to the design, implementation, and evaluation of innovative technological solutions within Intel's manufacturing systems. The role involves software application development and integration, with potential for performance tuning and debugging. | — | 0 |
| SoC Compute/Memory Subsystem Architect Intel is seeking a Senior SoC Compute & Memory Architect to define and drive the architecture of compute complexes and high-performance memory subsystems for next-generation IPU/DPU platforms. This role involves end-to-end architecture of CPU clusters, cache hierarchies, coherency models, and memory subsystems, optimizing for performance, scalability, power efficiency, and programmability in hyperscale environments. Responsibilities include cache hierarchy and coherency, memory subsystem, IO memory and virtualization, system-level integration, power efficiency, and defining a multi-generation architecture roadmap. The role requires collaboration with various teams and strong leadership skills. | — | 0 |
| Senior SoC Architect Senior SoC Architect role at Intel focusing on defining and driving architecture specifications for Unified Intel Chassis (UIC) IP components and subsystems. Responsibilities include platform-level performance analysis, building performance environments, and ensuring architecture is power-optimized, scalable, and practical for implementation. Requires experience in SoC IP architecture, writing specifications, and power optimization techniques. | — | 0 |
| Senior Thin Films Engineer Senior Engineer role focused on process innovation and optimization for thin film deposition in advanced semiconductor manufacturing, bridging technology development and high-volume production for Intel's foundry customers. | — | 0 |
| Senior Design Verification Engineer Senior Design Verification Engineer for Intel's Silicon Chassis team, responsible for end-to-end verification of chassis and interconnect IP blocks. Requires expertise in DV methodologies, protocol verification, memory subsystems, and collaboration with cross-functional teams. The role involves driving quality, testbench architecture, and coverage closure, with an emphasis on adopting emerging methodologies like ML-driven verification flows and AI-assisted development tools. | — | 0 |
| Semiconductor Facilities Technician This role is for a Facilities Chemical/Gas Technician at Intel's semiconductor manufacturing facility in Rio Rancho, New Mexico. The technician will provide operational support, perform preventive maintenance, and troubleshoot Vacuum Pump and Abatement Systems. Responsibilities include managing code compliance, assisting in developing procedures, and completing certification packages. The role requires adaptability, strong judgment, leadership, collaboration, continuous learning, safety consciousness, problem-solving, and communication skills. Candidates must be willing to work a specific night shift schedule and handle physically demanding tasks including wearing breathing protection and chemical suits. Minimum qualifications include a BS in STEM or an associate degree in STEM with 2+ years of relevant experience, or a High School Diploma/GED with 2.5+ years of related hands-on manufacturing or military experience. Preferred qualifications include 3+ years of experience in preventive maintenance programs and equipment repair processes. | — | 0 |
| Senior Customer Technical Enablement and Debug Engineer This role is for a Senior Customer Technical Enablement and Debug Engineer at Intel, focusing on system-level debug (HW/FW/SW) for networking IPU deployments. The engineer will be the primary technical point of contact for customers, diagnosing and resolving complex issues in real-world environments, and collaborating with internal teams to drive resolutions. The role also involves customer enablement and improving debug methodologies. | — | 0 |
| Senior EDA Tools Software Engineer Senior EDA Tools Software Engineer to define and lead development of a chassis automation tool. This tool will translate user requirements into chassis parameters, topology, and generate RTL, register definitions, and verification collateral. The role involves working with architecture, RTL design, verification, and SOC integration teams, mentoring junior engineers, and enabling PPA optimization loops. AI-assisted workflows are mentioned as part of daily development. | — | 0 |
| Senior Analog IP Integration, Power, and SI Engineer Senior Analog IP Integration, Power, and SI Engineer at Intel, focusing on designing and optimizing analog and mixed-signal IP for various Intel customers. Responsibilities include circuit design, layout, simulation, technical leadership, and collaboration with cross-functional teams. Requires expertise in analog circuit design, high-speed IO, and experience with industry-standard tools and process technologies. | — | 0 |
| Network Platform Architect Intel is seeking a Network Platform Architect to define, build, and secure the company's network strategy. This role involves driving architectural reviews, solving complex network challenges, and delivering secure and efficient infrastructure. Responsibilities include defining platform integration and adapter architecture end-to-end for networking products, collaborating with partners and customers on connectivity, manageability, cooling, and form factor. The role will also define next-generation products, focusing on the intersection of SoC architecture, board design, platform firmware/software, and OEM/ODM integration. Key areas include IPU/DPU/NIC Card/Adapter Architecture Ownership, Platform Manageability Interconnect and Serviceability Architecture, and Platform Thermal, Power, and Reliability Requirements. The architect will serve as the platform architecture voice, lead technical alignment across cross-functional teams, and partner with leadership to define platform milestones. | — | 0 |
| Analog Design Engineering Manager Leads technical teams to deliver industry-defining analog and mixed-signal IP for Intel's Client, Datacenter, AI and Foundry customers. Manages analog design engineers, guides silicon design, and oversees post-silicon validation. | — | 0 |
| Device Engineer Device Engineer role focused on advanced FinFETs technology, working on yield ramp-up, process and device optimization in a high-volume manufacturing Fab. Responsibilities include driving product roadmaps, executing yield roadmaps, developing new device technology, root cause analysis of yield/performance issues, NPI, and modeling device performance. | — | 0 |
| Intel Foundry Advanced Device Development Engineer Develops and optimizes semiconductor manufacturing processes for advanced transistor technology, involving experiment design, data analysis, and collaboration with various engineering teams. Requires expertise in semiconductor materials, fabrication, and device physics. | — | 0 |
| Graduate Talent (RF Test Product Development Engineer) This role is for a Graduate Talent (RF Test Product Development Engineer) at Intel in Malaysia. The responsibilities include ensuring the testability and manufacturability of integrated circuits, developing test methods and hardware solutions, and analyzing component specifications and customer returns to optimize production quality and cost. Qualifications include a Master/Bachelor Degree in Electronics, Electrical, Microelectronics or Computer Engineering, programming skills in C++ or Java, and understanding of RF technology, WiFi, BT, RF test methods, RF instruments, and Automated Test Equipment (ATE). High volume manufacturing experience with RF testing is also required. | — | 0 |
| APTD Manufacturing Technician - Night shift Manufacturing Technician for Intel's Advanced Packaging Technology Development team, focusing on substrate and wafer assembly. Responsibilities include operating and maintaining production equipment, performing preventive maintenance, troubleshooting issues, supporting process improvements, and ensuring quality standards. The role involves data collection, process optimization, and training. | — | 0 |
| Tool Install Project Manager Project Manager for Tool Installation in semiconductor manufacturing factories, managing teams, suppliers, schedules, and budgets to ensure safe and quality delivery of projects. | — | 0 |
| Senior CPU RTL Design Engineer Senior CPU RTL Design Engineer responsible for logic design, RTL coding, and simulation for CPU IP blocks. The role involves defining architecture and microarchitecture features, optimizing logic for power, performance, and area, and providing technical leadership to the design team. Experience with Timing Closure, Power Convergence, and OOO execution is required. | — | 0 |
| SoC Integration Engineer Seeking an experienced SoC Integration Engineer to join the Unified Intel Chassis (UIC) team. This role involves working on high-performance Network-on-Chip (NoC) platform solutions, integrating IP blocks into SoC platforms, and collaborating with architecture, IP, and physical design teams to meet power, performance, and area (PPA) targets. The position requires a Bachelor's degree in Electrical Engineering or related field with 6+ years of experience or a Master's degree with 4+ years of experience, specifically in SoC and/or IP design. | — | 0 |
| Senior SoC Power Management Architect This role focuses on defining and developing cutting-edge System-on-Chip (SoC) architectures with emphasis on power management, performance optimization, and energy efficiency for next-generation computing platforms. The Senior SoC Power Management Architect will collaborate across architecture, design, validation, and product teams to deliver scalable solutions from concept through high-volume manufacturing (HVM). Responsibilities include defining and developing SoC power management architecture, maintaining a system-level perspective, evaluating design trade-offs, driving power integration strategies, partnering with hardware and software teams, supporting the full product lifecycle, and analyzing post-silicon power/performance data. | — | 0 |
| Ocotillo Technology Fabrication Process Integration and Yield Engineer Process Integration and Yield Engineer at Intel responsible for analyzing data, identifying root causes of defects and yield issues, and leading continuous improvement projects in semiconductor fabrication. Requires strong statistical analysis and problem-solving skills. | — | 0 |
| OTF Failure Analysis Technician - Night Shift This role is for an OTF Failure Analysis Technician in a semiconductor lab, responsible for operating lab instruments and handling silicon wafers for advanced technology nodes. The job involves sample preparation, operating tools like FIB/PFIB/SEM for cross-sectioning and material analysis, and working from schematics. It requires experience in semiconductor manufacturing or failure analysis tools and emphasizes attention to detail and adaptability in a fast-paced environment. | — | 0 |
| Manufacturing Technician Manufacturing Technician role at Intel Ireland focused on supporting wafer manufacturing operations in a high-volume semiconductor environment. Responsibilities include equipment maintenance, troubleshooting, operational support, and ensuring safety, quality, and output targets are met. Requires a technical qualification and significant experience in manufacturing and maintenance within a regulated environment. | — | 0 |