Intel currently has 84 active job listings related to artificial intelligence. The majority of these roles, 51%, are focused on serving infrastructure, with agents representing another significant portion at 24%. Engineering is the most frequent function for these positions. The company is actively hiring in the United States, China, and Mexico. Frequent technical tags include model serving, inference infrastructure, and agent orchestration. In the last 30 days, Intel has added 73 new AI roles, representing a 52% increase compared to the previous 30-day period.
Currently tracking 56 active AI roles, down 27% versus the prior 4 weeks. Primary focus: Serve · Engineering. Salary range $122k–$414k (avg $253k).
Intel currently has 59 active AI-related roles in our index. The most common open titles are: AI Software Engineering Intern (3), AI Software Engineer Intern (2), GenAI Software Solutions Engineer (2), Graduate Talent (GenAI Software Solutions Engineer) (2), AI Algorithm Engineer. Most positions are in Engineering and Research.
Intel's active AI hiring is concentrated in: serving infrastructure (49%), agents (29%), application (8%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
Intel is hiring AI talent in: United States (28 roles), China (7 roles), Mexico (6 roles), Malaysia (6 roles).
Job postings at Intel most frequently reference: model serving, inference infra, agent orchestration, rag, tool use.
In the past 30 days, Intel has posted 28 new AI-related roles. That is a -63% change versus the prior 30 days (75 → 28).
| Title | Stage | AI score |
|---|---|---|
| Soc Subsystem Architect - AI platform Development Intel's AI SoC organization is seeking an experienced SoC Subsystem Architect to lead the evaluation of architectural trade-offs, define and document micro-architecture for complex SoC IP blocks, and drive silicon bring-up and post-silicon validation for AI hardware. The role involves RTL design, integration, verification, timing constraints, and mentoring junior engineers. | — | 0 |
| Facilities Engineer Instrumentation and Controls - Intel Contract Employee Facilities Engineer focused on instrumentation and controls for industrial automation platforms (GE Cimplicity, Rockwell Automation Control Logix PLC) in a manufacturing/facility setting. Responsibilities include system design, maintenance, troubleshooting, project management, and ensuring operational efficiency and compliance. | — | 0 |
| Senior EDA Tools Hardware Engineer This role focuses on designing, implementing, and enabling next-generation hardware design tools, flows, and methodologies for advanced technology nodes at Intel. The engineer will analyze and optimize methodologies for power, performance, area, and efficiency, build platforms and scripts for design automation, and collaborate with EDA vendors to test and adopt new tools. The role requires experience in EDA tools, physical design, digital design, and verification. |
| — |
| 0 |
| Manufacturing Technician Operate and monitor production equipment, conduct maintenance, perform wafer production functions, optimize machinery settings, collaborate to meet targets, maintain logs, drive quality and cost improvements, conduct quality control, and support equipment installation and training. | — | 0 |
| Physical Design Engineer This role focuses on the physical design of custom IP and SoC for high-performance computing applications, covering the full RTL-to-GDS flow. Responsibilities include synthesis, place-and-route, timing analysis, verification, and optimization using EDA tools, with a strong emphasis on scripting for automation and collaboration with cross-functional teams. | — | 0 |
| IP Design verification Engineer This role focuses on IP Design Verification, ensuring the functional correctness and reliability of intellectual property designs. Responsibilities include developing verification plans, designing test benches, simulating designs, debugging pre-silicon issues, and collaborating with architects and RTL developers. The role requires proficiency in SystemVerilog, experience with complex protocols, and scripting languages like Python or Perl. | — | 0 |
| Graduate Talent (Product Enablement and Solutions) Develops CAD software solutions for Intel's RTL Design and Validation teams, focusing on HW validation needs like RTL Coverage and UVM support. Responsibilities include developing flows, offering technical training, and providing hands-on assistance to validation engineers in areas such as Test-Bench development, regression management, coverage, failure analysis, and trace analysis. | — | 0 |
| Ocotillo Technology Fabrication Shift Group Leader This role is for an Ocotillo Technology Fabrication Shift Group Leader at Intel, responsible for managing technicians in a manufacturing environment. The role involves ensuring performance, development, and employee relations, creating roadmaps to meet goals in safety, quality, availability, velocity, affordability, and training. Responsibilities include supervising product teams, assessing personnel and material levels, assigning tasks, monitoring workflow, establishing operating policies, and ensuring overall safety. The ideal candidate will have strong leadership, communication, problem-solving skills, and a proven track record of delivering results through people in a high-performing team culture. | — | 0 |
| Electrical Validation Engineering Intern- Client IO Electrical Validation Engineering Intern for Client IO team at Intel, focusing on validating high-speed and low-speed silicon interfaces. Responsibilities include hardware bring-up, lab testing, data analysis, and supporting automation framework development. Requires final-year Bachelor's or Master's in Electrical Engineering with Python/C++ experience. | — | 0 |
| Silicon Packaging Design Engineer Designs and implements physical layout and routing of silicon interposers and embedded bridges, collaborating with silicon, technology development, and hardware teams to optimize system-level design. Utilizes EDA tools for package layouts and analyzes design data to resolve checks for manufacturability. | — | 0 |
| Ocotillo Technology Fabrication Experienced Module Engineer Experienced Module Engineer for Ocotillo Technology Fabrication (OTF) at Intel in Phoenix, Arizona. This role focuses on defining roadmaps, establishing process flows, selecting materials and equipment, conducting experiments, driving process improvements, and transferring processes to high-volume manufacturing. Requires a strong background in semiconductor engineering and experience supporting manufacturing ramps and technology transfers. | — | 0 |
| IP RTL Design Engineer RTL Design Engineer for Intel Unified Chassis, focusing on protocol bridges and IP components. Responsibilities include design, implementation, verification, and collaboration with architects and senior engineers. Requires expertise in RTL coding, digital design principles, and hardware description languages like Verilog or VHDL. | — | 0 |
| CPU Senior Circuit Design Engineer Senior Circuit Design Engineer for next-generation CPU programs, focusing on designing high-performance, low-power custom circuits meeting PPA targets. Responsibilities include circuit simulation, verification, optimization, and applying advanced CMOS technology. | — | 0 |
| Physical Verification Engineer Intel Foundry Services is seeking a Senior Physical Verification Application Engineer to provide technical support to customers on layout verification and parasitic extraction for advanced CMOS processes. The role involves resolving complex physical design challenges, developing technical content, leading verification methodology improvements, and engaging with customers. Requires experience with advanced CMOS processes, EDA tools for layout verification and parasitic extraction, and scripting languages. US Citizenship and ability to obtain security clearance are required. | — | 0 |
| Senior Design Engineer – AI SoC Development Senior Design Engineer focused on developing logic design, RTL coding, and simulation for AI SoC development, integrating IP blocks, defining architecture, and optimizing for power, performance, and timing. The role involves collaboration with verification teams, driving silicon bring-up, and mentoring junior engineers. | — | 0 |
| Lead Senior Design Engineer – AI SoC Development Lead Senior Design Engineer for Intel's AI SoC organization, focusing on the development of logic design, RTL coding, simulation, and integration of IP blocks for AI hardware. The role involves defining architecture and microarchitecture, optimizing for power, performance, and timing, and driving silicon bring-up and validation. It requires strong engineering skills in ASIC/SoC development and leadership qualities. | — | 0 |
| IT Network Operation Engineer IT Network Operation Engineer responsible for sustaining and operating mission-critical complex manufacturing network infrastructure supporting Intel Foundry environments. Focuses on operational execution, network stability, incident response, and problem analysis for Cisco networks (including ACI) in a 24x7 production environment. | — | 0 |
| Firewall Network Security Engineer Network Security Engineer role focused on designing, architecting, and building secure classified network products for USG operations, involving firewall configuration, network hardening, and security assessments. | — | 0 |
| NMSi / WPM Module Equipment Technician Contract This role is for a Module Equipment Technician supporting semiconductor manufacturing operations. Responsibilities include maintaining, troubleshooting, and improving manufacturing equipment performance in a high-tech, cleanroom environment. The role requires performing electrical and mechanical troubleshooting, disassembling, adjusting, repairing, installing, and assembling equipment, executing setup, calibration, and preventive maintenance, and monitoring equipment performance data. It also involves documenting system failures, partnering with engineering teams for experiments and data collection, and supporting engineering troubleshooting efforts. Collaboration with module engineering and construction teams during factory ramps is also part of the job. The role requires strict adherence to safety, quality, and procedural standards. | — | 0 |
| Senior CPU Design Verification Engineer Senior CPU Design Verification Engineer at Intel, responsible for pre-silicon functional verification of complex CPU and SoC logic using SystemVerilog and UVM, ensuring architectural correctness and functional robustness before first silicon. | — | 0 |
| Module Development Engineer Module Development Engineer at Intel, focusing on dry etch process innovations for high volume semiconductor manufacturing. Requires expertise in plasma physics, process integration, advanced data analytics, and DOE. The role involves technical ownership, defining long-term technical direction, and influencing cross-functional teams and suppliers to enable new device architectures and future technology roadmaps. Experience in advanced logic or foundry technologies, and a strong publication/patent record are preferred. | — | 0 |
| Thermal Compression Bonding Development Engineer Develop and optimize assembly processes and equipment for advanced semiconductor packaging technologies, focusing on Thermal Compression Bonding. Requires expertise in statistical methods, DOE, and data analysis to improve quality, yield, and efficiency. Collaborates with cross-functional teams and documents technical advancements. | — | 0 |
| CUF TD Module Engineer Develops and optimizes assembly processes and equipment for semiconductor packaging, focusing on manufacturing efficiency, quality, reliability, and cost. This role involves applying experimental design and statistical methods to improve processes, ensuring manufacturability, and meeting customer reliability needs. The role also involves establishing material specifications and collaborating with suppliers. The business group context mentions enabling Intel's roadmap of future assembly packaging platform technologies for the AI era, but the core responsibilities are in traditional manufacturing engineering. | — | 0 |
| DFT Design Engineer Develops logic design, RTL coding, and simulation for mixed signal and/or high-speed IPs for integration into full chip designs. Participates in architecture and microarchitecture definition, applies strategies for mixed signal designs, and reviews verification plans to ensure design correctness. Supports SoC customers for IP block integration. | — | 0 |
| GPU Software Development Engineer This role focuses on the validation and debug of graphics IP offerings, ensuring the robustness and quality of graphics driver/application features. Responsibilities include integrating new graphics features, triaging and resolving failures, and developing debug tools to improve efficiency. The role also involves enabling new features for AI domains to enhance performance on graphics products. | — | 0 |
| EDA Tools Hardware Engineer This role is for an EDA Tools Hardware Engineer at Intel, focusing on developing and supporting methodology and flow solutions for leading-edge technology nodes in the Design Implementation (RTL to GDSII) and Advanced Technologies group. Responsibilities include driving R2G enablement, developing TechLayer tool and flow settings, and advancing Physical Design tools, flows, and methods. The role requires interaction with EDA providers and resolving designer tool/methodology issues. | — | 0 |
| SoC Design Engineer This role is for a SoC Logic Design Engineer responsible for developing RTL code, integrating logic blocks, optimizing designs for power, performance, area, and timing, and ensuring design integrity for physical implementation. It requires experience in microarchitecture development, RTL coding, logic design, and SoC integration. | — | 0 |
| Yield and Process Control Automation Engineer This role focuses on integrating factory systems including equipment control, production activity control, MES, yield management, and SPC systems to optimize throughput, improve product quality, and enhance operational efficiency in semiconductor manufacturing. The engineer will architect, develop, and deploy automation solutions, design real-time communication interfaces using SEMI standards, and lead root-cause analysis and system-level debugging. | — | 0 |
| Senior Testchip SoC Physical Design Engineer (Integration & Methodology) This role focuses on physical design and integration methodologies for testchip vehicles in advanced semiconductor process nodes, aiming to validate new technologies and ensure manufacturing readiness. It involves developing layout design, defining critical design features with process integration teams, establishing hierarchical layout specifications, and driving physical design convergence. | — | 0 |
| Senior Software Engineer Senior Software Engineer/Architect to design, build, and support internal web applications for technical documentation, publishing, and review workflows. Requires strong full stack engineering, architectural experience, and end-to-end ownership in an enterprise environment. Responsibilities include system architecture, coding standards, stakeholder partnership, and integrating tools. Experience with ML frameworks, distributed systems, and full-stack frameworks is required. | — | 0 |
| Module Engineer Module Engineer at Intel in Malaysia, responsible for owning and optimizing critical high-volume manufacturing equipment and processes in semiconductor fabrication. The role involves ensuring precision, defect control, driving production efficiencies, recommending modifications, executing maintenance, and transferring technology to global manufacturing sites. Focus is on meeting safety, quality, and cost goals for integrated circuit mass production. | — | 0 |
| SoC RTL Design Engineer This role is for an SoC Logic Design Engineer responsible for developing logic design, RTL coding, and simulation for SoC designs, integrating IP blocks, and ensuring power, performance, area, and timing goals are met. The engineer will also perform quality checks, optimize logic, and collaborate with customers. | — | 0 |
| Silicon Firmware Development Engineer Develop and maintain silicon firmware (UEFI BIOS Reference code) that interfaces directly with hardware, abstracting low-level functionality for higher-level software. Responsibilities include design, implementation, code reviews, testing, validation, and debugging, with a focus on secure coding practices. Requires proficiency in C, computer architecture, and problem-solving. | — | 0 |
| Atom CPU Layout Design Engineer Job posting for an Atom CPU Layout Design Engineer at Intel in Guadalajara, Mexico. Responsibilities include physical implementation of memory compilers, custom IP blocks, and layout partitions for future-generation Intel Atom microprocessors. Requires a Bachelor's degree in a related field, 6+ months of layout design experience, and advanced English. Preferred qualifications include a Master's degree, VLSI/CMOS experience, and Unix/Linux knowledge. | — | 0 |
| Atom CPU Layout Design Engineer Job posting for an Atom CPU Layout Design Engineer at Intel in Guadalajara, Mexico. Responsibilities include physical implementation of memory compilers, custom IP blocks, and layout partitions for future-generation Intel Atom microprocessors. Requires a Bachelor's degree in a related field, 6+ months of layout design experience, and advanced English. Preferred qualifications include a Master's degree, VLSI/CMOS experience, and Unix/Linux knowledge. | — | 0 |
| Senior Photonics Design Engineer, Actives Design Senior Photonics Design Engineer specializing in active components and high-speed design for Intel's silicon photonics platform, focusing on developing next-generation optical communication solutions for data centers and AI datacenters. | — | 0 |
| Manufacturing Operations Manager (Contract) Manufacturing Operations Manager at Intel in Malaysia, responsible for leading a team of technicians, overseeing operations, equipment maintenance, safety, quality, and scheduling in manufacturing facilities. The role involves establishing tactical plans, ensuring production schedules are met, developing long-term strategies for manufacturing capabilities, and managing employee staffing and training. | — | 0 |
| Electrical Validation Engineering Manager Electrical Validation Engineering Manager leading a team responsible for delivering high speed IO silicon (PCIe, UCIe, GPIO, SERDES) through electrical validation, signal integrity, and compliance testing from silicon bring up to mass production. The role involves people leadership, technical talent development, and cross-functional collaboration with design and manufacturing teams. | — | 0 |
| Logistics Operations Manager Logistics Operations Manager responsible for managing inbound, interplant, and outbound materials, equipment, and finished goods. This role includes managing capital warehouse operations, ensuring compliance with legal and regulatory requirements, and driving operational excellence. The manager will analyze processes, identify inefficiencies, and partner with cross-functional teams and external providers to optimize logistics solutions. | — | 0 |
| Supply Chain Engineer (SCE) Supply Chain Engineer at Intel responsible for managing supplier relationships, optimizing supply chain processes, and ensuring quality and yield improvements. The role involves NPI, ramp, HVM, and EOL support, as well as project participation and strategic planning for Intel's supply chain roadmap. | — | 0 |
| FSO Ireland Equipment Technicians This role involves performing maintenance and repair of manufacturing equipment in a semiconductor fabrication plant, troubleshooting issues, and analyzing data to improve tool performance. It requires technical proficiency, problem-solving skills, and adherence to procedures in a shift-based environment. | — | 0 |
| Analog Mixed Signal Design Engineer Seeking a Senior Mixed Signal Design Engineer to lead static timing analysis and analog circuit design for next-generation mixed-signal systems. Responsibilities include driving timing closure, executing simulations, debugging testbenches, and enhancing verification methodologies. Experience with Cadence ADE and scripting for automation is required. | — | 0 |
| Senior Staff Post-Silicon Engineer Senior Staff Post-Silicon Engineer at Intel to validate SerDes technologies, focusing on functional validation plans, methodology development, root cause analysis, and infrastructure management for mixed signal designs. Requires experience in SerDes post-silicon validation, I/O principles, and test planning. | — | 0 |
| Software Engineer Software & Infrastructure Engineer to architect, build, and maintain cloud-native applications and distributed systems for semiconductor manufacturing and testing operations. Responsibilities include full-stack development, infrastructure management (cloud/on-prem, Kubernetes), DevOps, automation, and operational support. Requires 4+ years of software development experience and US Citizenship with ability to obtain security clearance. | — | 0 |
| Materials Program Manager This role is for a Materials Program Manager at Intel, focusing on managing the supply chain for materials used in manufacturing. The responsibilities include translating market dynamics into strategies for materials planning, risk mitigation, and cost optimization, coordinating material acquisition for new product introductions and high-volume manufacturing, and collaborating with suppliers and cross-functional teams. The role requires analyzing complex data for process optimization and managing supplier relationships to ensure timely delivery and cost control. The ideal candidate will have a degree in supply chain, business, or engineering, with experience in Material Requirements Planning, risk management, and supply chain strategy. | — | 0 |
| Module Equipment Technician (Contract) The Module Equipment Technician is responsible for performing electrical or mechanical troubleshooting, setup, calibration, and preventative maintenance on manufacturing production equipment. This role involves working with Module Engineering to execute experiments and equipment configuration changes, supporting data collection, and completing tasks per published procedures. A Diploma in a relevant technical field and basic understanding of mechanical, electronic, or mechatronic systems are required. | — | 0 |
| Memory Electrical Validation Engineer Intel is seeking a Memory Electrical Validation Engineer to ensure optimized electrical performance, compliance with industry standards, and system-level reliability for memory technologies in CPU products. The role involves defining validation strategies, validating circuit analog performance, developing Memory Reference Code (MRC) requirements, designing and executing validation procedures, debugging electrical design features, and collaborating with cross-functional teams. | — | 0 |
| Working Student - HW/SW Customer Engineer (m/f/d) Working student role supporting customers integrating Intel computing products into embedded and industrial applications. Responsibilities include debugging HW/SW issues, optimizing performance, and collaborating with engineering teams. Requires basic knowledge of computer architecture and boot processes, with beneficial experience in embedded systems and debugging tools. | — | 0 |
| Materials Development Engineer Materials Development Engineer at Intel, focusing on developing, integrating, and certifying materials for assembly packaging in Malaysia. Requires a Ph.D. in a relevant engineering field with at least 5 years of experience in materials development, characterization, and supplier management. The role involves technical problem-solving, program planning, and collaboration with cross-functional teams and external suppliers. | — | 0 |
| Ethernet Hardware Product Application Engineer This role is for an Ethernet Hardware Product Application Engineer at Intel, focusing on providing technical support for Intel's Ethernet products and technologies. Responsibilities include optimizing solutions, enabling ecosystem partners, developing design and validation tools, performing design reviews (schematic, board layout, signal integrity), creating technical collateral, and resolving customer technical issues during development, testing, and production. The role requires expertise in Ethernet architecture, interfaces, networking products, signal integrity, and analog circuit design. Familiarity with scripting languages like Python for test automation is a plus. The preferred qualifications mention an interest in learning AI/ML applications, but the core role is hardware engineering. | — | 0 |