Intel currently has 84 active job listings related to artificial intelligence. The majority of these roles, 51%, are focused on serving infrastructure, with agents representing another significant portion at 24%. Engineering is the most frequent function for these positions. The company is actively hiring in the United States, China, and Mexico. Frequent technical tags include model serving, inference infrastructure, and agent orchestration. In the last 30 days, Intel has added 73 new AI roles, representing a 52% increase compared to the previous 30-day period.
Currently tracking 56 active AI roles, down 27% versus the prior 4 weeks. Primary focus: Serve · Engineering. Salary range $122k–$414k (avg $253k).
Intel currently has 59 active AI-related roles in our index. The most common open titles are: AI Software Engineering Intern (3), AI Software Engineer Intern (2), GenAI Software Solutions Engineer (2), Graduate Talent (GenAI Software Solutions Engineer) (2), AI Algorithm Engineer. Most positions are in Engineering and Research.
Intel's active AI hiring is concentrated in: serving infrastructure (49%), agents (29%), application (8%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
Intel is hiring AI talent in: United States (28 roles), China (7 roles), Mexico (6 roles), Malaysia (6 roles).
Job postings at Intel most frequently reference: model serving, inference infra, agent orchestration, rag, tool use.
In the past 30 days, Intel has posted 28 new AI-related roles. That is a -63% change versus the prior 30 days (75 → 28).
| Title | Stage | AI score |
|---|---|---|
| Software Application Development Engineer Grade Software Application Development Engineer at Intel Foundry Automation (IFA) NPI Systems team. Develops full-stack software solutions for manufacturing automation, including new product introduction workflows, execution readiness, build logistics, and DOE planning. Responsibilities cover the full software project lifecycle, from requirements analysis to testing and support. Collaborates with technology development teams and factory engineers. | — | 0 |
| EDA Tools Software Engineer Designs, develops, tests, and debugs software tools, flows, and methodologies used in design automation for hardware products, process design, or manufacturing. Requires in-depth knowledge of semiconductor physics, process technology, design rules, and EDA tools for EM, IR drop, and ESD. Scripting skills in languages like SKILL, Python, PERL, or TCL are essential. Experience applying AI/ML techniques for analog layout generation and geometry/graph-based problems is a plus. | — |
| GPU Design Verification Engineer This role focuses on the functional verification of graphics logic components (3D graphics, media, display) for GPUs. Responsibilities include defining and developing verification plans, test benches, and architecture, executing verification plans, running simulations, debugging issues, and collaborating with architects and developers. The role requires strong programming skills in System Verilog, OVM, and UVM, and experience in ASIC, CPU, or GPU verification. | — | 0 |
| Experienced IP Logic Design Engineer Experienced IP Logic Design Engineer responsible for designing, optimizing, and validating IP blocks for SoC integration at Intel in Costa Rica. This role involves RTL coding, simulation, architecture definition, and ensuring power, performance, area, and timing goals are met. Collaboration with SoC customers and verification teams is key for high-quality IP delivery. | — | 0 |
| Analog Design Architect Analog Circuit Design Engineer role at Intel, focusing on designing and developing cutting-edge analog circuits for advanced process nodes. The role involves creating high-performance analog and mixed-signal IPs, optimizing circuits for various objectives, and collaborating with cross-functional teams. Requires expertise in high-speed IO circuits and analog circuit design, with a strong foundation in CMOS design principles. | — | 0 |
| Mixed Signal Design Verification Engineer Mixed Signal Design Verification Engineer responsible for ensuring the functionality and performance of mixed signal logic components using System Verilog, UVM, and Verilog, developing test plans and environments, and debugging issues in the presilicon environment. | — | 0 |
| Design Verification Engineer Design Verification Engineer at Intel responsible for functional verification of IP logic, developing verification plans, test benches, and simulation environments. The role involves executing verification plans, debugging issues, collaborating with design teams, and maintaining verification infrastructure. | — | 0 |
| Mixed Signal Logic Design Engineer Develops logic design, RTL coding, and simulation for mixed signal and/or high-speed IPs for integration in full chip designs. Participates in architecture and microarchitecture definition, applies strategies for mixed signal designs including analog behavior modeling and circuit simulation, writes RTL, and optimizes mixed signal logic to meet power, performance, area, and timing goals. Reviews verification plans, implements corrective measures for failing RTL tests, and supports SoC customers for IP block integration. | — | 0 |
| Senior Applications and Solutions Engineer - Foundry Services Senior Applications and Solutions Engineer for Intel Foundry Services, focusing on technical support for customers using Intel's semiconductor process and packaging technologies, with a specialization in complex multi-voltage domain ASIC design implementation and verification. The role involves customer guidance, quality improvements in design kits, and performing ASIC design services. | — | 0 |
| Senior CPU Core Physical Design Engineer This role is for a Senior CPU Physical Design Engineer responsible for the physical design implementation of custom CPU designs from RTL to GDS, including synthesis, place and route, clock tree synthesis, static timing analysis, and power/clock distribution. The engineer will also conduct verification and signoff, analyze results to improve microarchitectures, and work with EDA vendors to enhance tool capabilities. The role is critical to the development of next-generation CPUs designed to power the AI revolution. | — | 0 |
| CPU Core Physical Design Engineer This role is for a CPU Physical Design Engineer responsible for the physical design implementation of custom CPU designs from RTL to GDS, including synthesis, place and route, static timing analysis, and power/clock distribution. The engineer will also perform verification and signoff, analyze results to improve microarchitectures, and work with EDA vendors to enhance tool capabilities. The role requires expertise in VLSI circuit design, static timing analysis, and low power design, with a focus on developing CPUs for the AI revolution. | — | 0 |
| CPU Verification Engineer CPU Design Verification Engineer responsible for verifying and validating high-performance, power-efficient processors. Develops and executes verification plans, creates UVM-based testbenches, performs functional coverage analysis, and debugs pre-silicon environments. Collaborates with architects and designers, and enhances verification infrastructure. | — | 0 |
| Packaging Module Development Engineer Develops and optimizes semiconductor packaging technologies, focusing on First Level Interconnect (FLI) and collaborating with cross-functional teams to improve assembly processes, scale advanced capabilities, and lead equipment development. Requires a Master's or PhD in a relevant engineering field with experience in programming/scripting (Python, MATLAB) with AI/ML concepts. | — | 0 |
| Pre-Silicon Validation Engineer Intel is seeking a Pre-Silicon Validation Engineer with 7+ years of experience to join their Central Engineering Group in Bangalore, India. The role involves defining and executing verification plans, developing test benches, and debugging complex SoC designs using SystemVerilog and UVM. The engineer will collaborate with cross-functional teams to ensure high-quality SoC delivery and contribute to Intel's next-generation products. | — | 0 |
| Assembly Equipment Group Department Manager Leads the Assembly & Finish Equipment organization at Vietnam Assembly Test (VNAT), driving improvements in quality, predictability, velocity, and affordability. Focuses on operational excellence, engineering rigor, and innovation through AI/ML and advanced engineering solutions. Owns end-to-end equipment performance for Assembly and Finish, ensuring readiness for High Volume Manufacturing (HVM) and New Product Introduction (NPI). Leverages AI/ML and automation to improve tool availability and reduce repeat issues. Builds a strong team culture and serves as the equipment leader interface to factory and site leadership. | — | 0 |
| IP Design Verification Engineer Seeking an IP Design Verification Engineer to ensure the functionality and performance of Intel's cutting-edge intellectual property (IP) designs for system-on-chip (SoC) applications, focusing on LPDDR5 and DDR5 PHY verification. Responsibilities include developing test benches, defining verification strategies, implementing test cases, debugging failures, and automating pre-silicon validation flows. | — | 0 |
| Systems and Solutions Engineer Systems and Solutions Engineer responsible for the design, development, and integration of systems including software, firmware, board, and silicon/SoC components, focusing on customer requirements and system lifecycle. The role involves systems architecture, component-level analysis, defining implementation solutions, delivering end-to-end technical solutions, and collaborating on next-generation requirements and proof-of-concept innovations. Requires strong experience with Bluetooth protocols and Windows platforms, along with bug triage and customer collaboration skills. | — | 0 |
| TD Media and Collaterals Development Engineer Develops and optimizes media and collaterals for Intel's assembly packaging platform technologies, applying statistical principles and experimental design to improve manufacturing efficiency, quality, and reliability. This role involves developing evaluation equipment, new techniques for problem identification, and consulting on design and process improvements. | — | 0 |
| Design Technology Tool Enablement Engineer The Design Technology Platform team is looking for an EDA Tools Software Engineer to design, develop, test, and debug software tools and flows for process design and manufacturing. This role involves collaborating with process developers and EDA vendors, automating workflows, and ensuring seamless integration with design methodologies. The position requires expertise in scripting languages, EDA tools, and semiconductor device physics. | — | 0 |
| IT Support Specialist IT Support Specialist (L4) providing advanced operational and technical support for Microsoft Teams, Teams Rooms (MTR), Audio/Visual (AV), and Telephony services in a global, 24x7 enterprise environment. Responsibilities include ensuring high availability, performance, and user experience across meeting rooms, conferencing services, and voice systems. The role acts as an escalation point for complex incidents, leads problem management, and proactively maintains service health. This includes readiness validation for conference rooms, lifecycle management of MTR systems, voice infrastructure operations, and live meeting support. | — | 0 |
| Security Software Development Engineer Security Software Validation Engineer at Intel, focusing on validating complex software-hardware security innovations for Intel CPUs using Pre-Silicon simulations and identifying/mitigating security risks. Requires strong C++/C programming and software development experience. | — | 0 |
| Systems and Hardware Enabling Engineer This role provides technical support for Intel products and technologies, focusing on solution design, development, validation, and market readiness. It involves creating technical collateral, enabling partners, and collaborating with customer R&D and manufacturing to ensure smooth product integration and ramp-up. The role requires strong C programming and UEFI/BIOS firmware development experience. | — | 0 |
| SoC Physical Design Engineer Physical Design Engineer at Intel responsible for the end-to-end physical design implementation of next-generation Client SoCs, from RTL to GDS. This includes synthesis, floor planning, placement, routing, clock tree synthesis, power analysis, verification, and signoff. The role also involves performance optimization, developing and improving physical design methodologies, and automating design flows. | — | 0 |
| Senior Clock Architecture & Design Engineer Senior Clock Architecture & Design Engineer role focused on developing clocking architecture for next-generation CPUs, involving the design of clock distribution networks, custom circuits, and optimization of clock tree synthesis flows. Requires experience in physical design, CTS, static timing analysis, and custom circuits. | — | 0 |
| Principal Analog Circuit Design Engineer - SerDes Principal Analog Circuit Design Engineer with expertise in high-speed SerDes applications, focusing on design, development, and verification of analog circuits in advanced process nodes. The role involves floorplanning, circuit design, parameter extraction, simulation, test plan creation, and optimization for power, performance, area, timing, and yield. Requires strong foundational knowledge of analog design principles and hands-on experience with advanced FinFET CMOS processes and simulation tools. The principal engineer is expected to influence technical direction, mentor junior engineers, and drive technical strategy. | — | 0 |
| Principal Analog Circuit Design Engineer - SerDes Principal Analog Circuit Design Engineer to lead the design and validation of cutting-edge analog circuits for high-speed (112G and 224G) SerDes applications. Requires expertise in PLL, CDR, CTLE, DFE, ADC, or TX design, and experience with advanced FinFET CMOS technologies. Role involves technical direction, mentorship, and cross-functional collaboration. | — | 0 |
| Principal Analog Circuit Design Engineer - SerDes Seeking a Principal Analog Design Engineer to lead the design and validation of high-speed analog circuits for SerDes applications. Requires expertise in analog/mixed-signal design, high-speed communication standards, and silicon bring-up. Will mentor junior engineers and collaborate with cross-functional teams. | — | 0 |
| RTL Design Engineer Develops logic design, RTL coding, and simulation for CPU cell libraries, functional units, and IP blocks. Participates in architecture and microarchitecture definition, optimizes logic for power, performance, area, and timing, and reviews verification plans. Documents microarchitectural specs and supports SoC customers. | — | 0 |
| System Modelling Engineer This role is for a System Modelling Engineer at Intel, focusing on the architecture, modeling, and performance analysis of 224Gbps SerDes IP. The engineer will develop end-to-end PHY system models, analyze electrical channels, optimize equalization algorithms, and perform clocking, jitter, and noise analysis. The role also involves supporting industry standards, defining test methodologies, and collaborating with cross-functional teams. The position requires a strong background in analog circuit design and high-speed design techniques. | — | 0 |
| Supply Chain Engineer Supply Chain Engineer responsible for direct material issues in the ATM assembly test process, managing quality, new product introductions, cost reduction, and continuous improvement. The role involves defining inspection methodologies, optimizing the supply chain, and collaborating with suppliers. It also includes leading and mentoring junior engineers and contributing to future technology definitions. | — | 0 |
| Practical Engineering Student for Intel Kiryat Gat Seeking a Practical Engineering student for a semiconductor manufacturing facility to support advanced equipment, learn maintenance and troubleshooting, and collaborate with engineering teams. Role involves hands-on experience in a high-volume, cutting-edge fabrication environment. | — | 0 |
| Analog Circuit Design Engineer Analog Circuit Design Engineer responsible for designing and developing analog circuits in advanced process nodes for analog and mixed-signal IPs, optimizing for power, performance, area, timing, and yield. Requires experience in PLLs, clocking circuits, LC VCO/DCO design, and CMOS fundamentals. | — | 0 |
| Analog Circuit Design Engineer Analog Circuit Design Engineer at Intel focusing on high-speed interconnect solutions, designing and verifying analog circuits in advanced process nodes. Responsibilities include transistor-level design, simulation, optimization, and post-silicon validation for SerDes PHY analog blocks. | — | 0 |
| Analog Circuit Design Engineer Intel is seeking an Analog Circuit Design Engineer to design, simulate, and verify analog circuits for advanced process nodes, focusing on high-speed SerDes (112/224Gbps). The role involves optimizing circuits for power, performance, area, and yield, and collaborating with cross-functional teams. Experience with EDA tools and CMOS technologies is required. | — | 0 |
| Analog Circuit Design Engineer Analog Circuit Design Engineer at Intel, focusing on designing, developing, and optimizing high-speed analog circuits in advanced process nodes for next-generation memory interface PHYs. Responsibilities include circuit design, simulation, optimization for power/performance/area, test plan creation, collaboration with cross-functional teams, layout reviews, and post-silicon debug. | — | 0 |
| Manufacturing Operator (Contract) Manufacturing Operator role focused on product manufacturing, assembly, equipment operation, data collection, and process optimization in an industrial setting. Requires technical aptitude and adherence to SOPs. | — | 0 |
| SerDes Circuit Design Engineer Design, develop, and optimize high-speed SerDes circuits for Intel's next-generation technologies, collaborating with cross-functional teams and supporting silicon validation. | — | 0 |
| Analog Circuit Design Engineer Analog Circuit Design Engineer at Intel, responsible for designing, developing, and optimizing high-speed analog circuits in advanced process nodes. This role involves circuit design, validation, simulation, optimization for power/performance/area/timing/yield, test plan creation, cross-functional collaboration, and post-silicon debug. Requires expertise in high-speed analog circuits like TX/RX blocks, PLLs, DLLs, SerDes, and voltage regulators, with proficiency in industry-standard tools. | — | 0 |
| Analog Circuit Design Engineer Analog Circuit Design Engineer at Intel responsible for designing, developing, and optimizing high-speed analog circuits in advanced process nodes, contributing to next-generation memory interface PHYs and analog/mixed-signal IPs. Involves circuit design, simulation, validation, optimization for power/performance/area, test plan creation, collaboration with cross-functional teams, layout reviews, and post-silicon debug. | — | 0 |
| Analog Circuit Design Engineer Analog Circuit Design Engineer at Intel responsible for designing, developing, and optimizing high-speed analog circuits in advanced process nodes, contributing to next-generation memory interface PHYs and analog/mixed-signal IPs. Involves circuit design, simulation, validation, optimization for power/performance/area, test plan creation, collaboration with cross-functional teams, layout reviews, and post-silicon debug. | — | 0 |
| APTM Advanced Packaging Dry Etch Development Manager Lead a team of process engineers in developing and implementing dry etch processes for next-generation advanced packaging solutions at Intel Foundry. This role involves managing engineers, formulating long-term strategies, overseeing production-worthy etch processes, and driving yield improvement initiatives. | — | 0 |
| WPM- C4 Production Line Coordinator Technician Contract (Swing Shift) This role is a Production Line Coordinator Technician in a wafer fab at Intel. The primary responsibilities involve identifying and eliminating barriers to tactical execution, managing line limiters, optimizing line management, WIP management, and Critical Queue Time (CQT). The role requires understanding production systems, analyzing lot flow and tool performance data, and collaborating with module teams. It is a contract position with a swing shift schedule. | — | 0 |
| Fab Equipment Maintenance Commodity Manager Commodity Manager responsible for developing and managing supply chain solutions for fab equipment spares and service. This role involves developing and executing commodity strategies, negotiating contracts, managing supplier relationships, and identifying cost-saving opportunities within Intel's global supply chain. | — | 0 |
| Senior CPU Physical Design Engineer Senior CPU Physical Design Engineer at Intel, responsible for the physical design and verification of E-Core/Atom microprocessors. This role involves qualifying PDKs, standard cell libraries, and managing the RTL2GDS flow, including synthesis, floor planning, place and route, static timing analysis, power analysis, and reliability checks. The engineer will also collaborate with cross-functional teams and EDA vendors to enhance design methodologies and automate processes. | — | 0 |
| SOC Physical Design Static Timing Analysis Engineer This role focuses on Static Timing Analysis (STA) for System-on-Chip (SoC) physical design at Intel. The engineer will perform timing analysis, generate and verify timing constraints, address timing violations, conduct timing rollups, and develop optimized clock networks. They will also define methodologies for timing models, establish PVT conditions, and collaborate with various teams (clocking, architecture, DFT, logic design) to ensure designs meet performance and power efficiency requirements. The role involves contributing to tools, flows, and methodologies for physical design and timing processes. | — | 0 |
| Manufacturing Operations Manager Manufacturing Operations Manager at Intel in Penang, Malaysia. This role involves leading a team of technicians to oversee operations, equipment maintenance, and repair in manufacturing facilities. Responsibilities include managing safety, quality, scheduling, conflict resolution, streamlining processes, and ensuring production schedules are met within quality and cost objectives. The manager will also focus on employee staffing, training, development, retention, and establishing long-term strategies for manufacturing capabilities. Requires a Bachelor's degree in a related field and 2-6 years of relevant experience. | — | 0 |
| Project Controls Engineer Project Controls Engineer at Intel Foundry Construction Sourcing responsible for cost/estimating/schedule controls for semiconductor manufacturing factory projects. This role involves cost reporting, forecast development, leading estimate development, driving process improvements, financial updates, cost reduction strategies, and partnering with procurement on commercial activities. Requires experience in estimation, cost control, capital, OpEx/Spending, and FPnA. | — | 0 |
| Data Architect This role is for a Data Architect within Intel's Corporate Planning Group Data and Analytics team. The primary focus is on driving insights and analytics through data analysis, requirement gathering, report development, data quality, governance, and validation. The role involves working with data used in various business functions like demand planning, supply planning, sales, manufacturing, and finance, and supporting data architecture strategy. While the role mentions using AI coding assistants as a preferred qualification, the core responsibilities are centered around traditional data architecture, BI, and reporting, not the direct development or deployment of AI/ML models. | — | 0 |
| Wet Etch Cleans Technical Manager Technical Manager for Wet Etch Cleans in Intel's Logic Technology Development, focusing on advanced logic nodes and High Volume Manufacturing. This role involves hands-on process development, R&D to HVM deployment, and technical leadership. | — | 0 |
| Memory Validation Intern Intern position contributing to the functional, power, performance, and memory validation of Intel silicon products. Responsibilities include debugging, data analysis, validation coverage assessment, test automation, and developing validation infrastructure. Requires current pursuit of a relevant Bachelor's or Master's degree and 3+ months of experience in signal integrity electronic circuit analysis and data analysis techniques. | — | 0 |