This role is for a Silicon Design Verification Engineer at AMD, focusing on verifying complex IP designs for processors. Responsibilities include creating test plans, designing testbenches using System Verilog and UVM, formal verification, debugging, and ensuring quality metrics. The role requires a Master's degree in computer or electrical engineering and experience with verification methodologies and scripting languages.

AMD is seeking an IP Verification Engineer to join their AECG Group. The role involves verifying cutting-edge FPGAs and ASICs for various customers, collaborating with architecture, IP design, PD, and product engineering teams. Responsibilities include developing test plans, coding UVM-based testbenches, building directed and random tests, and debugging failures to ensure high design quality. Preferred experience includes IP level ASIC verification, Verilog, System Verilog, UVM frameworks, and scripting for automation. Familiarity with computer architecture and protocols like PCIe, CXL, NVMe, or Ethernet is also beneficial.

This role is for a Verification Engineer working on FPGA and ASICs, focusing on IP verification for PCIe CXL based IPs. Responsibilities include developing test plans, coding UVM based testbenches, running regressions, and debugging failures. While generative AI is mentioned as a potential plus for verification tools, the core of the role is traditional hardware verification.

AMD is seeking a Verification Engineer to join their AECG Group, focusing on cutting-edge FPGA and ASIC development for various customers. The role involves collaborating with architects, design, and product engineers to ensure first-pass silicon success. Responsibilities include developing test plans, coding UVM-based testbenches, building directed and random tests, and debugging failures to ensure high design quality.

This role is for a Debug Engineer at AMD, focusing on the Server DPPM Data Center for AMD EPYC processors. The responsibilities include leading the debug team, driving improvements in testing and failure identification, and working with cross-functional teams to root-cause product issues. The role requires a strong understanding of x86 architecture, post-silicon validation, and semiconductor manufacturing processes. Experience in system-level debug, fault isolation, and scripting languages like Python is preferred.

This role focuses on the design and implementation of features within ML Processor & Digital IP for AMD. The responsibilities include driving feature definition, RTL implementation, and collaborating with various engineering teams. The role requires a strong understanding of digital design concepts, computer architecture, and PPA trade-offs, with a plus for GPU programming and architecture knowledge.

AMD is seeking a Client Public Relations (PR) Manager to lead tactical PR programs supporting Client Computing and Graphics product launches, reviews, and momentum campaigns. This role partners closely with regional PR teams to coordinate consumer client and graphics communications globally, with direct responsibility for North America. The PR Manager will cultivate and support relationships with media, bloggers, content creators, YouTubers, and industry influencers to drive positive coverage, reinforce key product messages, and amplify AMD thought leadership. Internally, this role collaborates with business units and marketing teams to develop messaging, content, and communications strategies that support product launches and ongoing campaigns. The overall objective is to maximize positive editorial coverage and engagement across North America and globally. This position also oversees press sampling and review program strategy across the Client and Graphics portfolios, ensuring alignment between business objectives, marketing priorities, and regional execution.

This role is for a Sr. Analog Design Engineer at AMD, focusing on the definition, specification, and implementation of high-speed and high-precision memory interface PHY circuits (DDR, LPDDR, GDDR). The engineer will be responsible for circuit design, layout quality, electrical and timing analysis, and reliability checks, interfacing with cross-functional teams. Experience in analog/mixed-signal circuits for memory interfaces or serial links is preferred.

This role is for a Sr. Memory Subsystem Verification Engineer at AMD, focusing on pre-silicon verification of advanced Network-on-Chip (NoC) architectures and DRAM memory controller IPs (LPDDR6, HBM4). The engineer will drive verification strategies, develop simulation and formal verification environments, and collaborate with design, architecture, and software teams to ensure high-quality silicon.

This role is for a SOC/Debug Lead Engineer focused on AMD's Server and AI Platforms. The primary responsibilities involve leading system validation plans, collaborating with various engineering teams for root cause analysis of platform and SoC issues, and improving debug methodologies. The role requires a strong understanding of server platform components, CPU architectures, and experience with debugging tools and scripting. While the role works with AI platforms, the core function is hardware validation and debug, not AI model development or research.

This role is for a Physical Design / PnR Lead at AMD, focusing on the implementation and convergence of complex ASIC and APU/dGPU designs for various applications including AI inference. The lead will manage a team, drive backend activities from RTL to GDS, and collaborate with cross-functional teams to achieve PPA optimization and first-pass silicon success. Experience with physical design flows, timing closure, and verification is required.

This role is for a PHY-V Lead at AMD, responsible for physical verification sign-off, full-chip integration, and packaging interface planning for advanced SoC programs. The lead will drive DRC/LVS clean tapeouts, integration quality, and sign-off predictability, requiring expertise in physical verification, top-level integration, and advanced packaging alignment. The role involves leading cross-functional execution across PD, Analog, and Packaging teams, with a focus on quality, manufacturability, and schedule predictability in high-pressure tapeout environments.

This role is for an Occupational Health Program Manager at AMD. The primary responsibilities include developing, implementing, and managing comprehensive occupational health programs such as injury prevention, workers' compensation, OSHA recordkeeping, medical accommodations, and emergency response. The role also involves data analysis, reporting, fostering a culture of well-being, and collaborating with various internal teams. While the company mentions AI and the role has preferred experience with basic AI tools, the core function of the job is not AI/ML development or research.

Director of Hardware Systems Engineering at AMD, focusing on leading teams in the design, validation, and launch of cutting-edge hardware products, including defining system architecture, managing teams, and resolving complex hardware issues related to PCIe, memory, and high-speed ethernet. The role involves strategic leadership, team management, product development lifecycle ownership, root cause analysis, and driving hardware improvements.

This role is for a Server Customer Debug Engineer at AMD, focusing on resolving customer issues related to RAS, PCIe, Memory, MCA, CXL, and Micro-Controller failures. It involves using debug tools, collaborating with global teams, and providing recommendations for validation and root cause analysis. The role requires expertise in silicon and system engineering for customer enablement and debug.

AMD is seeking an Interconnect Micro-architect/RTL Design Engineer to help build the next generation coherent interconnect for CPUs, GPUs, and special purpose accelerators. The role involves architectural exploration, microarchitectural definition, RTL design, optimization for power/performance/area/timing, and participation in post-silicon debug.

Mechanical/Thermal Engineer role focused on designing and validating advanced liquid cooling solutions for high-performance systems, including AI and data centers. Responsibilities include CAD design, thermal/fluid analysis, experimental testing, and cross-functional collaboration within an Agile framework.

This role focuses on the design and verification of power systems for AMD's Instinct Graphics Processing Units (GPUs), which are used in AI and data centers. The engineer will work on power delivery networks, component selection, layout guidelines, and system-level validation. While the role supports AI hardware, it is not directly involved in building or researching AI models or agents.

This role is for a Senior Program Manager at AMD, focusing on leading end-to-end execution of complex System-on-Chip (SoC/ASIC) development programs. The role involves planning, tracking, reporting, and risk management across all phases from architecture through tapeout and post-silicon. While the role mentions leveraging AI for execution efficiency and using AI tools, the core function is program management for SoC development, not direct AI/ML model development or research. The primary deliverable is the successful execution of the SoC program, which can be considered a shipped product (L6).

This role is for a Power Engineer focused on server systems, involving hardware requirements definition, power supply design, system-level power distribution, test plan development, and cross-functional collaboration. It requires expertise in analog and digital circuit design, power supply topologies, and lab equipment usage. The role is not directly involved in building or researching AI/ML models.

This role is for a Senior Program Manager at AMD, focusing on leading end-to-end execution of complex System-on-Chip (SoC/ASIC) development programs. The role involves planning, tracking, reporting, and risk management across all phases from architecture through tapeout and post-silicon. While the role mentions leveraging AI for execution efficiency and using AI tools, the core function is program management for SoC development, not direct AI/ML model development or research. The primary deliverable is the successful execution of the SoC program, which can be considered a shipped product (L6).

This role focuses on performance and benchmarking of CPU, GPU, and NPU on Linux-based systems, involving kernel programming, system-level debugging, and automation of performance analysis. The engineer will analyze kernel logs, profiling data, and optimize OS and kernel behavior for repeatable performance insights.

This role is for a Lead / Principal Systems Design Engineer at AMD, focusing on driving and improving the quality and delivery of AMD's technologies. The engineer will be responsible for technical innovation in validation, tool and script development, methodology enhancement, debugging issues, tracking test execution, and collaborating with various teams. Experience in programming, debugging, lab equipment, and system architecture is preferred.

This role is for a Customer Debug Engineer focused on Datacenter Platform Engineering at AMD. The primary responsibilities involve issue isolation, debug, and validation for AMD's Data Center products, working with ODMs, OEMs, and customers. The role requires interaction with internal engineering teams and a strong understanding of server design, debug tools, and high-speed IO protocols. While the company mentions AI and its role in shaping the future, this specific position is centered on hardware platform debugging and validation, not on building or researching AI/ML models or systems.

This role is for a Customer Program Manager at AMD, focusing on managing customer programs for data center platform engineering, from concept to mass production. The role involves working with ODMs/OEMs, managing customer requirements, schedules, and issues, and ensuring effective communication between customers and internal AMD teams. The Program Manager will report on customer program status to executives, support various internal teams, and drive corrective actions to improve processes. Familiarity with AI and Machine Learning workloads is preferred, but the core function is program management, not AI/ML development.

Software BIOS/BMC Engineer responsible for developing, debugging, and testing BMC and Security firmware for DCGPU products, collaborating with cross-functional teams and customers to enhance manageability, reliability, and security.

This role supports ODM/OEM and customers in the Data Center Business, focusing on debugging and resolving multi-disciplinary customer issues across Data Center CPU, GPU, and system levels. The engineer will work with software/FW development teams, enable customer software/FW, assist in development and validation, and provide technical training. Responsibilities include board bring-up, driver optimization, and serving as a subject matter expert for BIOS/Firmware.

This role is for a Customer Program Manager at AMD, focusing on managing customer programs for data center platform engineering, from concept to mass production. The role involves working with ODMs/OEMs, managing customer requirements, schedules, and issues, and ensuring effective communication between customers and internal AMD teams. The Program Manager will report on customer program status to executives, support various internal teams, and drive corrective actions to improve processes. Familiarity with AI and Machine Learning workloads is preferred, but the core function is program management, not AI/ML development.

This role is for a Lead IP Block level Verification Engineer at AMD, focusing on Network on Chip (NOC) IPs and Subsystems. The engineer will architect, develop, and use verification environments (simulation and formal) to ensure the functional correctness of NOC IPs, subsystems, and SOC designs. Responsibilities include planning verification, designing testbenches in System Verilog and UVM, debugging, and coverage analysis. Experience with verification techniques, ASIC development phases, and specific protocols like AXI/DDR/PCIe is preferred.

This role is for an ASIC Subsystem/Block Level Verification Engineer at AMD, focusing on Network on Chip (NOC) IPs and Subsystems. The engineer will architect, develop, and use simulation and formal verification environments to ensure the functional correctness of NOC IPs, subsystems, and SOC designs. Responsibilities include planning verification, designing testbenches in System Verilog and UVM, debugging, and coverage analysis. While the company mentions AI and data centers, this specific role is in hardware verification, not AI model development.

The role is for an IP/Subsystem Verification Lead responsible for verifying cutting-edge FPGA and ASICs for various customers. This involves collaborating with architects and engineers, developing test plans, coding UVM-based testbenches, running regressions, and debugging failures to ensure high design quality.

Lead the Front-end SoC Design team in India for AMD's flagship Instinct GPU SoC, overseeing the entire front-end process from micro-architecture to netlist. This role requires extensive leadership experience in complex SoC design, including IP integration, verification, power management, and post-silicon support.

The EHS Engineer is responsible for administering Environmental, Health and Safety (EHS) programs across AMD’s Malaysia Research & Development operations and supporting functions in Penang and Cyberjaya. This role, based in Penang, is focused on ensuring full compliance with Malaysian regulatory requirements, including the Department of Occupational Safety and Health (DOSH), as well as AMD corporate policies and procedures. This position will serve as the primary liaison between AMD and DOSH, supporting regulatory inspections, reporting, and engagement. The EHS Engineer will work closely with regional and global EHS teams, site leadership, and site employees to maintain a safe and healthy work environment, implement programs, and drive continuous improvement in EHS performance.

This role is for a Silicon Design Engineer focused on Design for Test (DFT) for AMD's Radeon Technologies Group. The engineer will be responsible for implementing and verifying DFT architecture, scan insertion, ATPG pattern generation, and post-silicon support to ensure successful bring-up and yield learning. The role requires a strong understanding of DFT methodologies and experience with relevant tools and scripting languages.

AMD is seeking a results-driven PCBA Manufacturing Program Manager to lead cross-functional initiatives across engineering, supply chain, production, and quality to ensure seamless program execution from NPI to full-scale production. The role requires a deep understanding of PCBA manufacturing operations, SMT processes, and continuous improvement.

This role is for a DFT Engineer at AMD, focusing on the definition, implementation, and verification of Design for Test (DFT) for System-on-Chip (SOC) within the Strategic Silicon Solution Business Unit. The engineer will work on cutting-edge DFT technology, participate in SOC DFT architecture definition, implement various DFT functions (SCAN, MBIST, etc.), perform verification, generate timing constraints, and assist with ATE bring-up and DFX logic.

This role focuses on testing and validating optical transceivers for high-performance and reliability in fiber optic communication systems. It involves developing validation plans, performing calibration and testing, setting up automated test platforms, analyzing results, and collaborating with design teams to improve product quality. The role requires a strong foundation in optical communication systems and hands-on experience with optical components and high-speed link validation.

AMD is seeking a Technical Program Manager for their Pre-Silicon Development team, focusing on driving the execution of key development programs from concept to tape out for AI and data center computing experiences. The role involves coordinating across various engineering teams, managing project plans, schedules, resources, and risks, and ensuring program success in terms of scope, schedule, and spend.

Senior Hardware Validation & Failure Analysis Engineer at AMD responsible for leading hardware validation, system bring-up, failure analysis, and product sustainment activities across complex computing and embedded hardware platforms. This role involves evaluating product performance throughout the product lifecycle, from pre-silicon validation to manufacturing support and field issue resolution.

Analog/Mixed-signal SerDes Design Engineer at AMD, focusing on high-speed receiver and transmitter design using advanced CMOS processes. Responsibilities include circuit architecture definition, link-level simulation, and modeling of RF passive components and optical structures.

This role is a Director, Lenovo Global Account Manager responsible for leading AMD's global engagement with Lenovo across Data Center and Client businesses. The role focuses on defining and executing global program strategy, driving platform adoption, expanding revenue and market share, and strengthening AMD's position across Lenovo's portfolio. It involves executive engagement, platform strategy, AI infrastructure growth, and global account leadership, leveraging AI-enabled tools for planning and forecasting.

This role is for a Senior Software Development Engineer at AMD, focusing on firmware development for AMD Secure Encrypted Virtualization. The engineer will design, develop, and debug firmware solutions for new processors, collaborate with customers and partners, resolve technical challenges, and align efforts across engineering teams. The role requires strong C/C++ skills, experience in firmware or device driver development, and an understanding of secure coding processes and encryption technology. Experience with virtualization, hypervisors/VMs, and Linux kernel is desired. The role is not directly AI/ML development but is within the broader context of AMD's work in AI and data centers.

AMD is seeking an Emulation Engineer for their CPU Silicon Emulation team in Bangalore, India. This role involves deep understanding of AMD X86 CPU architecture and microarchitecture, debugging emulation issues of RTL, and providing feedback to the design team in a pre-silicon and emulation environment. The position requires experience in emulation environments, debugging low-level software and hardware issues, CPU and SoC architectures, Verilog/SystemVerilog, and scripting languages like Python and TCL. Experience with FPGA expertise and processor/ASIC design verification is also important.

Test Engineer at AMD responsible for designing and verifying DC power solutions for AI server products, including CPU/GPU core power, POL, LDO, and HSC/E-Fuse. The role involves supporting design engineers, performing failure analysis, and improving test processes. Experience in server/GPU product development and automation test tool development is preferred.

This role is for a Memory Validation Staff Engineer at AMD, focusing on the memory sub-system of new processors. The responsibilities include developing test plans, feature enablement, and debugging electrical issues. The person will lead a team, provide technical leadership in DDR interface validation, and collaborate with design, firmware, and software teams. Experience in system validation, DDR interface, and electrical/functional test plans is preferred, along with scripting skills.

This role is for a Physical Design Engineer at AMD, focusing on SOC solution delivery and implementation optimization. The engineer will lead PPA optimization and 3DIC solutions, and develop AI methods to improve FEINT and PD work efficiency. Experience with RTL-to-GDS, advanced process nodes, 3DIC design, and PPA optimization is preferred, especially in combining AI methods.

This role is for an MTS Silicon Design Engineer at AMD, focusing on the development and signoff of complex multi-mode/multi-corner timing constraints for RTL and signoff. The engineer will ensure constraint quality, drive pre-route timing checks, and perform timing closure for chip subsystems or full chips. The role requires strong knowledge of SDC, EDA timing tools, and Tcl scripting.