AMD currently has 35 active AI-related job listings. The majority of these roles, 66%, are focused on serving infrastructure. Engineering is the dominant function, with 32 positions. Frequent technical tags include model_serving, inference_infra, and evals, suggesting a focus on the deployment and evaluation of AI models. In the last 30 days, AMD posted 37 new AI roles.
AMD currently has 59 active AI-related roles in our index. The most common open titles are: DC-GPU Performance Modeling Engineer (3), Sr. Software Development Engineer (3), Data Center Engineer (2), MTS Software Development Engineer (2), Software Development Engineer (2). Most positions are in Engineering and Research.
AMD's active AI hiring is concentrated in: serving infrastructure (78%), data (10%), agents (5%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
AMD is hiring AI talent in: United States (30 roles), India (13 roles), Poland (5 roles), China (5 roles).
Job postings at AMD most frequently mention: GPU Computing, Computer Architecture, Python, C++, PyTorch.
In the past 30 days, AMD has posted 70 new AI-related roles.
| Title | Stage | AI score |
|---|---|---|
| Director of Software Validation Engineering – ROCm Director of Test Engineering for ROCm software stack, focusing on AI training, inference, and HPC workloads. The role involves leading and transforming the quality function by scaling the team's impact through AI and agentic tooling, building an autonomous quality organization. Responsibilities include defining test strategy, building continuous testing infrastructure, and driving adoption of AI-assisted testing workflows. | ShipServe | 8 |
| 3D IC and ADVANCED PACKAGING CAD ENGINEER This role focuses on integrating AI and ML capabilities into CAD and EDA workflows for 3D-IC and advanced packaging design. The engineer will develop and deploy agentic AI systems, LLM-assisted automation, and ML-based optimizations to improve design quality of results (QoR) in areas like timing, area, and performance. The role requires a strong silicon hardware design background, software/scripting proficiency, and hands-on experience applying AI to CAD/EDA problems. |
| Agent |
| 7 |
| PMTS Software Applications Eng. This role is for a Principal Member of Technical Staff (PMTS) Software Development Engineer in AMD's AI Enterprise applications and platform engineering organization. The engineer will design, build, and evolve secure, reliable AI infrastructure applications and tools for deploying, running, and scaling ML and LLM workloads on cloud and GPU infrastructure. The role involves full-stack engineering, technical and strategic leadership, influencing roadmap and architecture, and partnering with product and customers. Key responsibilities include owning backend services and user-facing applications for AI/GPU and platform workflows, setting architectural direction for Kubernetes toolchain, optimizing systems for efficiency and reliability, and embedding engineering excellence. The role also involves customer interaction, leading initiatives from requirements to shipped outcomes, and mentoring engineers. Experience with GPU workloads, ML/LLM training or inference pipelines, and multi-tenant platform concerns is highly desirable. | ServeAgent | 7 |
| Lead Packaging Automation Engineer This role focuses on developing and deploying AI-assisted workflows and automation for advanced packaging design in the semiconductor industry. The Lead Packaging Automation Engineer will optimize design stages using AI/ML, transition to agentic design models, and build closed-loop optimization systems. | Agent | 7 |
| Discrete Graphics Lead Systems Engineer Lead silicon evaluation, system validation, platform optimization and bring-up for AMD's latest discrete graphics and AI server solutions. This role requires leadership and hands-on lab work through the silicon and system life cycle of the product. You will also collaborate across silicon, firmware, software and platform teams to deliver cutting edge discrete graphics solutions. | — | 5 |
| HW/SW Co-Design Engineer This role focuses on the hardware/software co-design of next-generation GPU solutions, specifically for ML/HPC workloads. The engineer will optimize GPU kernels, prototype ideas across the stack, and work with architects to propose innovative solutions. Experience with ML networks, building libraries for ML operators, and compiler stacks is preferred. | Serve | 5 |
| Fall 2026 Short Term ROCm Libraries Technical Program Management Intern/ Co-Op This is an internship/co-op role focused on Technical Program Management within AMD's AI GPU Software (AGS) group, specifically working on GPU-accelerated libraries for the ROCm open-source platform. The role involves facilitating AI and HPC acceleration, documenting requirements, developing project plans, tracking progress, supporting issue resolution, developing dashboards, and driving process improvement initiatives. The intern will gain experience in technical program management for AI/HPC on AMD GPUs, process automation, and open-source development. | Serve | 5 |
| Senior EMC/RFI Design and Test Engineer Senior EMC/RFI Design and Test Engineer at AMD responsible for design and validation testing on AMD ICs and their associated Platforms-PCBs reference design & Systems. The role involves performing design work to meet EMC and RFI requirements, developing design guidelines and test procedures, supporting simulation needs, writing test plans, performing validation and debug tests, and assisting in EMC certification. The candidate is expected to embrace AI and leverage AI LLM and Agentic AI to accelerate the design and testing workflow. | — | 5 |
| Senior Software Development Engineer - Profiling Tools Senior Software Engineer to develop and optimize GPU profiling tools for HPC and AI workloads, focusing on ROCprofiler-SDK components, new features, and performance optimization. Requires strong C++ and GPU architecture understanding. | — | 5 |
| SoC DFX Staff Engineer Seeking an experienced SoC DFX Engineer to define, design, and verify Design for Test (DFT) and Design for Debug (DFD) solutions for complex, high-performance SoCs. This role involves collaboration with architecture, RTL, firmware, and verification teams to integrate DFX features for silicon validation, bring-up, and debug across the product lifecycle. | — | 0 |
| System Firmware Test Development Engineer AMD is seeking a System Firmware Test Development Engineer to join their firmware validation team. The role involves shaping firmware validation across pre-silicon and post-silicon environments by building scalable, automation-ready test solutions. Responsibilities include defining test strategies, designing end-to-end test flows, building automation-ready tests, analyzing requirements, executing tests, debugging failures, and contributing to simulation environments and test infrastructure improvements. The role emphasizes collaboration with firmware architects and SoC design teams, with a focus on low-level system behavior and building reliable test solutions. While AI-assisted tooling is mentioned, the core of the role is firmware validation for CPUs and GPUs. | — | 0 |
| Software Engineer - FPGA Physical Implementation Software engineer role focused on developing and optimizing algorithms for FPGA physical implementation tools, including placement, routing, and timing. The role involves improving performance, scalability, and quality of results within AMD's FPGA toolchain, with exposure to emerging areas like Network-on-Chip architectures. | — | 0 |
| Design Verification Engineer Design Verification Engineer at AMD, focusing on RTL design verification for memory and systems IP. Responsibilities include developing testbenches, interacting with architects and designers, creating test plans, and improving productivity through automation. | — | 0 |
| Analog Designer (1 year contract) This role focuses on physical verification of I/O pad rings for AMD products, ensuring integration issues are identified and resolved before final chip integration. Responsibilities include assembling macros/IPs into a database, running verification tools (DRC, LVS, ERC, PERC), and facilitating reviews and waivers. | — | 0 |
| Lead Board Hardware Debug Engineer – Datacenter & AI Platforms Lead Board Hardware Debug Engineer for Datacenter & AI Platforms at AMD. Focuses on complex board-level debug, hardware validation from prototype to production, and system-level integration for high-performance GPU platforms. Requires strong skills in signal integrity, PCB-level debug, and problem-solving across silicon, firmware, and system domains. | — | 0 |
| Automation Software System Design Engineer This role focuses on designing and implementing automation solutions to improve efficiency and quality across AMD's product lines, particularly in computing and graphics. The engineer will develop automation frameworks, integrate tools, and debug system-level issues across hardware and software. While AI tools are mentioned as preferred experience for productivity, the core function is automation engineering for product development, not direct AI model building or research. | — | 0 |
| Design Verification Engineer Design Verification Engineer at AMD, focusing on verifying PCI Express designs using UVM and developing test plans for next-generation products. The role involves all aspects of ASIC design stages, including testbench development, test case writing, coverage analysis, and debugging. | — | 0 |
| Physical Design Engineer This role is for a Physical Design Engineer at AMD, focusing on improving Performance, Power, and Area (PPA) for next-generation graphics processor IP. The engineer will collaborate with RTL, Physical Design, Methodology, and CAD teams to translate architectures into silicon, influencing design decisions from concept to tape-out. Responsibilities include driving PPA improvements, optimizing memory placement and synthesis recipes, resolving bottlenecks, exploring area/power savings, optimizing tools/flows, and delivering best-known recipes. Preferred experience includes ASIC Physical Design, RTL analysis, timing analysis, library understanding, experience with low-voltage design and STA correlation, and experience with taping out advanced SOC nodes. The role also involves mentorship. | — | 0 |
| IREM Physical Design Engineer This role focuses on power integrity solutions for AMD's next-generation SoCs and advanced packaging technologies. Responsibilities include defining and optimizing power delivery networks, performing IR-drop and EM analysis, and shaping design methodologies for CPU/GPU products. The role involves partnering with physical design, packaging, and CAD teams, and influencing architecture-level decisions. | — | 0 |
| IP Post-Silicon Validation Engineer This role is for an IP Post-Silicon Validation Engineer at AMD. The primary focus is on validating hardware IP for AMD's APU, CPU, Compute, and Discrete Graphics SOC programs. Responsibilities include defining and executing test plans, debugging IP issues, and collaborating with cross-functional teams on pre-silicon activities. The role also involves developing and enhancing validation tools and methodologies. While the company mentions AI and next-generation computing, the core responsibilities of this specific role are in hardware validation and engineering, not direct AI/ML model development or deployment. | — | 0 |
| IP Validation Design Engineer AMD is seeking an IP Validation Design Engineer to join their NBIO Team. The role involves planning, validating, and debugging hardware IP for AMD's SOC programs, including defining test plans, developing automation scripts, debugging issues across various phases (pre-silicon to production), and collaborating with cross-functional teams like DV and Emulation. Experience with digital logic design, ASIC debug, high-speed interfaces (PCIe/CXL), and scripting (Python/Ruby) is preferred. | — | 0 |
| Analog/Mixed-signal SerDes Design Engineer Analog/Mixed-signal SerDes Design Engineer at AMD, focusing on high-speed receiver and transmitter design using advanced CMOS processes. Responsibilities include circuit architecture definition, link-level simulation, and modeling of RF passive components and optical structures. | — | 0 |
| Software Development Engineer - Contract Software Development Engineer at AMD focused on developing and customizing diagnostics solutions for CPU, APU, and dGPU platforms. The role involves system-level validation, hardware-software intersection, and collaboration with cross-functional teams. While AI/ML methodologies are mentioned as a potential area for efficiency improvements, the core function of the role is not AI/ML development. | — | 0 |
| Business Administration & Operational Support Coordinator This role supports the AI group at AMD by managing procurement, operational logistics, and team events. While the role is within an AI group and mentions using AI tools, its core function is business administration and operational support, not direct AI/ML development or research. | — | 0 |
| Executive Assistant Executive Assistant role supporting the AI SW group leadership team at AMD. Responsibilities include calendar management, travel arrangements, expense reporting, interfacing with management and customers, handling inquiries, maintaining files, preparing reports, ordering supplies, and supporting financial processes. Requires strong organizational, multi-tasking, and confidentiality skills, with the ability to gather information and make decisions independently. Experience with AI-assisted solutions for data analysis and trend identification is preferred, along with a willingness to adapt to new AI technologies. | — | 0 |
| IOMMU Design Verification Engineer AMD is seeking an ASIC Design Verification Engineer to join their IOHUB Team. The role involves all aspects of IP verification, including architecture, test plans, environment development, and closure. The engineer will work on leading-edge I/O connectivity and virtualization technologies for data center and machine learning workloads. | — | 0 |
| Fullchip Floorplan Design Engineer This role is for a Fullchip Floorplan Design Engineer at AMD, focusing on translating SoC RTL into a full-chip floorplan. The engineer will define chip-level structure, manage partitioning, macro placement, integration, and collaborate with various design teams. The role requires expertise in full-chip floorplanning and physical design, using tools like Fusion Compiler/Innovus, and building automation scripts. | — | 0 |
| BIOS/Firmware Development Engineer – Memory Subsystems (DDR/LPDDR) Develop and validate BIOS and firmware features for DDR/LPDDR memory subsystems, collaborating with hardware design, validation, and system teams to ensure robust integration and troubleshoot complex system-level issues. The role involves contributing across the full product lifecycle, from early architecture and simulation through silicon bring-up and production. | — | 0 |
| Datacenter Infrastructure & Quality Excellence Leader This role focuses on driving datacenter quality excellence by applying aerospace/automotive-grade rigor to datacenter infrastructure, ensuring reliability across manufacturing, OEM/ODM quality, component qualification, and material integrity. The leader will define and enforce quality standards, lead failure analysis, and collaborate with cross-functional teams to embed design-for-quality principles. | — | 0 |
| Sr. Software Development Engineer (1-Year Contract) This role is for a Senior Software Development Engineer at AMD, focusing on developing and enhancing software for new technology and product introduction projects. The role involves validating new software features, collaborating with multiple teams, and contributing to system architecture design. While the company mentions AI and data centers as areas of focus and notes the potential use of AI in the screening process, the core responsibilities of this specific role are centered on general software engineering principles and product development, not on building or researching AI models themselves. | — | 0 |
| Design Verification Engineer (1-Year Contract) AMD is seeking a Design Verification Engineer for a 1-year contract role focused on chiplet technology. The role involves developing testbenches, writing test cases, analyzing coverage, debugging regressions, and deploying verification methodologies like UVM and Formal Verification. The position requires proficiency in Verilog, System Verilog, UVM, and ASIC design knowledge, with experience in scripting languages like Python. | — | 0 |
| Program Manager – Diagnostics Program Manager responsible for driving planning, execution, and delivery of diagnostic, debug, validation, and enablement software for complex silicon programs, with a focus on AI and data center technologies. This role coordinates globally distributed teams, manages program readiness, supports customer-facing debug activities, and ensures timely delivery of diagnostics to support silicon bring-up, validation, production readiness, and customer enablement. | — | 0 |
| Design Verification Engineer Design Verification Engineer for AMD's graphics processor IP. Responsibilities include planning, building, and executing verification tests, debugging failures, and collaborating with architects and engineers. Requires proficiency in IP level ASIC verification, UVM, Verilog, System Verilog, C/C++, and debugging firmware/RTL. | — | 0 |
| Lead Diagnostics Software Engineer, ATE Integration Lead/Principal Diagnostics Engineer to drive shift from post-silicon software validation frameworks and System-Level Tests (SLT) directly into Automated Test Equipment (ATE) and Wafer Sort environments. Design architecture, tooling, and translation methodologies to pack, convert, and stream complex software-driven GFX and compute test cases into production-grade ATE patterns. | — | 0 |
| Technical Program Manager - Windows Security (1 year contract) Technical Program Manager to lead co-engineering programs between AMD, Microsoft, and OEM partners, enabling Windows Security features across AMD platforms. This role requires strong program management skills combined with technical expertise to drive security initiatives from concept to production. | — | 0 |
| CPU Performance Architect This role focuses on analyzing and optimizing the architectural performance of AMD's PC and Gaming processors, including CPU and AI workloads. Responsibilities include performance modeling, debugging SOC performance issues, and developing performance evaluation tools. The role requires strong analytical skills, experience with computer architecture, system simulation, and performance evaluation, as well as proficiency in C/C++. | — | 0 |
| Short Term 2026 Firmware Engineering Intern/Co-Op | — | — |
| Short Term 2026 Software Engineering Intern/Co-Op | — | — |