AMD currently has 35 active AI-related job listings. The majority of these roles, 66%, are focused on serving infrastructure. Engineering is the dominant function, with 32 positions. Frequent technical tags include model_serving, inference_infra, and evals, suggesting a focus on the deployment and evaluation of AI models. In the last 30 days, AMD posted 37 new AI roles.
AMD currently has 62 active AI-related roles in our index. The most common open titles are: DC-GPU Performance Modeling Engineer (3), Data Center Engineer (2), Lead Packaging Automation Engineer (2), 3D IC and ADVANCED PACKAGING CAD ENGINEER , AI Framework Engineer. Most positions are in Engineering and Research.
AMD's active AI hiring is concentrated in: serving infrastructure (73%), agents (13%), application (6%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
AMD is hiring AI talent in: United States (27 roles), India (13 roles), China (7 roles), Canada (6 roles).
Job postings at AMD most frequently mention: GPU Computing, Computer Architecture, Compiler Design, Python, Performance Profiling.
In the past 30 days, AMD has posted 55 new AI-related roles.
| Title | Stage | AI score |
|---|---|---|
| GPU Performance Modeling & Optimization Engineer Seeking an experienced GPU Performance Modeling and Optimization Engineer to focus on pre-silicon performance modeling, feature exploration, and workload optimization, as well as post-silicon characterization, hardware-software correlation, and performance debug for upcoming SoCs/GPUs. The role involves optimizing for both traditional graphics and cutting-edge compute/AI workloads, including Transformer-based models and LLMs. | Serve | 8 |
| Lead GPU Kernel Optimization Engineer This role focuses on optimizing low-level GPU kernels for accelerating the inference and training of large machine learning models. It involves multi-GPU and multi-node optimization, performance profiling, and leveraging parallel computing techniques. The candidate will work with frameworks like PyTorch and VLLM, and requires deep expertise in CUDA, GPU programming, and C++ optimization. | Serve |
| 8 |
| Lead Engineer - AI Lead Engineer for AI at AMD, focusing on developing and deploying AI-powered tools and platforms to enhance RTL design and verification productivity within the IP organization. The role involves owning the architecture, development, integration, and adoption of AI solutions, including ML/LLM models and data pipelines, into EDA workflows and CI/CD systems. The goal is to drive process transformation and enterprise-scale automation for hardware engineering teams. | Agent | 8 |
| DC-GPU Performance Modeling Engineer This role focuses on architecting, analyzing, and optimizing high-performance GPU-centric SoCs for Machine Learning workloads. The engineer will develop performance models and methodologies to enhance performance and optimize power for next-generation data center systems, collaborating with architecture, design, and software teams. | Serve | 7 |
| DC-GPU Performance Modeling Engineer This role focuses on architecting, analyzing, and optimizing high-performance GPU-centric SoCs for Machine Learning workloads. The engineer will develop performance models and methodologies, propose solutions for performance and power optimization, and collaborate with various teams on hardware/software co-design for next-generation data center systems. Experience with ML models, distributed training, and inference is preferred. | Serve | 7 |
| Lead/Staff AI-ML Software Engineer Lead/Staff AI-ML Software Engineer at AMD responsible for developing and optimizing AI/ML specific C/C++ kernels and dataflow schedules for AMD Ryzen Processors with XDNA NPUs, focusing on mapping LLMs and Stable Diffusion networks. The role involves vector processor optimization, performance profiling, tuning, testing, and validation. | Serve | 7 |
| Sr. Staff/Principal Validation Engineer- AI/ML This role focuses on validating AI/ML workloads on GPU infrastructure and leading the adoption of Agentic AI to transform test strategy, planning, and solution development. The engineer will architect and implement AI agents to automate critical workflows across software development, testing, and release management, establishing best practices for applying AI across engineering workflows. | AgentServe | 7 |
| Staff/Principal Engineer - AI/ML & System-Level Validation Staff/Principal Engineer focused on validating ROCm software for AMD Instinct GPU platforms, covering end-to-end validation architecture, release-qualification gates, system-level testing, and compute workload characterization (including LLM training/inference). The role involves architecting test infrastructure, championing agile quality engineering, leading debug efforts, and influencing roadmaps, with a strong emphasis on using AI/ML agentic tools for engineering productivity. | ServeAgent | 7 |
| Senior ML Compiler Engineer Senior ML Compiler Engineer role focused on designing, developing, and optimizing ML compilers for AMD NPUs, debugging system-level issues, and ensuring performance improvements for ML models. | Serve | 7 |
| SoC Performance Modeling & Architecture Engineer Seeking a SoC Performance Modeling & Architecture Engineer to define, analyze, and optimize next-generation SoCs, focusing on performance-per-watt and shaping future silicon roadmaps. Responsibilities include leveraging and maintaining performance simulators, exploring architectural space, modeling hardware/software interactions, characterizing workloads (including ML/AI), evaluating NoC and memory hierarchy, and conducting PPA trade-off studies. | Serve | 5 |
| Functional Verification Engineer -SOC/IP This role focuses on the functional verification of AMD's graphics processor IP, ensuring no bugs in the final design. It involves developing UVM environments, testbenches, and utilizing AI tools to enhance test suite efficiency. The role also includes formal verification, power-aware verification, and verification of high-speed bus protocols and interconnects. | — | 5 |
| Manager- AI Transformation, CPU Diagnostics and Validation Manager for CPU Diagnostics and Validation team in Bangalore, responsible for post-silicon validation, SLT manufacturing stress content, CReST pattern development, and RMA debug. The role also involves embedding AI into the team's operating model to identify use cases, scale AI solutions, accelerate engineering productivity, improve debug efficiency, and enhance data-driven decision making. This includes defining and driving the team's AI strategy within diagnostics and validation flows, piloting and scaling AI use cases, and ensuring AI adoption across global sites. | Ship | 5 |
| Server Silicon Performance Analysis Engineer AMD is seeking a Server Performance Analysis Engineer in Bangalore, India, to analyze and optimize the performance of EPYC based servers for cloud, enterprise, HPC, and AI/ML workloads. The role involves characterizing workloads, analyzing performance data, identifying bottlenecks, and working with software teams on optimizations. Requires strong computer architecture expertise and experience with performance profiling tools. | — | 5 |
| ML SOFTWARE DEVELOPMENT ENGINEER This role focuses on building and verifying ML-based software, specifically improving training efficiency and creating test cases for ML compilers. The engineer will work with C++, Python, and GPU/CPU communication, contributing to the AMD AI platform. | Data | 5 |
| DC-GPU Performance Modeling Engineer This role focuses on architecting, analyzing, and optimizing high-performance GPU-centric SoCs for Machine Learning workloads. The engineer will develop performance models and methodologies to enhance performance and optimize power for next-generation data center systems, collaborating with architecture, design, and software teams. | Serve | 5 |
| Lead Power and Performance Attainment Engineer Lead Power and Performance Attainment Engineer at AMD, focusing on AI/ML/HPC GPUs. The role involves owning the Perf@Power attainment of Instinct accelerators, including pre-Si modeling, post-Si correlation, workload analysis, target setting, and reporting. Requires cross-functional leadership and mentorship. | — | 5 |
| Sr. Software System Designer This role focuses on designing and building system-level profiling and performance analysis tools for AMD platforms, covering CPU, GPU, and system-level aspects. The goal is to enable customers and internal teams to analyze and optimize application performance at scale using tools like AMD uProf. The role involves developing data collection frameworks, low-overhead profiling infrastructure, and advanced analysis techniques, with a drive towards AI/ML-assisted performance insights. | — | 5 |
| Embedded Linux Power and Performance Engineer Embedded Linux Power and Performance Engineer at AMD, focusing on benchmarking, profiling, and bottleneck analysis of AMD's system PnP stack in Linux and virtualized environments, with an emphasis on competitive benchmarking against other SoCs for robotics, automotive, and industrial segments. Requires deep Linux internals, real-time systems, performance profiling tools, and x86 SoC architecture understanding. | — | 5 |
| Lead Software System Design Eng - System PNP Lead Software System Design Engineer focused on System Power & Performance (PnP) for AMD's SoCs, with a dual focus on benchmarking/profiling in Linux and virtualized environments, and driving competitive benchmarking across market segments for Robotics, automotive, and industrial applications. | — | 5 |
| RTL Design Engineer AMD is seeking an RTL Design Engineer to join their Silicon IP solutions & SOC group. The role involves technical leadership across the design hierarchy, from architecture to productization, for complex IP solutions. Responsibilities include defining micro-architecture, evaluating design plans, RTL design, IP integration, documentation, and mentoring junior engineers. Experience with Verilog RTL design, VCS simulation, and scripting is preferred, along with a strong track record in developing leading-edge IP solutions like PCIe, DMAs, NVMe, or networking IPs. | — | 0 |
| CPU/Cores Post‑Silicon Validation (Virtualization) This role is for a Staff Engineer focused on post-silicon validation of CPU cores using virtualization. The engineer will stress core microarchitecture, identify silicon issues, and collaborate with design teams for root-cause analysis and resolution. The role treats virtualization as a primary validation vector to uncover real-world core issues under production-like stress. | — | 0 |
| Lead Engineer – Systems & Performance Engineering This role is for a Lead Engineer in Systems & Performance Engineering at AMD, focusing on improving products, exploring opportunities, and providing consultative direction. The role involves performance, automation, and development, with a need for strong programming skills in Python, C, or C++ and experience with system benchmarks. While the company emphasizes AI, this specific role is not directly building or researching AI models. | — | 0 |
| Lead Architect – Programmable Clock Architecture Lead Architect for Programmable Clock Architecture at AMD in Hyderabad, India. This role involves leading a team to develop clocking solutions for Adaptive-Embedded Computing products, collaborating with global teams, and addressing complex SOC clocking challenges. Responsibilities include developing clock distribution methodologies, analyzing clock timing, and collaborating with various IP teams. Requires deep understanding of system-level clocking, leadership skills, and expertise in STA and EDA tools. | — | 0 |
| Systems Integration and Debug Lead This role is for a Systems Integration and Debug Lead in AMD's Datacenter Platform Engineering Group. The primary focus is on system-level debug, ensuring availability and uptime of data center systems, and root-causing complex hardware/firmware issues. The role involves leadership in guiding junior engineers and collaborating with various teams to resolve problems. While the company mentions AI and data centers, the core responsibilities of this specific role are centered around hardware and system integration/debug, not AI model development or deployment. | — | 0 |
| Senior Lead IP Design Engineer This role is for a Senior Lead IP Design Engineer at AMD, focusing on micro-architecting, designing, and delivering data fabric IP RTL components. The engineer will manage power, performance, and area requirements, working with architecture, verification, and physical design teams to ensure silicon success. The role involves defining features, digital design implementation, RTL coding, leading design domains, and post-silicon support. Experience in fabric/transport architecture, coherency, and memory/cache design is preferred. | — | 0 |
| Lead Software Development Eng. Lead Software Development Engineer for AMD's Business Enterprise Applications team, focusing on IT Global Operations & Supply Chain. The role involves developing product security, analyzing system performance impacting AMD product lifecycle, and improving generated code quality. Requires strong software development, debugging, and communication skills, with experience in Java, .Net, C++, Python, SQL, UNIX/Linux, and security principles. | — | 0 |
| Staff Systems Administrator Staff Systems Administrator role at AMD in Bangalore, India, focusing on leading onsite IT operations and end-user support, including AI adoption. Responsibilities include technical support for hardware and software, team leadership, IT project management, and collaboration with other IT teams. Requires strong troubleshooting, multi-platform expertise including AI tools, and people leadership. | — | 0 |
| Silicon Design Engineering Leader This role is for a Silicon Design Engineering Leader at AMD, focusing on driving SOC design execution, tape-outs, and people management. While the company is involved in AI and data centers, and may use AI for screening, the core responsibilities of this role are in traditional silicon design and engineering leadership, not direct AI/ML model development or deployment. | — | 0 |
| Design Verification Engineer Design Verification Engineer at AMD in Bangalore, India, focusing on verifying new and existing features for AMD's graphics processor IP. Responsibilities include collaborating with architects and engineers, building verification tests, debugging failures, and analyzing test plans. Requires 8+ years of ASIC Design Verification experience, strong computer architecture knowledge, and proficiency in C++ and assembly language. | — | 0 |
| Senior RTL Design Lead - CPU Team This role is for a Senior RTL Design Lead focused on CPU team at AMD. The responsibilities include RTL design of high performance x86-core ISA features, clock/reset/power features of processor, IP Integration, sub-system level design, architecting and designing power management features, cache, coherency, and design optimization for power efficiency. The role also involves leading the design team, mentoring junior members, and representing AMD to the technical community. The preferred experience includes 11+ years in Digital IP/ASIC design, Verilog RTL development, and familiarity with the full IP design cycle. | — | 0 |
| Principal Cache RTL Design - CPU Team This Principal Cache RTL Design role at AMD focuses on the RTL design of high-performance x86-core ISA features, power management, cache, and coherency. It involves IP integration, sub-system level design, and optimization for power efficiency. The role requires extensive experience in digital IP/ASIC design, Verilog RTL development, and familiarity with the full IP design cycle, including verification, synthesis, and post-silicon validation. Leadership and mentoring of junior engineers are also key responsibilities. | — | 0 |
| Senior Synthesis PD Engineer This role is for a Senior Synthesis PD Engineer at AMD, focusing on the physical design and synthesis of complex IPs for computing experiences, including AI and data centers. The engineer will work closely with architecture, IP design, and product engineering teams to optimize PPA (Power, Performance, Area) for these IPs. Responsibilities include synthesis, constraint development, and physical-aware activities like floorplanning and placement. The role requires a strong understanding of the backend design cycle and experience in synthesis/PD/constraints. | — | 0 |
| Lead verification Engineer - high speed protocol Lead Verification Engineer for Data Center Networking IPs and systems, focusing on high-speed protocols like PCIe, Ethernet, CXL, RoCE/NVMe-oF. Responsibilities include architecting testbenches, developing verification plans, writing SystemVerilog/UVM, and using scripting languages for automation. The role also involves collaboration, leadership, and mentoring. | — | 0 |
| Synthesis STA Lead This role is for a Senior Member of Technical Staff (SMTS) Silicon Design Engineer in the NBIO IP Physical Aware group at AMD. The primary responsibilities involve synthesis, Static Timing Analysis (STA), constraint development, and physical-aware activities like floorplanning and placement. The role also includes leading junior team members. While the company mentions AI and data centers, the core responsibilities of this specific role are in silicon design and verification, not AI/ML model development or deployment. | — | 0 |
| Senior Design Verification Engineer Senior Design Verification Engineer role focused on planning, building, and executing verification of wired networking IP features. Responsibilities include collaborating with architects and engineers, building test plans, writing and debugging directed and random verification tests, and reviewing coverage metrics. Requires proficiency in IP level ASIC verification, UVM, and SystemVerilog. | — | 0 |
| Senior Physical Verification Engineer (Full-Chip/SoC) AMD is seeking a Senior Physical Verification Engineer to join their Server SOC PD group. This role will be responsible for full-chip Physical Verification signoff (DRC/LVS/ERC/DFM/Antenna/PERC) and methodology ownership on advanced nodes, partnering cross-functionally to ensure tapeout-quality delivery. The engineer will work with cutting-edge designs and solve critical physical verification issues. | — | 0 |
| IP/SOC Verification with power management Engineer This role is for an IP/SOC Verification Engineer with a focus on power management features for Server SOCs. Responsibilities include developing test plans, creating coverage models, building UVM testbenches, verifying power management interactions, debugging issues, and ensuring functional coverage closure. The role also involves participating in architecture reviews and supporting post-silicon validation. | — | 0 |
| Commercial Sales Account Manager This role is for a Sr Commercial Sales Account Manager responsible for building AMD's commercial systems channel business, focusing on PCs, servers, and professional graphics. The role involves business development with partners, evangelizing AMD technology, building sales programs, enabling sales teams, and managing executive relationships. | — | 0 |
| DDR Lead Verification Engineer This role is for a Lead Verification Engineer at AMD, focusing on planning, building, and executing verification for Memory Controller IP. It involves collaborating with architects and hardware engineers, building test plans, writing and debugging verification tests, and ensuring coverage requirements are met. Experience with memory controllers and ASIC verification is preferred. | — | 0 |
| Senior Software Development Engineer - C++ This role is for a Senior Software Development Engineer focused on C++ development for AMD's Vivado Design Suite, an IDE for FPGA and adaptive SoC design. The responsibilities include algorithm development, feature delivery, debugging, and mentoring engineers. While the company mentions AI and its use in screening, the core function of this role is not AI/ML development but rather software engineering for hardware design tools. | — | 0 |
| Analog Layout Engineer Analog Layout Engineer role at AMD, focusing on full custom layouts in cutting-edge technology nodes. Responsibilities include handling sub cells, chip-level integration, physical verification, and electrical closure. Requires expertise in custom layout, digital, analog, and mixed-signal design, with a strong understanding of electrical parameters and reliability concepts. The role is primarily an individual contributor with leadership potential. | — | 0 |
| SOC / IP Verification Engineer This role is for a SOC/IP Verification Engineer at AMD, focusing on planning, building, and executing verification for graphics processor IP. The responsibilities include collaborating with architects and engineers, building test plans, writing and debugging verification tests, and reviewing coverage metrics. The role requires proficiency in IP level ASIC verification, debugging firmware and RTL, and experience with UVM testbenches, Verilog, System Verilog, C, and C++. | — | 0 |
| Emulation Engineer Emulation Engineer in AMD’s Server SoC team responsible for validating next-generation server-class SoCs using advanced emulation platforms, ensuring silicon is bug-free, high-performance, and server-grade reliable. | — | 0 |
| RTL Design Lead - IP Design This role is for an RTL Design Lead at AMD, focusing on front-end design and integration of IP and subsystems for computing and graphics. It involves leading a team, ensuring first-pass silicon success, and collaborating with various engineering teams. The role requires expertise in RTL design, quality checks, and understanding of SoC design flows, power management, and embedded processors. | — | 0 |
| CAD Design Engineer CAD Engineer at AMD responsible for developing and supporting next-generation synthesis, place and route (PnR) flows for advanced technology nodes (3nm & 2nm). This role involves automation of PnR flows, collaboration with EDA vendors, and supporting global design teams to achieve optimal power, performance, and area (PPA) for SOCs. | — | 0 |
| CAD Design Engineer CAD Engineer at AMD responsible for developing and supporting next-generation synthesis, place and route (PnR) flows for advanced technology nodes (3nm & 2nm). This role involves automation of PnR flows, collaboration with EDA vendors, and supporting global design teams to achieve optimal power, performance, and area (PPA) for SOCs. | — | 0 |
| Lead Software Development Engineer – C++ / EDA Software Development Engineer role focused on improving the performance of the Vivado Design Suite, an IDE for FPGA and adaptive SoC hardware design. The role involves hands-on design and implementation of core algorithms, data models, and modules, with end-to-end feature delivery responsibility. It also includes mentoring, code reviews, debugging, and research into more efficient methods. While the company mentions AI and its own AI policy, the core responsibilities are in software engineering for hardware design tools, not direct AI/ML model development. | — | 0 |
| DFX Design Lead This role is for a DFX Design Lead at AMD, focusing on the design and implementation of Design for Testability (DFx) features for next-generation silicon innovation. The engineer will own/lead DFx architecture, implement features like SCAN, ATPG, MBIST, and BSCAN, and collaborate with various design and verification teams to accelerate defect identification and ensure correct DFT implementation. The role also involves post-silicon support and requires strong scripting, debugging, and communication skills. | — | 0 |
| Physical Design / PnR Lead This role is for a Physical Design / PnR Lead at AMD, focusing on the implementation and convergence of complex ASIC and APU/dGPU designs for various applications including AI inference. The lead will manage a team, drive backend activities from RTL to GDS, and collaborate with cross-functional teams to achieve PPA optimization and first-pass silicon success. Experience with physical design flows, timing closure, and verification is required. | — | 0 |
| Phy- V Lead This role is for a PHY-V Lead at AMD, responsible for physical verification sign-off, full-chip integration, and packaging interface planning for advanced SoC programs. The lead will drive DRC/LVS clean tapeouts, integration quality, and sign-off predictability, requiring expertise in physical verification, top-level integration, and advanced packaging alignment. The role involves leading cross-functional execution across PD, Analog, and Packaging teams, with a focus on quality, manufacturability, and schedule predictability in high-pressure tapeout environments. | — | 0 |
