NVIDIA currently has 496 active AI-related job listings. The majority of these roles, 52%, are focused on serving infrastructure, with agents representing another significant segment at 23%. Engineering is the dominant function, with 441 positions. The United States leads hiring geographies with 287 roles, followed by China with 64. Frequent tech tags include model_serving, inference_infra, and agent_orchestration, suggesting a focus on deployment and management of AI models. Over the last 30 days, NVIDIA posted 214 new AI roles, a 27% decrease compared to the previous 30-day period.
Currently tracking 440 active AI roles, down 50% versus the prior 4 weeks. Primary focus: Serve · Engineering. Salary range $100k–$575k (avg $262k).
NVIDIA currently has 487 active AI-related roles in our index. The most common open titles are: Deep Learning Performance Architect (4), Senior Deep Learning Performance Architect (4), AI Research Scientist (3), Developer Technology Engineer - AI (3), Manager, Deep Learning Algorithms (3). Most positions are in Engineering and Research.
NVIDIA's active AI hiring is concentrated in: serving infrastructure (54%), agents (21%), application (8%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
NVIDIA is hiring AI talent in: United States (286 roles), China (59 roles), Israel (50 roles), Germany (21 roles).
Job postings at NVIDIA most frequently reference: model serving, inference infra, agent orchestration, llm observability, multimodal.
In the past 30 days, NVIDIA has posted 110 new AI-related roles. That is a -50% change versus the prior 30 days (218 → 110).
| Title | Stage | AI score |
|---|---|---|
| Senior Solution Architect, Networking Solutions Labs NVIDIA is seeking a Senior Solution Architect for their Networking Solutions Labs in Israel. The role involves designing and implementing complex data center solutions, including architecture, deployment, performance analysis, and ROI. The candidate will work with software developers and architects to research new technologies and will be responsible for end-to-end solution implementation, automation, documentation, and supporting business units with POCs and consulting. Experience with data center technologies like OS, virtualization, containers, storage, networking, and IaC tools is required, along with expertise in Linux, Kubernetes, Docker, and QEMU/KVM. Experience with distributed systems, big data frameworks, and AI/ML frameworks is a plus. | — | 0 |
| Firmware SerDes Verification Engineer NVIDIA is seeking a Firmware Verification Engineer to join their FW SerDes verification Group. The role involves owning the delivery and verification of Networking features, defining and maintaining verification infrastructure and regression test suites, and working with continuous integration systems. The ideal candidate will have 1+ year of relevant experience, strong programming skills in C, C++, and Python, and experience with verification, automation, Linux, Git, and CI methodologies. |
| — |
| 0 |
| Senior ASIC Verification Engineer - Networking Chip Design Senior ASIC Verification Engineer role focused on leading the delivery of next-generation Switch Silicon chips, involving fullchip activities, integration, and verification with a strategic leadership component. | — | 0 |
| Manager, Firmware - NVLink Manager for pre-silicon firmware development for NVLink Switches & GPU Networking, leading a team, driving planning and execution from architecture to validation, and evolving development processes. | — | 0 |
| Senior ASIC Engineer, Power Integrity NVIDIA is seeking a Senior ASIC Engineer with expertise in Power Integrity, Modeling and Simulation to join their Circuits Solutions Group. The role involves participating in processor design, building models of analog and digital circuits, and performing simulations to ensure design reliability, performance, and stability. The ideal candidate will have a BSEE or equivalent with 5+ years of experience, proficiency with EDA and simulation tools, and experience modeling and simulating circuits. Experience with power delivery networks, other industry tools, control systems, and scripting languages are considered advantageous. | — | 0 |
| Senior Chip Design Engineer NVIDIA is seeking a Senior Chip Design Engineer to design and verify high-speed communication devices, focusing on cutting-edge PCIe technology. The role involves daily work across micro-architecture, firmware, production, and verification, with a strong emphasis on performance and challenging constraints. | — | 0 |
| Software Formal Verification Engineer Software Formal Verification Engineer at NVIDIA focusing on using and developing formal verification tools and methods to mathematically prove the correctness of complex logic problems in software and hardware, supporting NVIDIA's core technologies. | — | 0 |
| Senior Firmware Engineer - NVLink Switch Senior Firmware Engineer for NVLink Switch at NVIDIA, focusing on designing and implementing firmware features for next-generation data center products that support the AI revolution. The role involves collaboration with architecture and software teams, pre and post-silicon development, and understanding system debugging and networking technology. | — | 0 |
| Manager, Networking Firmware Engineering Manager for a Networking Firmware Engineering team at NVIDIA, focusing on developing cutting-edge networking features for AI, cloud, HPC, and storage. The role involves leading a team, providing technical guidance, and hands-on development of NVIDIA NIC firmware. | — | 0 |
| BSP and BMC Verification Software Engineer Software Verification Engineer for NVIDIA's Networking OS Software Verification Group, focusing on Board Support Package (BSP) and Board Management Controller (BMC) Switch Software Development. Responsibilities include designing, developing, and maintaining APIs, tools, and libraries for HW-management drivers and BMC software verification infrastructure, as well as designing, developing, and executing test automation for release features. Requires 3+ years of experience as a Software Engineer, strong object-oriented programming skills, and experience with Linux. | — | 0 |
| Senior Software Engineer Senior Software Engineer role focused on firmware verification for NVIDIA's InfiniBand Switch and NVLink products. Responsibilities include developing verification processes, designing and implementing features in C++ and Python, and collaborating with cross-functional teams in pre and post-silicon environments. Requires strong analytical and debugging skills, with experience in embedded software development. | — | 0 |
| Senior Firmware Micro-Architect Senior Firmware Micro-Architect role at NVIDIA focusing on defining Firmware architecture for next-generation Switch products, working closely with chip design teams. Requires 8+ years of experience, C/C++/Python programming, and L2 Networking knowledge. | — | 0 |
| Software Engineer, Cloud Platforms Software Engineer role focused on designing, building, and deploying high-performance, scalable open-source cloud platforms using technologies like Kubernetes, with a focus on network and storage acceleration. Requires strong software development skills in C/Python/Golang, deep understanding of network protocols, virtualization, and containers. | — | 0 |
| Senior Process Engineer NVIDIA is seeking a Senior SoIC Assembly Engineer to lead the development and deployment of SoIC assembly tools and processes for their next-generation products. This role involves defining tool architecture, developing stable processes, ensuring quality and reliability, and collaborating with internal and external teams to scale up manufacturing. The ideal candidate will have extensive experience in SoIC and CoWoS, strong statistical analysis skills, and a background in relevant engineering or science fields. | — | 0 |
| Senior Physical Design Engineer Senior Physical Design Engineer responsible for the physical design and implementation of GPUs and other ASICs, including floorplan, power/clock distribution, assembly, P&R, and timing closure. Requires extensive experience with VLSI physical design on advanced process nodes and proficiency with relevant CAD tools. | — | 0 |
| Senior Physical Design Engineer NVIDIA is seeking a Senior Physical Design Engineer to be responsible for the physical design and implementation of GPUs and other ASICs. This role involves establishing design methodologies, chip floorplan, power/clock distribution, assembly, P&R, and timing closure. The engineer will also craft designs for static timing analysis, power/noise analysis, and back-end verification, working with advanced process nodes (5nm, 4nm, 3nm) and various CAD tools. | — | 0 |
| Physical Design Backend STA Engineer NVIDIA is seeking an experienced Static Timing Analysis (STA) Physical Design Engineer for their Networking team in Israel. The role involves performing advanced STA, running Prime Time, debugging timing paths, and collaborating with cross-functional teams to ensure chip convergence and quality approval from pre-layout to signoff. The ideal candidate will have 2-3 years of STA experience and a B.Sc. in Electrical or Computer Engineering. | — | 0 |
| Senior HPC Performance Engineer Senior HPC Performance Engineer at NVIDIA to analyze HPC applications on various systems (CPUs, GPUs) and identify optimization opportunities for compiler and application engineering teams. Requires strong programming, parallel architecture, and performance analysis skills. | — | 0 |
| System Software Engineer - GPU and SOC System Software Engineer focused on GPU and SOC kernel drivers, platform performance, power savings, and robustness for NVIDIA's production hardware. Requires strong C/C++ and OS fundamentals, with experience in system-level debugging and computer architecture. | — | 0 |
| Senior HPC Performance Engineer Senior HPC Performance Engineer at NVIDIA to analyze and optimize High Performance Computing (HPC) applications on HPC servers and systems, focusing on performance characteristics and identifying optimization opportunities for compiler and application engineering teams. This involves working with applications ranging from benchmarks to large-scale distributed systems with heterogeneous compute nodes (CPUs, GPUs, many-core processors). | — | 0 |
| Senior Software Engineer, AVOS, DRIVE OS and BSP - Automotive Senior Software Engineer role focused on supporting NVIDIA's autonomous driving software stack (AVOS, DRIVE OS) for automotive customers. Requires deep understanding of BSP, operating systems, device drivers, and strong software development skills for ECU bring-up, profiling, and debugging. Involves close customer interaction and adaptation of software to customer hardware platforms. | — | 0 |
| Manager, Tegra Software Chip Manager for Tegra Software Chip at NVIDIA, responsible for leading and executing the entire silicon life cycle for various products. This role involves technical project management, coordinating software planning and execution, managing schedules, and interfacing with multiple teams and product groups. | — | 0 |
| Senior System Software Engineer, Drive AV Architect - Automotive Senior Software Engineer for NVIDIA's DRIVE OS & NDAS software stack, focusing on OEM alignment, SW architecture for driving functions (L2++), and customer support in the automotive domain. Requires strong C/C++ skills, embedded systems experience, and knowledge of ADAS/functional safety. | — | 0 |
| Senior Embedded Software Engineer - AV Platform Senior Embedded Software Engineer for NVIDIA's Autonomous Vehicles Platform Team. Focuses on hardware platform and sensor integration (cameras, radars, lidars), software design, development, and bring-up for next-generation autonomous vehicles. Involves debugging complex issues across software and hardware domains within environments like Hypervisor, Linux, and QNX RTOS. | — | 0 |
| Senior SRAM Circuit Design Engineer Senior SRAM Circuit Design Engineer at NVIDIA, focusing on the design, verification, and characterization of next-generation SRAM for advanced processor designs in cutting-edge technologies. Responsibilities include transistor-level circuit design, optimization for power/timing/area/yield, layout floorplanning, timing characterization, and verification using Verilog/VHDL. Requires MS in Electrical/Computer Engineering or equivalent, 6+ years of experience, and strong background in deep submicron processes, SRAM design, and ASIC flows. | — | 0 |
| Senior ASIC Physical Design Engineer, Netlisting This role is for a Senior ASIC Physical Design Engineer focused on netlisting aspects of high-frequency and low-power CPUs, GPUs, and SoCs. Responsibilities include equivalence checking, asynchronous checking, logic synthesis, and timing convergence. The role requires significant experience in ASIC design flows and EDA tools, with proficiency in scripting languages. While NVIDIA is a leader in AI, this specific role is in hardware design for computing infrastructure, not direct AI model development or deployment. | — | 0 |
| Software Embedded Engineer, DOCA Seeking an embedded Software Engineer with C/C++ and Linux experience to design and develop high-performance networking solutions based on NVIDIA's Bluefield DPU hardware. The role involves close collaboration with global HW, FW, and SW teams, customer engagement, and taking ownership of key DPU software components. | — | 0 |
| STA Engineer NVIDIA is seeking an STA Engineer with 2-3 years of experience to join their Networking DFT team. The role involves executing Static Timing Analysis (STA) for high-speed communication devices, from RTL driven constraints to STA sign-off. Responsibilities include daily work on constraints, environment, model generation, and timing ECO generation. Experience with physical design flows, DFT flows, and EDA tools is preferred. | — | 0 |
| Senior High Speed Electro Optics Engineer NVIDIA is seeking a Senior High Speed Electro Optics Engineer to develop, test, and characterize Silicon Photonics based high-speed optical communication devices for data centers. The role involves hands-on experimental lab work, including the bring-up of new switches and transceivers, and characterization of electro-optical components and subsystems. | — | 0 |
| Senior Chip Architect NVIDIA is seeking a Senior Chip Architect to define the Network Adapter chip architecture from market requirements through design and all product life cycles. This role involves collaboration with various engineering teams, research and analysis for future architectures, and crafting product design specifications. | — | 0 |
| Senior Mask Design Engineer - Hardware Senior Mask Design Engineer for high-speed mixed-signal circuit designs using Cadence tools in sub-micron CMOS technologies. Responsibilities include physical layout, cross-functional collaboration, and verification against design rules and schematics. Requires BSEE or equivalent, 7+ years of experience, deep understanding of analog circuit layout, proficiency with Cadence virtuoso, verification tools (Dracula, Hercules, Calibre), scripting languages (perl, python, skill), and DRC/LVS flows. | — | 0 |
| Senior ASIC Verification engineer Senior ASIC Verification Engineer for NVIDIA's next-generation GPU and SOC IPs, focusing on High-Speed Test Access Mechanism (TAM) verification for various testing stages and silicon lifecycle management. | — | 0 |
| Senior Chip Design Verification Engineer Senior Chip Design Verification Engineer at NVIDIA, focusing on developing and verifying high-speed communication devices and networking/GPU networking chips. Requires 5+ years of ASIC verification experience. | — | 0 |
| Software Security Researcher NVIDIA is seeking a Senior Security Researcher to enhance the security posture of its networking products. The role involves offensive security research, threat modeling, defining security standards, and providing security architecture recommendations. The ideal candidate will have a strong background in security research, applied cryptography, and common attack vectors, with the ability to work independently and collaboratively. | — | 0 |
| Senior Firmware PHY Verification Engineer Senior Firmware PHY Verification Engineer for NVIDIA's FW PHY verification group, focusing on networking features and verification infrastructure for NVIDIA products. | — | 0 |
| Senior DFT Verification Engineer NVIDIA is seeking a Senior Chip Design Verification Engineer to develop and verify next-generation DFT technologies for their Switches, Nic, and SoC product lines. The role involves creating verification environments, test plans, and collaborating with cross-functional teams to ensure design correctness. | — | 0 |
| System Design Power Validation Engineer NVIDIA is seeking a Power Validation Engineer in Taipei to perform board/system power qualification and function testing for various NVIDIA platforms including Data Center, Graphics, ARM, and Autonomous Driving. The role involves DC-DC power signal measurement, power testing, debugging, compensation tuning, and system functionality testing, with collaboration with hardware design and mechanical/thermal engineers. | — | 0 |
| Senior Software Engineer – Distributed Test Platform Senior Software Engineer role focused on building and improving distributed test platforms and microservices for validating chip designs at NVIDIA. The role involves enhancing system performance, reliability, and throughput, and developing interfaces for engineering users. Requires strong software engineering skills in Python, OOP, distributed systems, and Kubernetes. | — | 0 |
| Senior I/O Specifications Architect This role focuses on architecting and developing chip requirements for industry-standard I/O interfaces (PCIe, CXL, UCIe), engaging with standards bodies, and collaborating with internal teams to define interconnect strategies for future AI and graphics systems. It requires deep knowledge of I/O technologies and system architecture. | — | 0 |
| Senior Mixed Signal Design Engineer NVIDIA is seeking a Senior Mixed Signal Design Engineer to lead the design of CMOS high-speed interface circuits and mixed-signal circuits, including hands-on experience in silicon validation, debugging, characterization, and bring-up. The role involves designing high-speed transceivers and PLLs, simulating and verifying mixed-signal circuits, and working with multi-functional teams through implementation and productization. | — | 0 |
| Senior System Software Engineer, OpenBMC Senior System Software Engineer role at NVIDIA focusing on OpenBMC firmware development for server platforms. Responsibilities include implementing Unified Firmware architecture, system management software, BMC firmware bring-up, performance analysis, and ensuring code quality and security. Requires extensive experience in BMC firmware, system management, and programming languages like C/C++, Bash, Python, and Go. | — | 0 |
| Senior System Software Engineer, CUDA - Tegra NVIDIA is seeking an experienced software engineer to contribute to the CUDA driver and runtime, a core component of NVIDIA's CUDA parallel computing platform. The role involves building and maintaining features, contributing to the full SDLC, writing production-level code, and collaborating with hardware teams on next-generation GPUs. Requires a BS/MS in CS or equivalent experience, strong C/C++ skills, OS fundamentals, and debugging abilities. | — | 0 |
| Senior Verification Engineer - HSIO Cluster and SOC Senior Verification Engineer role focused on HSIO IP cluster and SOC level verification for automotive chips. Responsibilities include developing verification components, architecting testbenches, defining test plans, building verification infrastructure, and ensuring verification closure for high-speed I/O IPs like USB, UFS, Ethernet, and MACSEC. Requires experience with SV, UVM, and high-speed IO verification. | — | 0 |
| System Software Engineer, GPU Development Tools System Software Engineer role at NVIDIA focused on developing core infrastructure for modeling, analyzing, and debugging large-scale GPU development. The role involves working at the interface of software drivers and GPU simulation, enabling functional and performance testing, and improving daily workflows for chip modelers and designers. Requires strong C++ programming and understanding of software driver stacks. | — | 0 |
| Senior Post Silicon HSIO Bringup Lead NVIDIA is seeking a Senior Post Silicon HSIO Bringup Lead to own the post-silicon validation and support new hardware bring-up for HSIO interfaces (PCIe, CXL, NVLink) on GPU accelerated computing platforms. The role involves test plan development, automation, bug resolution, and influencing pre-silicon methodologies. Requires extensive experience in HSIO protocols, lab instruments, and post-silicon bring-up. | — | 0 |
| Senior Verification Engineer - HSIO Cluster and SOC Senior Verification Engineer responsible for HSIO IP's cluster and SOCV level verification, developing verification components and APIs for complex rapid data transfer IO IPs and sub-systems. This includes architecting testbenches, defining test plans, building verification infrastructure, implementing functional coverage, and ensuring SOC level verification closure. | — | 0 |
| Senior Verification Engineer - ARM Fabric Unit Level Senior Verification Engineer for ARM Fabric Unit Level at NVIDIA, focusing on developing UVM-based verification test benches and methodologies for high-performance automotive chips. Responsibilities include architecting testbenches, defining test plans, implementing functional coverage, and collaborating with design and post-silicon teams. | — | 0 |
| Senior Verification Engineer - HSIO Unit Level Senior Verification Engineer at NVIDIA focusing on HSIO IP unit level verification for automotive chips. Responsibilities include developing UVM-based test benches, defining test plans, building verification components, implementing functional coverage, and coordinating verification closure. Requires BTech/MTech with 4+ years of experience in High Speed IO verification, SV, and UVM. Experience with AI tools for code development is a plus. | — | 0 |
| Senior ASIC Design Engineer, High Speed IO NVIDIA is seeking a Senior ASIC Design Engineer for High Speed IO IPs in Automotive chips. The role involves understanding protocols, making architectural trade-offs, implementing RTL, driving verification, closing timing, and supporting silicon validation for UFS/Ethernet/PCIE/USB IPs. | — | 0 |
| Senior Verification Engineer - Audio and Auxiliary CPU Sub-Systems Senior Verification Engineer role focused on Audio and Auxiliary CPU Sub-Systems for automotive chips. Responsibilities include developing UVM-based verification test benches, defining test plans, building verification components, implementing functional coverage, and collaborating with cross-functional teams. Requires experience in verification closure of complex units/sub-systems/SOCs, RISCV/ARM/DSP core experience, and SV/UVM methodologies. | — | 0 |