Tenstorrent

Tenstorrent is seeking a SoC Chiplet Design Lead to drive the design and development of advanced System-on-Chip (SoC) architectures targeting AI, HPC, and automotive markets. This role involves leading cross-functional teams through the entire SoC lifecycle, from concept to tape-out, focusing on performance, scalability, and efficiency. The ideal candidate will have deep expertise in SoC and chiplet design, RTL design, and digital architecture, with proven experience in leading end-to-end SoC development and verification.

Tenstorrent is seeking a GCC Compiler Engineer to design, develop, and optimize compilers for next-generation RISC-V and AI compute architectures. The role involves working across hardware and software teams to improve performance and integration of custom toolchains for both traditional compute and machine learning workloads.

Senior Design Verification Engineer for AI hardware, focusing on custom AI compute cores, RISC-V CPUs, and chiplet-based architectures. The role involves validating compute IP and subsystems, building scalable DV infrastructure, and contributing to verification environments, agents, and scoreboards using SystemVerilog and Python. The position requires experience in modern verification methodologies, scripting, and coverage-driven verification, with a focus on AI-native compute architectures.

Tenstorrent is seeking a Staff, Ethernet Validation Engineer to work on cutting-edge AI technology, focusing on validating Ethernet IP in silicon. The role involves building robust validation infrastructure for performance, interoperability, and reliability, and collaborating with hardware and software teams on complex networking challenges.

This role focuses on formal verification of CPUs and chiplets, applying advanced methods to ensure rigorous quality standards. While the company works on AI technology and the role involves applying AI techniques to improve verification processes, the core craft of the engineer is formal verification of hardware, not direct AI/ML model development.

Software Engineer role focused on building and maintaining system management tools (tt-smi, utilities) and enhancing OpenBMC for Tenstorrent's AI hardware platforms. The role involves working at the boundary of firmware/BMC and host software, requiring experience in low-level software development, C/C++, Python, and Linux environments. Responsibilities include developing hardware-facing functionality like telemetry, health reporting, and controls, as well as supporting Linux bring-up and test infrastructure.

Staff Firmware Engineer to develop system management firmware for AI hardware platforms, focusing on embedded controllers, bootloaders, and low-level system software integration. Requires strong C/C++ and embedded systems experience, with collaboration across hardware and software teams.

Tenstorrent is seeking an Advanced Packaging Process Engineer with experience in 2.5D and 3D chiplet packaging to drive advanced package technology and reliability for next-generation AI/ML products. The role involves close partnership with foundries and OSATs, owning technology implementation, acting as a technical interface, and collaborating with design and reliability teams.

Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes. This role involves leading physical verification closure, debugging issues, and collaborating with various teams to achieve successful tapeouts.

Tenstorrent is seeking an experienced EDA/PDK CAD Engineer to build and maintain design infrastructure for AI silicon innovation. The role involves installing and optimizing PDKs, managing EDA tool flows, and collaborating with various engineering teams to improve design efficiency. Responsibilities include troubleshooting CAD issues and supporting physical verification and simulation flows.

Tenstorrent is seeking a Sr. Staff Engineer, Driver to focus on the user-mode driver and interface layer for their AI hardware. This role involves designing and evolving high-performance APIs, defining driver interfaces, collaborating with kernel and hardware teams, driving performance engineering, and supporting external integrations, including in safety-critical use cases.

This role is for a Mixed-Signal IC Layout Design Engineer at Tenstorrent, an AI technology company. The engineer will be responsible for full-custom physical layout of analog and mixed-signal integrated circuits, ensuring they meet performance, power, area, and reliability targets in advanced FinFET processes. The role involves developing floorplans, placement, and routing, applying best-known layout practices, and supporting post-layout extraction and simulation. Experience with Synopsys Custom Compiler/Cadence Virtuoso and Synopsys ICV/Siemens Calibre is required. The company emphasizes collaboration, curiosity, and solving hard problems.

Tenstorrent is seeking a System IP & Site Lead in India to manage the technical direction of their System IP portfolio and oversee the operational success, cultural health, and strategic growth of their India engineering design center. This role requires deep technical expertise in SoC architecture and System IP development, strategic business acumen, and proven experience in managing large-scale cross-functional engineering teams and engineering sites.

Staff Engineer focused on CPU core-level verification for out-of-order RISC-V CPUs, involving RTL, UVM, C/C++ stimulus development, debug, and collaboration across design and validation teams.

Tenstorrent is seeking a Staff Digital Design Engineer to define, build, and optimize high-performance chiplet-based SoC architectures. The role involves RTL development, microarchitecture, and performance/power optimization for AI hardware.

Senior Physical Design Engineer for Tenstorrent's AIDC Yayoi project, focusing on chiplet-level and chip-top physical implementation of high-performance CPU-based SoCs in a system-in-package environment. Requires extensive experience in SoC/ASIC/GPU/CPU physical design, proficiency with industry-standard tools, and scripting skills.

This role focuses on the physical design of AI and CPU System-on-Chip (SOC) designs, including floorplanning, power grids, and clock networks, to ensure chip-level closure. It involves collaboration with cross-disciplinary teams and optimization for power, performance, and area.

Tenstorrent is seeking a Staff Engineer, Emulation Technical Lead to lead technical efforts and strategy around their emulation infrastructure for high-performance CPUs that power AI products. This role involves leading technical strategy, enabling emulation infrastructure, driving debug efforts, and optimizing performance with design verification teams and tool vendors. The role is hybrid and based in Austin, TX.

Tenstorrent is seeking an Infrastructure Automation Engineer to automate the provisioning, configuration, and deployment of large-scale AI infrastructure across on-prem data centers and accelerator clusters. The role involves using Ansible and AWX, scripting languages like Python, and managing Linux systems and CI/CD pipelines.

The role focuses on CPU design infrastructure for performance analysis, correlation, and verification, working with RISC-V ISA and collaborating with core architects and RTL teams to deliver efficient and performant designs. It involves enhancing the design environment, tools, and methodologies, and optimizing power, performance, and area.

Tenstorrent is an AI company seeking a Power Design Engineer to focus on power analysis and optimization for CPU chiplets. The role involves defining power strategies, managing power vectors, driving analysis on RTL and netlist using tools like Joules and PrimePower, and collaborating with various design teams. While the company is in the AI space, this specific role is focused on semiconductor design (CPU power) rather than direct AI/ML model development or deployment.

Tenstorrent is seeking a Lead Engineer to own post-silicon power characterization and correlation for AI semiconductor products. Responsibilities include developing and executing power measurement strategies, correlating silicon data with pre-silicon models, and driving improvements in power architecture and methodologies. The role requires deep understanding of silicon power domains and lab measurement techniques, with a focus on cross-functional collaboration.

Business Development Lead for Tenstorrent's sovereign AI strategy in India, focusing on identifying opportunities, managing client relationships, and supporting go-to-market execution. Requires experience in the AI hardware/software market and strong client relationships in India.

This role is for a Sr. Manager of Quality within the Supply Chain at Tenstorrent, a company focused on AI technology and RISC-V compute. The individual will build and own the quality organization for hardware systems and custom silicon, setting standards for reliability and scalability. Responsibilities include establishing a Quality Management System (QMS), driving Design for Quality, defining manufacturing controls, and managing supplier quality programs. The role requires extensive experience in hardware/semiconductor quality, leadership in building quality functions, and frequent travel.

Tenstorrent is seeking a Signal Integrity Engineer to design, simulate, and validate high-speed interconnects for AI hardware. The role involves collaboration with ASIC packaging teams, ODMs, and internal layout teams, as well as supporting post-silicon bring-up and troubleshooting. Experience with high-speed digital design, PCB/package design, and SI/PI simulation tools is required.

Tenstorrent is seeking a Layout Engineer with expertise in board layout for high-performance computing and AI hardware. This role requires direct experience with multi-layer boards, HDI vias, blind vias, back drilling, DFM, DFA and routing / layout of interfaces like GDDR, LPDDR, DDR, PCIe Gen 5 & 6, Ethernet IEEE 802.3bj, cd, cf, USB, etc. The ideal candidate will work closely with cross-functional teams consisting of engineers from systems, power, signal integrity and mechanical to ensure that our products meet the layout margins and cutting-edge specifications for mass production boards for data centers, workstations, and consumer computing applications.

This role is for a Sustaining Test Engineer in Taiwan, focusing on supporting semiconductor test operations at OSAT partners. The engineer will be responsible for driving yield improvements, resolving manufacturing issues, and ensuring the successful deployment of test solutions. Key responsibilities include validating and maintaining test programs, analyzing test data, leading investigations for RMA and customer returns, and managing business continuity for test operations. The role requires hands-on ATE experience and strong debugging skills in a production environment.

Software Architect role focused on defining and developing software stacks for automotive (ADAS, IVI) and robotics applications, particularly for RISC-V based heterogeneous edge computing environments. The role involves working across software development teams, customers, and partners to define software strategy and enable adoption of RISC-V architecture. Experience with ISO26262, IEC61508, and ASPICE is mentioned.

Site Lead for Tenstorrent's Munich engineering hub, responsible for program planning and execution of silicon and platform initiatives, bridging German engineering with global priorities, and fostering innovation.

Tenstorrent is seeking a Staff Engineer for Software Release and Packaging, focusing on RISC-V and system IP products. The role involves building, packaging, and releasing software that combines Linux and open-source packages with proprietary software to enable customer success. This is a remote or hybrid position in North America or Australia, with compensation ranging from $100k to $500k. A key requirement is eligibility to access U.S. export-controlled technology.

Tenstorrent is seeking a Sr Staff Engineer, CPU System Microarchitect to define and implement CPU system RTL, combining cores, clusters, fabrics, and subsystem components. The role involves collaboration with DV, PD, architecture, and performance teams to deliver a functional, timing, and power-converged design. Experience with microarchitecture definition, RTL coding, and debugging is required.

Tenstorrent is seeking an SOC Architect to design central compute chiplets for next-generation automotive SoCs. This role involves translating automotive and safety requirements into architecture, focusing on performance, power, and reliability. The position requires a systems mindset and experience with SoC architecture, interconnects, memory, and CPUs, with familiarity in functional safety (ISO 26262) and automotive-grade design challenges.

Field Application Engineer for Tenstorrent's automotive robotics division, focusing on driving adoption of their AI technology and RISC-V CPUs through customer and partner engagement. The role involves technical marketing, support, and ecosystem building within the semiconductor industry, particularly with open chiplet initiatives.

Sr. Staff Design Verification Engineer for Tenstorrent, focusing on digital designs for AI accelerators and RISC-V CPUs in an automotive robotics context. The role involves leading verification strategy, building test environments, and mentoring engineers, with a strong emphasis on SystemVerilog and UVM.

Tenstorrent is seeking an Emulation Engineer to build and scale emulation platforms for their SiP-based AI or ML engines. This role involves architecting and developing emulation environments, testbenches, and support systems to enable hardware, software, and architectural validation, with a focus on silicon debug, DV, and performance.

Sr. Staff RTL Engineer for Automotive Robotics at Tenstorrent, focusing on designing and delivering core hardware modules for next-generation chiplet-based SoCs. The role involves hands-on RTL design for silicon that will power real automotive systems under strict performance and safety constraints, requiring collaboration with IP vendors and internal teams for subsystem integration, testing, and bring-up.

DFT Engineer for Automotive Robotics team, focusing on designing and delivering core hardware modules for next-generation chiplet-based SoCs. The role involves defining DFx strategy, ensuring aggressive performance, quality, and safety targets are met, and collaborating with silicon design, DFT, OSAT partners, and customers. Experience with ATPG, DFx insertion tools, RTL coding for DFx logic, and fault models is required. Exposure to post-silicon testing and fault campaigns is a plus. The role will involve learning about SiP production, chiplet integration, and balancing architecture, DFT, and test costs.

Tenstorrent is seeking a Physical Design Engineer to drive the Die-to-Die (D2D) Physical Implementation from RTL to GDSII for multi-die/chiplet architectures. The role involves full physical design flow, including synthesis, floorplanning, place-and-route, CTS, and sign-off, with a focus on high-speed interfaces.

Develops production test programs for high-performance AI/ML silicon on ATE test platforms, translating DFT/ATPG content into optimized ATE solutions and implementing Streaming Scan Network architectures. Focuses on reducing test cost, optimizing test time for chiplet/multi-die architectures, and enabling yield learning.

Tenstorrent is seeking a Senior Chiplet Physical Design Engineer to design and integrate chiplets into a System-in-Package (SiP) for AI silicon. The role involves synthesis, place-and-route, and timing closure for high-speed CPU cores on advanced process nodes, collaborating with global teams and external partners.

This role focuses on post-silicon validation of RISC-V based SoCs, involving bring-up, validation, and debug. It requires hands-on lab experience and understanding of SoC architectures, working closely with design, firmware, and software teams.

Seeking a Design Verification Engineer to join the RISC-V CPU team, responsible for block-level verification of high-performance Cache and Coherence units using UVM environments.

Senior Tax Manager responsible for leading all aspects of Tenstorrent’s tax function including federal, state, and international income tax filings, annual audits, sales tax reporting and remittance, and strategic tax planning. This role will report to the VP of Finance and key external partners.

Staff Design for Test STA Engineer at Tenstorrent, a company focused on AI technology. The role involves ensuring testability, quality, and performance of AI processors through DFT and STA expertise. Responsibilities include defining and implementing DFT methodology, owning timing constraints and sign-off for DFT modes, and collaborating with RTL, Physical Design, and Product Engineering teams.

This role focuses on advancing ASIC design infrastructure and flows for RTL development, verification, and physical implementation, aiming to improve design quality, enable scalability, and automate methodologies. It involves developing and maintaining ASIC design methodologies, owning static code analysis, developing synthesis timing constraints, and supporting the RTL-to-GDS flow.

Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes. Responsibilities include leading physical verification closure, debugging issues, and collaborating with cross-functional teams to achieve successful tapeouts.

This role focuses on the physical design of AI and CPU SoCs, including floorplanning, power grids, and clock networks, to ensure design closure at the chip level. It involves collaboration with architecture, RTL, and packaging teams to optimize for power, performance, and area.