Currently tracking 65 active AI roles, up 115% versus the prior 4 weeks. Primary focus: Serve · Engineering. Salary range $122k–$414k (avg $253k).
| Title | Stage | AI score |
|---|---|---|
| Intel Process Integration Engineer - (FE) Process Integration Engineer at Intel, focusing on developing integrated front-end process flows for new technology nodes, analyzing yield loss, and optimizing device performance. Requires a PhD in a relevant engineering or science field and experience in semiconductor fabrication or device characterization. | — | 0 |
| Infrastructure and DevOps Engineer Infrastructure and DevOps Engineer responsible for designing, deploying, and maintaining scalable infrastructure systems, building and optimizing CI/CD pipelines, and collaborating with development teams to implement technical solutions. Requires expertise in automation tools, DevOps methodologies, and Windows Server administration. | — | 0 |
| Accountant Accountant role at Intel focusing on preparing and maintaining financial records, managing audits, preparing internal and regulatory financial reports, developing finance policies, defining accounting system roadmaps, validating month-end accounts, and coordinating with statutory auditors. Requires a Bachelor's degree or Professional Degree in Accountancy, a Professional Accounting Qualification (CA/ACCA/CPA), and a minimum of 5 years of experience in a global organization. External auditor experience or knowledge of SAP S4 is preferred. |
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| Software Development Engineer Software Development Engineer role focused on designing, developing, and testing cloud-native applications and microservices with a strong emphasis on security best practices and automated testing within a government programs context. Requires experience with Azure cloud solutions, APIs, and container technologies. | — | 0 |
| Trainee Manufacturing Technician Trainee Manufacturing Technician role at Intel Ireland supporting wafer manufacturing operations in a semiconductor environment. Responsibilities include equipment operation, maintenance, troubleshooting, and following procedures, with a focus on developing technical skills through structured training. | — | 0 |
| Analog Post-Si Engineer Executes functional validation and performance characterization for on-chip power delivery IP, identifies and resolves power delivery issues, and partners with cross-functional engineering teams to drive design optimization. | — | 0 |
| Source To Pay Solutions - Senior Lead This role is for a Senior Lead in Source To Pay Solutions, focusing on Supply Chain IT systems, SAP procurement modules, and end-to-end business process design. The candidate will lead FIT/GAP analysis, design and implement solutions in SAP MM and Inventory Management, and support SAP Ariba modules. Experience with SAP ECC/S4, Ariba, EDI standards, and procurement processes is required. Knowledge of newer SAP technologies like BTP, SAP Core AI, SAP Build, Agentic, CAP, and Fiori/UI5 is preferred. | — | 0 |
| Sr. Infrastructure Engineer – Windows OS Sr. Infrastructure Engineer - Windows OS role focused on deploying, configuring, and managing Windows Server OS and layered applications for Intel's Foundry Automation group, with an emphasis on automation and security within a government programs context. | — | 0 |
| Sr. Infrastructure Engineer – Storage This role focuses on the infrastructure and storage engineering for government programs within Intel's Foundry Automation group. The engineer will be responsible for developing, optimizing, and integrating advanced storage technologies (object, file, block, SDS) across various service models (bare metal, IaaS, PaaS). Key responsibilities include planning, managing, and optimizing storage and backup solutions, designing scalable infrastructure, ensuring data protection and regulatory compliance, and troubleshooting storage issues. The role requires in-depth knowledge of SAN, NAS, SDS, and object storage, enterprise backup solutions, and automation tools like Ansible and Python. A strong understanding of general system administration and solutions architecture is also necessary. | — | 0 |
| Sr. Infrastructure Engineer – Virtualization and Cloud Platforms This role focuses on engineering, deploying, and managing on-prem cloud infrastructure and virtualization environments (VMware), with a strong emphasis on CI/CD, infrastructure-as-code, and adherence to NIST security standards. It involves collaboration with cross-functional teams and advanced troubleshooting within these environments. The role requires experience with government programs and the ability to obtain security clearance. | — | 0 |
| Middleware Development Engineer Develops the offloading runtime (liboffload) for heterogeneous compute (GPUs and CPUs) within the LLVM ecosystem, bridging languages like SYCL and OpenMP to driver-level backends. Responsibilities include API design, backend implementation, upstream LLVM contributions, and community engagement. | — | 0 |
| Silicon Packaging Design Engineer This role focuses on the physical layout design of Intel's silicon for packaging technology, involving optimization for performance, reliability, and manufacturability. It requires developing custom layouts, performing detailed planning and routing, verifying standard cell libraries, and executing layout verification processes. The engineer will use EDA tools, troubleshoot design issues, and collaborate with cross-functional teams to ensure seamless execution of silicon tape-in, driving innovative layout methodologies. | — | 0 |
| Design Verification Eng Graduate Intern This is an internship role for a Design Verification Engineer focused on verifying the functional logic of silicon designs, ensuring alignment with architecture specifications. Responsibilities include developing verification plans, test benches, and environments, performing emulation and simulation, and debugging design issues. The role requires proficiency in SystemVerilog/Verilog and understanding of verification methodologies like OVM/UVM. | — | 0 |
| Module Development Engineer - CMP Chemical Mechanical Planarization (CMP) Process Development Engineer in Logic Technology Development (LTD) organization, responsible for developing and sustaining planarization techniques for semiconductor manufacturing. This role involves process integration, equipment solutions, feasibility studies, and roadmap development for innovative device architectures. Requires collaboration with suppliers and staying updated on industry trends. | — | 0 |
| GPU Software Development Engineer GPU Software Development Engineer focused on validation and debug of graphics IP, integrating features, triaging failures, and developing debug tools. The role involves scaling across display, media, 3D, compute, and power conservation components, and enabling features for AI domains to improve performance on graphics products. Requires strong analytical and problem-solving skills, with experience in C, C++, Python, and graphics/GPU hardware/software. | — | 0 |
| Senior CPU Power Delivery Engineer Senior CPU Power Delivery Engineer role at Intel, focusing on the design, verification, and integration of power delivery networks for next-generation CPUs. Requires expertise in VLSI, physical design, and power delivery analysis tools. | — | 0 |
| Network Systems and Solutions Engineer This role focuses on providing technical support and engineering solutions for Intel's programmable Infrastructure Processing Units (IPUs) to customers, involving hardware and software integration, system bring-up, driver configuration, and use case testing. The engineer will also develop technical collateral, evaluate tools, and analyze customer feedback to drive product improvements. | — | 0 |
| CPU Formal Verification Engineer Intel is seeking a Formal Verification Engineer to ensure the reliability and functionality of their IP and SoC microarchitectures. This role involves using advanced formal verification tools and methodologies, developing test and coverage plans, creating abstraction models, and developing formal proofs. The engineer will collaborate with architects, RTL developers, and physical design teams, and maintain the verification infrastructure. | — | 0 |
| Density Fill PDK Development Engineer Develops and debugs Fill components of Process Design Kits (PDKs) using EDA tools like Calibre, ICV, and Pegasus to address density deficiencies and ensure manufacturability compliance. Automates workflows and collaborates with cross-functional teams and external vendors. | — | 0 |
| Latin America Payroll Processor This role focuses on processing payroll computations, maintaining payroll records, and supporting automation initiatives using tools like Excel macros and RPA. It involves ensuring accuracy, handling employee inquiries, and collaborating on operational improvements within a payroll team. | — | 0 |
| Corporate Accounting Mergers Acquisitions Specialist Corporate Accounting Mergers Acquisitions Specialist at Intel, focusing on financial integration/disintegration, technical accounting research, and project management for M&A activities. Requires CPA and experience in public accounting or valuation. | — | 0 |
| SoC Pre-Silicon Verification Engineer This role focuses on the pre-silicon functional logic verification of an integrated SoC to ensure it meets specifications. Responsibilities include defining and developing verification plans, test benches, and environments, executing these plans through emulation and system simulation, debugging issues, and collaborating with various design teams. The role also involves incorporating security verification and improving the verification infrastructure. | — | 0 |
| SoC Design Verification Engineer - Emulation This role focuses on SoC Design Verification using Emulation, involving building emulation targets, supporting new features/IPs, debugging failures, developing validation tools, and performing system-level validation tasks. It requires experience with technical specs, RTL code, and building emulation models for large-scale SoCs. | — | 0 |
| Technology Development Quality and Reliability Engineer Engineer in Technology Development Quality and Reliability Engineering group focusing on research and technology development for semiconductor devices and processes. Responsible for developing solutions and design rules to mitigate plasma induced process charging, designing test structures, running experiments, analyzing data, and serving as a consultant to design teams. | — | 0 |
| APTM NPI Integration Seeking an NPI Integration Engineer to manage the development and execution of new product introductions and process transfers across factories, ensuring technology and products meet certification requirements before transferring to High Volume Manufacturing (HVM). Responsibilities include logistical coordination, acting as a primary information interface, tracking collateral, managing silicon progress, and developing new NPI systems and business processes. | — | 0 |
| Systems and Solutions Engineer This role focuses on product lifecycle management, workflow definition, requirements analysis, solution design, and program planning within the context of processor platforms. It involves cross-functional collaboration and continuous improvement of engineering processes. | — | 0 |
| Foveros Direct Pathfinding Integration This role focuses on the design, development, and qualification of advanced semiconductor packaging solutions and materials. It involves managing the entire packaging development process, from artwork to manufacturing startup, and consulting with cross-functional partners on various aspects of product launch and supply chain. The role requires a strong background in engineering principles, materials science, and semiconductor packaging, with experience in qualification testing and specification documentation. | — | 0 |
| Physical Design Engineer for Core IP This role involves the physical design implementation of custom CPU designs, from RTL to GDS, for Intel's core IP development team. Responsibilities include synthesis, place and route, static timing analysis, power/clock distribution, reliability analysis, and verification. The engineer will optimize CPU designs for power, frequency, and area, and collaborate with EDA vendors to improve tool capabilities. The role requires experience with integrated circuit design tools and scripting languages. | — | 0 |
| MDCE BEOL Integration Engineer This role focuses on process engineering and yield optimization within semiconductor manufacturing, specifically in the BEOL integration for Intel's advanced technology nodes. The engineer will work on identifying root causes of yield/performance issues, implementing corrective actions, and collaborating with various teams to ensure successful product introduction and continuous improvement. | — | 0 |
| Senior Compiler Engineer Senior Compiler Engineer at Intel responsible for the development, enhancement, and maintenance of Intel C/C++/DPC++ and Fortran Compilers, with a focus on performance optimization for CPU platforms. The role involves feature development, defect resolution, performance analysis, and collaboration with hardware design teams and open-source communities. | — | 0 |
| Emulation Engineer This role focuses on building and optimizing emulation and FPGA models for Intel's silicon prototyping and validation efforts. The engineer will work on translating RTL designs into working prototypes, developing hardware/software collateral, and improving emulation usability and efficiency to accelerate the development process for chipsets. The role involves collaboration with design, validation, and software teams to enable pre-silicon verification and software development. | — | 0 |
| Accountant Accountant role focused on employee benefit programs (Health & Welfare, Pension/Retirement). Responsibilities include monthly close, statutory reporting, audit support, and partnering with HR Benefits and external stakeholders to ensure accurate and compliant benefit accounting. Requires experience with close processes, analytical skills, and proficiency in Excel and financial systems. Preferred qualifications include employee benefits accounting experience, proxy support, statutory reporting, SOX compliance, and SAP S/4HANA knowledge. | — | 0 |
| Senior Physical Design Engineer Senior Physical Design Engineer responsible for the end-to-end physical design implementation of custom IP and SoC designs, from RTL to GDS, optimizing for power, frequency, and area. This role involves synthesis, place and route, timing analysis, verification, and contributing to the automation of physical design methodologies. | — | 0 |
| CPU power Architect Power management architect for Intel Architecture group, defining state-of-the-art CPU end-to-end power handling, including active and idle power management solutions, and interaction with OS, driver, and platform components. Focus on defining next-generation CPU power management architecture and delivering architectural specifications, initiating, guiding, and coordinating the design of new ideas and products, and driving implementation post-silicon. | — | 0 |
| Accountant Accountant role at Intel in Malaysia, focusing on financial preparation, compliance, and analysis. Responsibilities include supporting quarter-close activities, coordinating deliverables, preparing management reports, and assisting with SOX compliance and governance. The role also involves identifying opportunities for process improvement, including AI automation and digital workflow enhancements. | — | 0 |
| Accountant Accountant role at Intel in Malaysia, responsible for preparing, analyzing, and validating financial records, ensuring compliance with global financial standards (IFRS, US GAAP), managing auditor interactions, and supporting forecasting activities. Requires proficiency in accounting principles, financial systems (SAP S4, SQL, Power BI), and SOX compliance. | — | 0 |
| Accountant This role is in Accounting Operations and focuses on supporting and improving corporate P&L forecasting processes, accounting systems workflows, and finance transformation initiatives. The role involves recurring support for planning and reporting cycles, process coordination, stakeholder communications, and project work related to accounting workflows, system enhancements, testing, and implementation. A key aspect is identifying and applying AI and automation to improve finance and accounting processes, partnering with IT and finance systems teams to evaluate AI use cases. | — | 0 |
| Accountant Accountant role focused on administration, governance, enhancement, and transformation of accounting processes and tools, including system administration, workflow design, reporting, and continuous improvement within an S/4 environment. Requires experience with SAP S4, SQL, and Power BI. | — | 0 |
| Accountant This role is in Accounting Operations, supporting accounting and reporting activities. It involves close execution, financial compliance, and process improvement. The role will also explore and apply AI and automation tools to enhance efficiency and reporting within accounting processes. | — | 0 |
| Accountant Accountant role focused on treasury-related financial reporting, accounting, and controllership for cash flow hedging activities, derivative instruments, and investments. Requires expertise in US GAAP, financial systems (SAP, Power BI, SQL), and SOX compliance. The role involves preparing schedules, journal entries, reconciliations, and supporting hedge documentation and effectiveness analyses. Experience with AI and digital tools for process improvement is mentioned. | — | 0 |
| Accountant This role focuses on accounting, controllership, and financial reporting for treasury-related activities, specifically debt and equity transactions. Responsibilities include preparing journal entries, reconciliations, supporting analyses for new issuances and modifications, and ensuring compliance with US GAAP and internal policies. The role also involves supporting SOX compliance, maintaining process documentation, and collaborating with various finance and treasury teams. A key aspect is the use of AI and digital tools to enhance efficiency in accounting processes. | — | 0 |
| Accountant This role is for an Accountant at Intel in Malaysia, focusing on accounting, reporting, and controllership for treasury-related activities such as debt, equity, and cash management. The position involves leading accounting processes, ensuring US GAAP compliance, supporting financial reporting, and implementing process improvements. The role also requires partnering with various finance and treasury teams and utilizing AI and digital tools to enhance efficiency. | — | 0 |
| Accountant Accountant role focused on treasury-related financial reporting, including foreign currency exposures, balance sheet hedging, and derivative activities. Requires strong US GAAP knowledge, experience with financial systems (SAP, Power BI), and SOX compliance. The role will leverage AI and digital tools to improve efficiency in accounting processes. | — | 0 |
| Accountant Accountant role focused on managing the accounting lifecycle for global bonus and sabbatical programs, including accruals, journal entries, reconciliations, variance analysis, and financial close activities. Requires strong accounting fundamentals, analytical skills, and cross-functional collaboration with HR, Payroll, and other finance teams. Experience with US GAAP, ASC 710, SOX controls, and financial systems like SAP is preferred. | — | 0 |
| Accountant Accountant role at Intel in Malaysia, focusing on financial preparation, analysis, and compliance with global standards. Responsibilities include maintaining financial records, managing auditor interactions, validating accounts, driving IFRS/US GAAP compliance, and supporting accounting for employee benefit programs like sabbaticals and health/welfare. Requires proficiency in accounting principles, financial systems (SAP S4, SQL, Power BI), and SOX compliance knowledge. Experience in a global organization and accounting/audit is necessary. | — | 0 |
| Accountant Accountant role at Intel, focusing on global bonus and sabbatical programs. Responsibilities include end-to-end accounting, reporting, forecasting, and controllership. Requires preparing and analyzing financial records, ensuring compliance with global financial standards, and collaborating with HR, Payroll, and other finance teams. Experience with financial systems like SAP S4, SQL, Power BI, and SOX compliance is necessary. The role supports accounting under ASC 710 and involves close activities, reconciliations, variance analysis, and audit support. | — | 0 |
| Accounting Manager Accounting Manager at Intel responsible for the global accounting lifecycle of bonus and sabbatical programs, ensuring compliance with ASC 710 and US GAAP/IFRS. The role involves collaboration with HR, Payroll, Treasury, and other finance teams, financial forecasting, reporting, and maintaining internal controls. It also includes leading and developing a team and identifying process improvement opportunities. | — | 0 |
| Accountant Accountant role focused on managing the complete accounting lifecycle for restructuring and severance programs, including recognition, measurement, tracking, reconciliations, and financial reporting, while collaborating with various internal teams and ensuring SOX compliance. | — | 0 |
| Learning and Development Consultant This role focuses on developing and delivering training programs for a manufacturing workforce, assessing skill gaps, designing technical and compliance training, and evaluating program effectiveness. It requires experience in L&D within a manufacturing or industrial environment. | — | 0 |
| Director, Data Center Strategy and Capacity Planning This role defines and drives the multi-year infrastructure strategy and capacity plan for global IT data center environments, balancing performance, scalability, cost, and resiliency. It involves creating demand forecasts, scenario planning, identifying capacity risks, developing investment frameworks (CapEx, OpEx, TCO), and influencing enterprise-level trade-offs. The position also manages infrastructure refresh strategies, governs data for demand and capacity, and translates complex information into executive-ready narratives. | — | 0 |