Intel

This role is for an IP Design Verification Engineer at Intel, focusing on ensuring the quality and reliability of Intel's IP designs. Responsibilities include developing and executing verification plans, creating test benches and cases, performing simulations, debugging issues, and collaborating with cross-functional teams. The role requires proficiency in System Verilog and Python, knowledge of IP validation tools and methodologies, and experience in test planning and hardware simulation.

This role focuses on the functional logic verification of an integrated SoC, ensuring it meets specifications. Responsibilities include defining and developing verification plans, test benches, and environments, executing these plans using emulation and simulation models, debugging issues in the presilicon environment, and collaborating with various design teams. The role also involves incorporating security activities into test plans and maintaining the verification infrastructure. Experience with Pre-Si validation, System Verilog OVM/UVM, and scripting languages like Python is required.

Senior CPU Design Engineer focused on front-end integration and quality assurance across multiple teams and sites. Responsibilities include leading complex subIP integration, static methodology sign-off (CDC, RDC, Lint, low-power), and driving end-to-end integration workflows. Requires strong technical leadership and collaboration skills.

Designs, develops, tests, and debugs software applications, potentially spanning the full application stack (frontend and backend). Utilizes modern software development methodologies, secure coding practices, and follows legal compliance guidelines. Responsibilities include analyzing user stories, writing functional and test code, automating build/deployment, and performing various levels of testing. Also involves SDL tasks, contributing to product documentation, and potentially interacting with end-users for requirements definition.

This Systems and Solutions Engineer role at Intel focuses on the design, development, and integration of complex systems involving software, firmware, board, and silicon components for data centers. The role involves defining system architecture, translating business needs into technical specifications, and leading the implementation of end-to-end technical solutions. Key responsibilities include automating data center infrastructure build-up, provisioning, monitoring, and creating reusable building blocks for management tools. The position requires strong programming skills (Python preferred), deep OS knowledge, experience with IaC tools, and the ability to lead cross-functional teams.

Standard Cell Design Reliability Verification Engineer at Intel, focusing on IR/EM flows, VLSI, and using EDA tools for ASIC designs. Requires expertise in device physics, FinFet characteristics, and Python for automation.

This role is for an IP Functional Validation Engineer responsible for functional validation in pre-silicon or post-silicon environments. The engineer will understand architecture specifications, develop test plans, create infrastructure and automation, perform debugging, and work with stakeholders. Experience with High Speed IO (PCIE) and scripting languages like Python or C/C++ is required.

Analog Circuit Design Engineer responsible for designing, developing, and optimizing analog and mixed-signal circuits in advanced process nodes, contributing to Intel's IP solutions and shaping the future of computing and communication systems.

Design Engineer at Intel responsible for microarchitecture and design of soft IP cores for Intel’s next generation chips (including SOCs). Requires relevant ASIC design/validation experience in front end processes including RTL development, functional and performance verification. Expertise in verilog and system verilog based logic design, design quality check tools, and potentially PCI_Express or AMBA standards. Knowledge of AI tools like Github Copilot is mentioned.

Accountant role at Intel focusing on preparing and maintaining financial records, managing audits, preparing internal and regulatory financial reports, developing finance policies, defining accounting system roadmaps, validating month-end accounts, and coordinating with statutory auditors. Requires a Bachelor's degree or Professional Degree in Accountancy, a Professional Accounting Qualification (CA/ACCA/CPA), and a minimum of 5 years of experience in a global organization. External auditor experience or knowledge of SAP S4 is preferred.

This role is for a Senior Lead in Source To Pay Solutions, focusing on Supply Chain IT systems, SAP procurement modules, and end-to-end business process design. The candidate will lead FIT/GAP analysis, design and implement solutions in SAP MM and Inventory Management, and support SAP Ariba modules. Experience with SAP ECC/S4, Ariba, EDI standards, and procurement processes is required. Knowledge of newer SAP technologies like BTP, SAP Core AI, SAP Build, Agentic, CAP, and Fiori/UI5 is preferred.

This role focuses on building and optimizing emulation and FPGA models for Intel's silicon prototyping and validation efforts. The engineer will work on translating RTL designs into working prototypes, developing hardware/software collateral, and improving emulation usability and efficiency to accelerate the development process for chipsets. The role involves collaboration with design, validation, and software teams to enable pre-silicon verification and software development.

Seeking a Cloud Application Development Engineer to shape the future of cloud-based applications by enabling seamless integration of cloud platforms and DevOps solutions, ensuring a secure and scalable environment. Responsibilities include developing cloud applications, defining DevOps solutions, designing cloud architecture, implementing user interfaces, utilizing Kubernetes and microservices, creating APIs, optimizing databases, and collaborating with cross-functional teams.

Senior Layout Design Engineer at Intel responsible for designing complex analog signal circuit layouts, performing design verification, and developing new layout methodologies. Requires strong VLSI and custom/analog layout design experience.

This role focuses on architecting, designing, developing, and validating power management firmware (pCode) for IPs and SoCs. It involves developing power management features and algorithms, collaborating on silicon architecture, and performing functional verification. The role also includes power and performance analysis, optimization, and providing recommendations for future power management architectures. While the core is firmware development, there's a mention of potentially researching AI applications to improve performance.

Lead CPU Design Verification Engineer responsible for pre-silicon functional verification of CPU architectures and microarchitectures, including test bench development, simulation, emulation, and debugging. The role also involves exploring AI-based validation methodologies.

This role is for a CPU Design Verification Engineer at Intel, focusing on validating next-generation CPUs. Responsibilities include developing pre-silicon functional verification tests, creating and executing verification plans, defining and analyzing simulation/emulation models, debugging failures, and collaborating with cross-functional teams. The role also involves contributing to the definition of architectural features and exploring AI-based validation methodologies for improved efficiency and quality.

This role is for a CPU Design Verification Engineer at Intel, focusing on validating next-generation CPUs. Responsibilities include developing pre-silicon functional verification tests, creating and executing verification plans, defining and analyzing simulation/emulation models, debugging failures, and collaborating with cross-functional teams. The role also involves contributing to the definition of architectural features and exploring AI-based validation methodologies for improved efficiency and quality.

Experienced Infrastructure Storage Engineer to lead the development, optimization, and integration of advanced storage technologies (object, file, block, SDS) across various service models. Responsibilities include planning, designing, implementing, maintaining, and scaling high-performance on-premise storage solutions, resolving issues, and collaborating with software engineering teams. Requires in-depth knowledge of SAN, NAS, SDS, Object Storage, enterprise backup solutions, and automation tools.

SoC Physical Design Clocking Engineer responsible for next generation Server SoC designs, focusing on product pathfinding, clock distribution, and overall SoC clock implementation and sign-off. Requires experience in clocking IPs, simulations, and methodologies, with a good understanding of physical design and timing analysis.

Seeking a Firmware Validation Lead to drive the validation of firmware for client products, develop BIOS validation plans, ensure process compliance, and manage defect closure. The role involves leadership in defining new platforms, supporting bring-up, and reviewing designs. Requires strong understanding of Intel Architecture, UEFI/BIOS, firmware-silicon-platform dependencies, and security validation. Hands-on experience in test content automation is mandatory, with Python proficiency preferred.

Seeking a Systems and Solutions Engineer to lead customer co-engineering programs, manage technical issue resolution, and build strategic engagements with Japan OEMs. This role involves defining and driving multi-year programs, coordinating with internal engineering teams for validation and readiness, and ensuring timely design launches and process improvements.

Administrative Assistant role at Intel, supporting office operations, executives, and events. Responsibilities include calendar management, travel coordination, event planning, communication screening, report generation, and inventory management. Requires proficiency in Microsoft Office Suite and strong organizational skills.

Senior Design Verification Engineer for Intel's Silicon Chassis team, responsible for owning verification of interconnect and chassis IP blocks. Requires expertise in verification planning, environment development, collaboration with cross-functional teams, and debugging. The role involves using AI-assisted development tools.

Intel is seeking a Senior System Software/Firmware Engineer to design, develop, and validate system software and firmware for data center hardware, including AI platforms. The role involves collaborating with cross-functional teams, implementing low-level hardware abstractions, and participating in power-on and bring-up activities. Responsibilities include design, implementation, testing, and validation of firmware components like UEFI, BMC, and device drivers for operating systems such as Linux.

Develop firmware for DDR memory subsystems, including initialization, training, and calibration algorithms, adhering to JEDEC standards. Analyze, replicate, root cause, and debug issues in presilicon and post-silicon environments. Collaborate with architects and designers to ensure robust solutions.

Seeking a hands-on SoC Design Verification Engineer to own the verification lifecycle for complex SoC/IP blocks, including planning, UVM testbench development, test content creation, coverage closure, and debug. The role involves close collaboration with design, architecture, and firmware teams to deliver high-quality silicon.

Firmware Validation Engineer at Intel, focusing on defining validation strategies, developing automated test frameworks (Python/pytest), validating low-level embedded features, and performing root-cause analysis for pre-silicon and post-silicon environments. Requires strong embedded systems fundamentals, test automation proficiency, and debugging skills.

Seeking an experienced Logic Design engineer for the Intel Chassis Group to deliver component and foundation IPs for SoC chassis. Responsibilities include logic design of routers, switches, arbiters, and protocol conversion bridges, with a focus on high-performance data and control planes. Familiarity with AMBA/CXL protocols and concepts like QoS, access control, and RAS is desired. Experience with AI to assist logic design is a plus.

This role focuses on formal verification of IP and/or SoC microarchitecture using model checking and equivalence checking algorithms. The engineer will create verification plans, abstraction models, develop formal proofs, and maintain verification infrastructure. Collaboration with RTL developers and architects is key.

This role manages a team of engineers responsible for developing, validating, and optimizing Process Design Kits (PDKs) and design methodologies for Intel's advanced process nodes. The focus is on ensuring the quality and robustness of PDK collateral for internal and external design communities, particularly in ASIC EM/IR, ESD PERC, and High Voltage domains. The manager will drive innovation in tools and flows, collaborate with manufacturing and design teams, and conduct root cause analyses for issues.

Lead formal verification efforts for complex CPU designs, developing environments, creating models and properties, analyzing failures, and guiding team members. Requires Master's degree and 8+ years of experience in formal verification, with proficiency in relevant tools and languages.

Lead formal verification efforts for complex CPU designs (i9, i7, i5, Xeon processors). Develop environments, create models and properties, analyze failures, and guide team members. Stay updated on formal verification technologies and develop new methodologies.

Senior/Staff VLSI Verification Engineer with 11-15 years of experience in complex SoC/ASIC verification, focusing on UVM/System Verilog testbench architecture, Mix signal IP verification strategy, and post-silicon debug. Responsibilities include defining verification plans, mentoring junior engineers, ensuring coverage closure, and collaborating with architects. Experience with formal verification methods is also required.

Lead a team responsible for pre-Silicon functional verification of Intel's latest CPUs, developing test plans, simulation models, and test benches to ensure design requirements are met. Focus on driving strategic tool/flow/methodology initiatives to reduce validation cycle time and ensure first-pass silicon success. Requires technical leadership and managerial experience in pre-Silicon verification environments.

This role is for a TFM and PPA Physical Design Engineer in the CPU team at Intel, focusing on developing and automating backend physical design flows for high-performance CPUs. Responsibilities include synthesis, place-and-route, floor planning, timing analysis, power consumption estimation, and working with EDA vendors to enhance tool capabilities. Requires a Master's degree with 6+ years of experience or a Bachelor's degree with 8+ years of experience, with expertise in physical design tools and scripting.

This role focuses on formal verification of microarchitecture using industry-standard tools and algorithms for server, client, and graphics IPs. The engineer will define verification scope, deploy strategies, create abstraction models, and ensure design correctness and quality on schedule. Experience with RTL languages, assertion languages, and formal verification principles is required.

Principal Engineer role focused on the architecture, design, and integration of SoC-wide clocking networks. Responsibilities include defining PPA trade-offs, collaborating with cross-functional teams, owning the technical roadmap, mentoring junior designers, and ensuring robust silicon correlation and yield. Requires extensive hands-on experience in SoC clocking, custom analog/digital circuit design, and timing architecture.

Lead Structural Design / physical design Implementation of Custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff, including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools. Optimizes design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.

Senior Design Engineer for Intel Chassis Group, focusing on logic design of component IPs for SoC chassis. Responsibilities include designing protocol conversion bridges, debug/trace components, and clock/power controls, translating standard protocols to custom transport protocols while managing QoS, Access Control, Flow Control, RAS, and Error Handling.