This role provides technical support for Intel products and technologies, focusing on solution design, development, validation, and market readiness. It involves creating technical collateral, enabling partners, and collaborating with customer R&D and manufacturing to ensure smooth product integration and ramp-up. The role requires strong C programming and UEFI/BIOS firmware development experience.

Physical Design Engineer at Intel responsible for the end-to-end physical design implementation of next-generation Client SoCs, from RTL to GDS. This includes synthesis, floor planning, placement, routing, clock tree synthesis, power analysis, verification, and signoff. The role also involves performance optimization, developing and improving physical design methodologies, and automating design flows.

This role is for a System Modelling Engineer at Intel, focusing on the architecture, modeling, and performance analysis of 224Gbps SerDes IP. The engineer will develop end-to-end PHY system models, analyze electrical channels, optimize equalization algorithms, and perform clocking, jitter, and noise analysis. The role also involves supporting industry standards, defining test methodologies, and collaborating with cross-functional teams. The position requires a strong background in analog circuit design and high-speed design techniques.

Analog Circuit Design Engineer responsible for designing and developing analog circuits in advanced process nodes for analog and mixed-signal IPs, optimizing for power, performance, area, timing, and yield. Requires experience in PLLs, clocking circuits, LC VCO/DCO design, and CMOS fundamentals.

Analog Circuit Design Engineer at Intel focusing on high-speed interconnect solutions, designing and verifying analog circuits in advanced process nodes. Responsibilities include transistor-level design, simulation, optimization, and post-silicon validation for SerDes PHY analog blocks.

Intel is seeking an Analog Circuit Design Engineer to design, simulate, and verify analog circuits for advanced process nodes, focusing on high-speed SerDes (112/224Gbps). The role involves optimizing circuits for power, performance, area, and yield, and collaborating with cross-functional teams. Experience with EDA tools and CMOS technologies is required.

Analog Circuit Design Engineer at Intel, focusing on designing, developing, and optimizing high-speed analog circuits in advanced process nodes for next-generation memory interface PHYs. Responsibilities include circuit design, simulation, optimization for power/performance/area, test plan creation, collaboration with cross-functional teams, layout reviews, and post-silicon debug.

Design, develop, and optimize high-speed SerDes circuits for Intel's next-generation technologies, collaborating with cross-functional teams and supporting silicon validation.

Analog Circuit Design Engineer at Intel, responsible for designing, developing, and optimizing high-speed analog circuits in advanced process nodes. This role involves circuit design, validation, simulation, optimization for power/performance/area/timing/yield, test plan creation, cross-functional collaboration, and post-silicon debug. Requires expertise in high-speed analog circuits like TX/RX blocks, PLLs, DLLs, SerDes, and voltage regulators, with proficiency in industry-standard tools.

Analog Circuit Design Engineer at Intel responsible for designing, developing, and optimizing high-speed analog circuits in advanced process nodes, contributing to next-generation memory interface PHYs and analog/mixed-signal IPs. Involves circuit design, simulation, validation, optimization for power/performance/area, test plan creation, collaboration with cross-functional teams, layout reviews, and post-silicon debug.

Analog Circuit Design Engineer at Intel responsible for designing, developing, and optimizing high-speed analog circuits in advanced process nodes, contributing to next-generation memory interface PHYs and analog/mixed-signal IPs. Involves circuit design, simulation, validation, optimization for power/performance/area, test plan creation, collaboration with cross-functional teams, layout reviews, and post-silicon debug.

Senior CPU Design Engineer focused on front-end integration and quality assurance across multiple teams and sites. Responsibilities include leading complex subIP integration, static methodology sign-off (CDC, RDC, Lint, low-power), and driving end-to-end integration workflows. Requires strong technical leadership and collaboration skills.

Standard Cell Design Reliability Verification Engineer at Intel, focusing on IR/EM flows, VLSI, and using EDA tools for ASIC designs. Requires expertise in device physics, FinFet characteristics, and Python for automation.

Analog Circuit Design Engineer responsible for designing, developing, and optimizing analog and mixed-signal circuits in advanced process nodes, contributing to Intel's IP solutions and shaping the future of computing and communication systems.

Design Engineer at Intel responsible for microarchitecture and design of soft IP cores for Intel’s next generation chips (including SOCs). Requires relevant ASIC design/validation experience in front end processes including RTL development, functional and performance verification. Expertise in verilog and system verilog based logic design, design quality check tools, and potentially PCI_Express or AMBA standards. Knowledge of AI tools like Github Copilot is mentioned.

This role is for a Senior Lead in Source To Pay Solutions, focusing on Supply Chain IT systems, SAP procurement modules, and end-to-end business process design. The candidate will lead FIT/GAP analysis, design and implement solutions in SAP MM and Inventory Management, and support SAP Ariba modules. Experience with SAP ECC/S4, Ariba, EDI standards, and procurement processes is required. Knowledge of newer SAP technologies like BTP, SAP Core AI, SAP Build, Agentic, CAP, and Fiori/UI5 is preferred.

This role focuses on building and optimizing emulation and FPGA models for Intel's silicon prototyping and validation efforts. The engineer will work on translating RTL designs into working prototypes, developing hardware/software collateral, and improving emulation usability and efficiency to accelerate the development process for chipsets. The role involves collaboration with design, validation, and software teams to enable pre-silicon verification and software development.

Seeking a Cloud Application Development Engineer to shape the future of cloud-based applications by enabling seamless integration of cloud platforms and DevOps solutions, ensuring a secure and scalable environment. Responsibilities include developing cloud applications, defining DevOps solutions, designing cloud architecture, implementing user interfaces, utilizing Kubernetes and microservices, creating APIs, optimizing databases, and collaborating with cross-functional teams.

Intel is seeking a Senior System Software/Firmware Engineer to design, develop, and validate system software and firmware for data center hardware, including AI platforms. The role involves collaborating with cross-functional teams, implementing low-level hardware abstractions, and participating in power-on and bring-up activities. Responsibilities include design, implementation, testing, and validation of firmware components like UEFI, BMC, and device drivers for operating systems such as Linux.

Lead formal verification efforts for complex CPU designs (i9, i7, i5, Xeon processors). Develop environments, create models and properties, analyze failures, and guide team members. Stay updated on formal verification technologies and develop new methodologies.

Senior/Staff VLSI Verification Engineer with 11-15 years of experience in complex SoC/ASIC verification, focusing on UVM/System Verilog testbench architecture, Mix signal IP verification strategy, and post-silicon debug. Responsibilities include defining verification plans, mentoring junior engineers, ensuring coverage closure, and collaborating with architects. Experience with formal verification methods is also required.

Lead a team responsible for pre-Silicon functional verification of Intel's latest CPUs, developing test plans, simulation models, and test benches to ensure design requirements are met. Focus on driving strategic tool/flow/methodology initiatives to reduce validation cycle time and ensure first-pass silicon success. Requires technical leadership and managerial experience in pre-Silicon verification environments.

This role focuses on formal verification of microarchitecture using industry-standard tools and algorithms for server, client, and graphics IPs. The engineer will define verification scope, deploy strategies, create abstraction models, and ensure design correctness and quality on schedule. Experience with RTL languages, assertion languages, and formal verification principles is required.

Principal Engineer role focused on the architecture, design, and integration of SoC-wide clocking networks. Responsibilities include defining PPA trade-offs, collaborating with cross-functional teams, owning the technical roadmap, mentoring junior designers, and ensuring robust silicon correlation and yield. Requires extensive hands-on experience in SoC clocking, custom analog/digital circuit design, and timing architecture.

Lead Structural Design / physical design Implementation of Custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff, including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools. Optimizes design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.

Senior Design Engineer for Intel Chassis Group, focusing on logic design of component IPs for SoC chassis. Responsibilities include designing protocol conversion bridges, debug/trace components, and clock/power controls, translating standard protocols to custom transport protocols while managing QoS, Access Control, Flow Control, RAS, and Error Handling.