Intel

Diploma level contract role for a CPU-SoC Mask Layout Designer at Intel, focusing on the training, design, and development of next-generation SOC/CPU. Responsibilities include creating mask layouts, running verification tools, designing floorplans, and troubleshooting layout issues. Requires a Diploma in Electrical and Electronic Engineering and offers hands-on experience in semiconductor design.

Manufacturing Operations Manager role at Intel in Malaysia, focused on leading teams to ensure factory operations, equipment maintenance, and repair for optimal performance. Responsibilities include managing workflow, responding to issues, collaborating with engineering, and developing long-term strategies for manufacturing capabilities. Requires a Bachelor's degree and 2 years of experience in manufacturing operations, with expertise in semiconductor manufacturing principles and factory floor planning.

Intel is seeking an IP Design Verification Engineer with 6+ years of experience in Pre-Si verification. The role involves developing IP verification plans, test benches, and simulation models to ensure design specifications are met. Responsibilities include debugging issues, collaborating with cross-functional teams, and maintaining verification infrastructure. Requires strong skills in Specman “e” / System Verilog and understanding of verification methodologies.

This role supports management in improving Intel's supply chain and logistics strategy, focusing on process and quality improvements, cost control, production yield, and exploring emerging technologies. The engineer will define material inspection methodology, support product long-range planning, lead supplier selections, perform risk mitigation, establish control standards, monitor KPIs, drive supplier process validation, and manage quality excursions.

Manufacturing Operators at Intel in Malaysia are responsible for performing product manufacturing and assembly tasks, operating equipment, collecting and evaluating operating data, and driving process improvements to meet industry standards and customer specifications. The role involves working in shifts and requires basic computer literacy and problem-solving skills.

Supply Chain Engineer at Intel responsible for developing and executing supply chain strategies, ensuring supplier process and product readiness, and managing supplier relationships to meet cost, quality, availability, technology, and environmental goals within the semiconductor industry.

This role focuses on defining and optimizing power and performance targets for Intel's products, collaborating with various engineering teams. Responsibilities include driving SoC PnP projections, developing power and performance models, and defining targets across development phases. The role requires strong system-level thinking, technical judgment, and leadership skills.

Lead Design Verification Engineer for Intel's Silicon Chassis team, responsible for defining and executing verification strategy for critical chassis and interconnect IP programs. Requires deep DV expertise, protocol and memory subsystem knowledge, and collaboration across design, software, and methodology teams. The role involves leading the development of verification environments, driving functional signoffs, and mentoring engineers. AI-assisted workflows are integrated into daily development.

This role is for a Graduate Talent in Memory Design at Intel, focusing on the pathfinding and development of advanced memory technology and circuits. Responsibilities include PPA optimization, product/design enablement, IC layout, memory array/IP design, circuit innovation, testchip design, and pre/post-Si validation. The role requires a Bachelor/Master/PhD in Electrical Engineering or related STEM field, proficiency in programming languages like Python, and familiarity with Unix/Linux.

This role is for a Graduate Talent (PDK QA Engineer) within Intel's Design Technology Platform (DTP) organization, focusing on the Process Design Kit (PDK) group. Responsibilities include validating PDK quality for custom design components and developing regression test suites to ensure PDK accuracy across various EDA flows and process nodes. The role requires knowledge of VLSI semiconductor devices, electronic circuits, and familiarity with EDA tools.

Seeking a Graduate Talent Platform Hardware Engineer to support the architecture, bring-up, validation, and execution of platform hardware for test chip and validation programs. Responsibilities include board-level execution, power-on, debug, test plan execution, data collection, and documentation. The role involves collaboration with cross-functional teams and support for sustaining activities.

This role manages a team of engineers responsible for developing, validating, and optimizing Process Design Kits (PDKs) and design methodologies for Intel's advanced process nodes. The focus is on ensuring the quality and robustness of PDK collateral for internal and external design communities, particularly in ASIC EM/IR, ESD PERC, and High Voltage domains. The manager will drive innovation in tools and flows, collaborate with manufacturing and design teams, and conduct root cause analyses for issues.

This role is for a Graduate Talent (PDK QA Engineer) at Intel, focusing on the Quality validation of ASIC Design components within the Design Technology Platform/Process Design Kit (PDK) group. Responsibilities include developing regression test suites, executing them to validate PDK elements like pcells and techfiles, developing layout designs for verification, and developing circuit designs for simulations. The role requires proficiency in programming languages like TCL, Perl, or Python, and Unix/Linux knowledge.

Designs and develops analog and mixed-signal circuits for Intel's Advanced Design Foundational IP Organization, focusing on pathfinding and development of advanced logic, memory, and analog/mixed-signal circuits for Intel's process technology.

This role is for a Graduate Talent in Memory Design at Intel, focusing on the pathfinding and development of advanced memory technology and circuits. Responsibilities include PPA optimization, product/design enablement, IC layout, memory array/IP design, circuit innovation, testchip design, and pre/post-Si validation. The role requires a Bachelor/Master/PhD in Electrical Engineering or related STEM field, proficiency in programming languages like Python, and familiarity with Unix/Linux.

This role is for a Graduate Talent in Memory Design at Intel, focusing on the pathfinding and development of advanced memory technology and circuits. Responsibilities include PPA optimization, product/design enablement, IC layout, memory array/IP design, circuit innovation, testchip design, and pre/post-Si validation. The role requires a Bachelor/Master/PhD in Electrical Engineering or related STEM field, proficiency in programming languages like Python, and familiarity with Unix/Linux.

Lead formal verification efforts for complex CPU designs, developing environments, creating models and properties, analyzing failures, and guiding team members. Requires Master's degree and 8+ years of experience in formal verification, with proficiency in relevant tools and languages.

Lead formal verification efforts for complex CPU designs (i9, i7, i5, Xeon processors). Develop environments, create models and properties, analyze failures, and guide team members. Stay updated on formal verification technologies and develop new methodologies.

Semiconductor Manufacturing Engineer responsible for operational support, process optimization, and new product introduction in a fabrication facility. This role involves analyzing factory metrics, developing manufacturing plans, and collaborating with engineering and automation teams to ensure efficient production and delivery schedules.

Process and Equipment Engineer at Intel in Malaysia, responsible for optimizing high-volume manufacturing equipment and processes for integrated circuit production. This role involves ensuring precision, quality, cost efficiency, and technology scaling, with opportunities for global process transfer and continuous improvement.

Process and Equipment Engineer at Intel in Malaysia, focusing on optimizing high-volume manufacturing equipment and processes for integrated circuits. Responsibilities include testing, defect minimization, implementing process modifications, building capacity, executing maintenance, developing excursion prevention systems, managing equipment installation, and collaborating with cross-functional teams for technology transfer.

This role is for a Graduate Talent (Physical Design Engineer) at Intel, focusing on Foundational IP (FIP) integration QA within the Foundry Technology Development group. The responsibilities include using industry standard tools for RTL to GDS design flow, scripting and automation, developing new IP-level quality checks, and interacting with EDA tool vendors and internal IP development teams. A key aspect involves applying data analytics and AI/ML techniques to optimize processes and improve quality.

Industrial Engineer specializing in automation for semiconductor manufacturing, focusing on designing and implementing solutions to enhance operational efficiency. The role involves programming (Python), data management (SQL, NoSQL), data analysis, process optimization, and utilizing visualization tools.

Develops and executes product qualification strategies and plans, ensuring adherence to release criteria. Performs risk assessments, defines quality and reliability goals, and contributes to the development and validation of components, boards, and systems. Analyzes specifications, ensures manufacturability, and resolves quality issues. Monitors post-silicon quality results and drives improvements for future products.

Internship role supporting the design, development, and validation of platform hardware and board-level solutions, focusing on component evaluation, PCB layout reviews, and electrical analysis. Requires collaboration with cross-functional teams and application of signal integrity and hardware design principles.

This role focuses on the functional verification of CPU logic, ensuring design specifications are met. Responsibilities include developing IP verification plans, test benches, and simulation models, debugging issues in the presilicon environment, and collaborating with design and architecture teams. The role requires experience with hardware modeling languages and validation/debug experience.

Facilities Mechanical and Controls Engineer responsible for ensuring the reliability, performance, and safety of mechanical, HVAC, and control systems in critical environments. This role involves system design, analysis, troubleshooting, project development, and oversight of integrated facilities management partners and external vendors. Requires a Bachelor's degree in Mechanical Engineering and 5+ years of experience with mechanical and control systems.

Designs, develops, and executes power and performance plans for IPs and SoCs. Identifies, builds, and maintains power, thermal, performance/watt optimizations, and characterizations for IPSoC power and performance goals. Conducts feature analysis from power and performance standpoint and drives to close any gaps between observed behavior and target on platforms in development. Provides recommendations for future architectures. Develops and enhances innovative tools for architectural performance analysis. Develops methodologies and models to drive continuous improvements in optimization of power and performance configurations to meet market requirements. Ensures platform and its components are optimized for performance and power balance. Identifies power activity zones and works with design, architecture, binning/technology, and manufacturing teams on ways to meet power consumption goals. Works cross functionally on analysis, validation, and tuning of architectures and features that advance the state of art in performance and efficiency.

RTL Design & Micro-Architecture Engineer for next-generation scalable data centers supporting AI workloads. Responsibilities include RTL design, coding, simulation, integration, and verification of SoC designs. Requires System Verilog, digital design fundamentals, and simulation tools.

This role involves performing technical power and voltage regulator validation, conducting engineering tests, and supporting engineering activities for Intel's data center innovations. Responsibilities include using lab instrumentation, reading schematics, and maintaining lab operations. The role requires an Associate's degree or higher in Electronics or a similar technical discipline, with at least 1 year of experience in platform rework, soldering, and using oscilloscopes. Intermediate English proficiency is also required.

Experienced Facilities Electrical Engineer responsible for the reliability and continuous improvement of Mega plant electrical systems, including electrical distribution, Medium Voltage systems, low voltage Centre, UPSs, Emergency Generator, and VFDs, supporting safe, reliable, and efficient plant operations. Collaborates with local and global teams to ensure consistency with global standards.

This role focuses on developing and supporting Process Design Kits (PDKs) for Intel Foundry, specifically involving physical layout verification (DRC, LVS, RC extraction) and ESD protection verification using industry-standard EDA tools. The engineer will work on runset development, QA plans, debugging, and enhancing runset quality and usability for advanced Intel process technologies.

This role focuses on developing and supporting Process Design Kits (PDKs) for Intel Foundry, specifically involving physical layout verification (DRC, LVS, RC extraction) and ESD protection verification using industry-standard EDA tools. The engineer will work on runset development, QA plans, debugging, and enhancing runset quality and usability for advanced Intel process technologies.

Senior CPU Physical Design Engineer responsible for the design and delivery of high-performance CPU blocks from RTL to GDS, including synthesis, floorplanning, place and route, CTS, timing closure, and verification. Requires 10+ years of experience with industry-standard EDA tools.

This role is for a CPU Physical Design Engineer at Intel, focusing on the design and delivery of high-performance CPU blocks from RTL to GDS. Responsibilities include executing the full physical design flow, leading verification and sign-off, and optimizing designs for power, performance, and area using industry-standard EDA tools. The role requires a BSc or MSc degree in Electrical or Computer Engineering and at least 7 years of experience in physical design.

The role involves designing, executing, and analyzing experiments in a semiconductor cleanroom to meet engineering specifications for advanced device development. Responsibilities include setting performance targets, assessing silicon readiness, defining test structures, and using data analysis techniques (statistics, data mining) on electrical-test, yield, and fab data to guide future development. Experience with semiconductor materials, fabrication, device physics, and electrical characterization is required, with preferred experience in advanced transistor structures, simulation, SPC/DOE, and analytics/scripting languages.

This role is for a pre-silicon verification engineer on the E-Core CPU team. The primary responsibility is to verify new and existing features for Intel's next-generation CPU IP by developing test plans, test scenarios, simulation components, and functional coverage, and debugging digital simulations. The role requires in-depth computer architecture knowledge and experience with hardware description languages and test bench development.

Senior Facilities Electrical Engineer to lead electrical infrastructure projects and maintain critical electrical systems across Intel's facilities in Malaysia. Responsibilities include designing, implementing, and optimizing electrical systems, ensuring safety, reliability, and compliance with codes and standards. Requires a Bachelor's degree in Electrical Engineering and 7-10 years of experience.

Senior/Staff VLSI Verification Engineer with 11-15 years of experience in complex SoC/ASIC verification, focusing on UVM/System Verilog testbench architecture, Mix signal IP verification strategy, and post-silicon debug. Responsibilities include defining verification plans, mentoring junior engineers, ensuring coverage closure, and collaborating with architects. Experience with formal verification methods is also required.

Intern position focused on platform debug engineering for silicon products, involving functional, power, and performance validation, debugging, and potentially test automation and infrastructure development. Requires familiarity with Python, C/C++, and IA-based PC knowledge. AI experience is preferred but not core.

This role is for a Graduate Talent (Physical Design Engineer) at Intel, focusing on Foundational IP (FIP) integration QA within the Foundry Technology Development group. The responsibilities include using industry standard tools for RTL to GDS design flow, scripting and automation, developing new IP-level quality checks, and interacting with EDA tool vendors and internal IP development teams. A key aspect involves applying data analytics and AI/ML techniques to optimize processes and improve quality.

Lead a team responsible for pre-Silicon functional verification of Intel's latest CPUs, developing test plans, simulation models, and test benches to ensure design requirements are met. Focus on driving strategic tool/flow/methodology initiatives to reduce validation cycle time and ensure first-pass silicon success. Requires technical leadership and managerial experience in pre-Silicon verification environments.

This role focuses on owning and optimizing high-volume manufacturing equipment and processes in the semiconductor industry. Responsibilities include recommending modifications for efficiency, managing maintenance and repair, driving continuous improvement for key performance indicators, and participating in technology transfer to global sites. The role also involves developing excursion prevention systems and managing equipment installation and qualification during factory ramps.

This role focuses on designing, deploying, and managing enterprise-grade Public Key Infrastructure (PKI) solutions, including certificate lifecycle management and automation. It involves integrating PKI with Active Directory and other identity solutions, and ensuring compliance with regulatory requirements. The role requires a strong understanding of X.509 certificates and related protocols.

This role focuses on the Design Technology Platform (DTP) within Intel Foundry Technology Development, specifically in enabling and optimizing EDA reference flow and design flow for advanced process technology. The engineer will work on front-end and back-end design aspects (RTL to GDS, digital/analog, physical design, verification, signoff) and apply AI/ML, CAD software, and data analytics to solve complex problems. The role requires proficiency in Python, C++, TCL, and SKILL, with a background in Electrical Engineering, Computer Engineering, or related STEM fields, and knowledge of VLSI Physical Digital or Custom Design implementation concepts.

Senior Network Systems and Solutions Engineer to support Intel Ethernet products, focusing on technical enablement, debug, and issue resolution for discrete Ethernet controllers and integrated Ethernet IP on SOC. Requires strong analytical, problem-solving, and customer management skills, with experience in high-speed IO debug methods like PCIe or Ethernet.

System Firmware Engineer responsible for developing, maintaining, and optimizing reusable components for seamless integration across Intel's client technology ecosystem. This role involves partnering with customers and vendors, establishing architecture standards, researching and prototyping firmware, evangelizing tools, and driving product improvements. Requires expertise in system firmware, software debug, and low-level software engineering.

Director of Analog Design & Infrastructure Design Automation to lead the development, deployment, and governance of analog/mixed-signal design environments and CAD infrastructure. This role owns EDA tool ecosystems, PDK integration, compute infrastructure, design data governance, and tapeout manifest management to ensure high productivity, reproducibility, and audit readiness across silicon programs.

This role focuses on optimizing Intel's new Graphics Processing Units (GPUs) for modern workloads, emphasizing 3D graphics rendering, workload analysis, hardware/software debugging, and performance bottleneck identification within a multi-disciplinary team.

This role involves the design, development, verification, and delivery of standard cell libraries for Intel's next-generation SoCs and Intel Foundry customers, utilizing leading-edge process technologies. Responsibilities include circuit design, parasitic extraction and optimization, automation flow development, library characterization, and supporting library releases for product teams and external customers. The ideal candidate will have a degree in Electrical Engineering or a related field, knowledge of digital circuit design, familiarity with EDA tools, and scripting experience.