AMD currently has 35 active AI-related job listings. The majority of these roles, 66%, are focused on serving infrastructure. Engineering is the dominant function, with 32 positions. Frequent technical tags include model_serving, inference_infra, and evals, suggesting a focus on the deployment and evaluation of AI models. In the last 30 days, AMD posted 37 new AI roles.
AMD currently has 62 active AI-related roles in our index. The most common open titles are: DC-GPU Performance Modeling Engineer (3), Data Center Engineer (2), Lead Packaging Automation Engineer (2), 3D IC and ADVANCED PACKAGING CAD ENGINEER , AI Framework Engineer. Most positions are in Engineering and Research.
AMD's active AI hiring is concentrated in: serving infrastructure (73%), agents (13%), application (6%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
AMD is hiring AI talent in: United States (27 roles), India (13 roles), China (7 roles), Canada (6 roles).
Job postings at AMD most frequently mention: GPU Computing, Computer Architecture, Compiler Design, Python, Performance Profiling.
In the past 30 days, AMD has posted 55 new AI-related roles.
| Title | Stage | AI score |
|---|---|---|
| Manager Packaging Engineering This role provides leadership for a team of engineers working closely with OSATs and cross-functional partners to enable new product bring-up and sustaining support for various advanced packaging technologies (InFO, EFB/CoWoS-L, CoWoS-S, WLFO, FCBGA, LGA, and chiplet packages). The position is accountable for team execution, technical direction, and delivery of manufacturing readiness, yield improvement, and continuous improvement objectives across backend engineering operations. The ideal candidate brings deep technical expertise in these packaging technologies and proven experience leading high-performing engineering teams. | — | 0 |
| Silicon Design Engineer This role is for a Silicon Design Engineer at AMD, focusing on planning, building, and executing the verification of graphics processor IP. The responsibilities include understanding new features, building test plans, writing directed and random verification tests, debugging failures, and reviewing coverage metrics. The role requires proficiency in IP level ASIC verification, debugging firmware and RTL code, and experience with UVM testbenches, Verilog, System Verilog, C, and C++. |
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| Design Verification Engineer Design Verification Engineer for AMD's graphics processor IP. Responsibilities include planning, building, and executing verification tests, debugging failures, and collaborating with architects and engineers. Requires proficiency in IP level ASIC verification, UVM, Verilog, System Verilog, C/C++, and debugging firmware/RTL. | — | 0 |
| Serdes Analog Mixed-Signal Design Expert This role is for an Analog Mixed-Signal Design Expert at AMD, focusing on Serdes technology. The responsibilities include designing high-performance analog mixed-signal circuit blocks for Serdes, defining micro-architectures, managing power/performance/area budgets, mentoring, and working with verification and validation teams. Experience with ultra-high-speed electrical and optical PHY design, silicon productization, and advanced CMOS PDKs is preferred. The role is in San Jose, CA. | — | 0 |
| Lead Diagnostics Software Engineer, ATE Integration Lead/Principal Diagnostics Engineer to drive shift from post-silicon software validation frameworks and System-Level Tests (SLT) directly into Automated Test Equipment (ATE) and Wafer Sort environments. Design architecture, tooling, and translation methodologies to pack, convert, and stream complex software-driven GFX and compute test cases into production-grade ATE patterns. | — | 0 |
| Director Operations - DC GPU This role provides business oversight for cloud service provider (CSP) and data center (DC) capacity within AMD's Data Center GPU business, focusing on transforming the AI and HPC landscape. Responsibilities include leading cluster acceptance, managing backstop capacity, aligning contracts with operational execution, and coordinating across Finance, Business Development, and Customer Engineering to synchronize plans and outcomes. The role also involves team building as the business scales. | — | 0 |
| Firmware Applications Eng. Develop firmware and software solutions for lab automation, remote control, and orchestration of lab bench instrumentation for AMD's Analog Mixed Signal team, focusing on RF data converters. | — | 0 |
| Silicon Design Engineer This role focuses on developing and maintaining CAD design flows and automation solutions for silicon design at AMD. While it involves assisting in transforming existing workflows into AI-assisted or agentic workflows, the core function is not AI/ML model development but rather engineering productivity through automation and tool support. | — | 0 |
| Senior Emulation Engineer AMD is seeking a Senior Emulation Engineer to join their growing team. This role involves building and bringing up emulation models, developing transactors/BFMs, bringing up PCIe and Ethernet interfaces, and debugging emulation failures. The ideal candidate will have hands-on experience with Mentor Veloce and familiarity with Synopsys ZeBu, strong C/C++ programming skills, and a good understanding of PCIe, Ethernet, or RISC-V processors, along with Verilog/SystemVerilog RTL and verification flows. A Bachelor's or Master's degree in Electrical/Electronics Engineering and 5+ years of relevant experience are required. | — | 0 |
| Senior BIOS & Firmware Applications Engineer Senior BIOS & Firmware Applications Engineer at AMD in Bangalore, India. This role focuses on UEFI BIOS, EDK2, Coreboot, and system-level understanding of embedded systems. Responsibilities include defining customer demos, supporting customers with BIOS issues, developing and running tests for system performance, and investigating hardware protocols. Requires strong programming skills in Python and C/C++ and experience with bootloaders and operating systems like Linux. | — | 0 |
| Pre-silicon Validation Engineer - Emulation This role focuses on pre-silicon validation engineering for complex System-on-Chip (SoC) programs, involving emulation platforms, debugging, and developing test content for hardware features. It is not directly involved in building or researching AI/ML models. | — | 0 |
| Graphics IP RAS Engineer AMD is seeking a mid-level Graphics IP RAS Engineer to work on system reliability and RAS features for next-generation AMD products, including AI accelerators. The role involves designing, analyzing, and improving RAS features, working with architects, and analyzing reliability metrics. Experience with VLSI designs, digital logic, and computer architecture is required. Exposure to AI/ML accelerator architectures and reliability challenges in AI systems is preferred. | — | 0 |
| Senior System RTL Designer/Architect Seeking a senior-level System RTL designer with a strong background or passion for IP architecture to join AMD’s industry-leading team. This role will influence future architecture directions, own complex IP integration strategies, and collaborate closely with world-class experts to deliver groundbreaking silicon solutions. The candidate will balance performance, power, and area while driving schedules and managing risk, working at the forefront of CPU/GPU/SoC innovation. | — | 0 |
| Formal Verification Engineer AMD is seeking a Formal Verification Engineer to join their Infinity Fabric network on-chip verification team. The role involves driving formal verification efforts on complex hardware designs using methodologies like VC Formal and JasperGold, writing SystemVerilog Assertions (SVA), and collaborating with RTL designers and architects. The position requires a strong focus on formal verification, with a minimum of 8 years of experience, and involves mentoring junior engineers. While the role supports AI/ML products, the core function is hardware verification, not AI model development. | — | 0 |
| SR ASIC Design Engineer - Networking/ DPU/ AI Systems Seeking a Senior ASIC Design Engineer to architect and design key blocks for next-generation DPU ASICs targeting AI networking workloads. This role involves the full ASIC development lifecycle from RTL architecture and design through tapeout, silicon bring-up, and mass production. | — | 0 |
| Product Control Engineer (Supply Chain) This role supports prototype sample operations within an engineering and manufacturing environment, coordinating the planning, scheduling, tracking, and delivery of early prototype samples. The candidate will partner with Product Engineering, Supply Chain, and Manufacturing teams to ensure material readiness, resolve supply constraints, and support on-time execution of engineering builds. | — | 0 |
| Hardware System Architecture Fellow - AI & Data Center Networking This role defines and drives end-to-end hardware system architecture for AMD's next-generation AI and data center networking platforms, focusing on AI-NICs, DPUs, switches, and rack-scale networking solutions. It requires deep system expertise, cross-domain technical leadership, and the ability to influence across organizations without direct people management. | — | 0 |
| FPGA Product Application Engineer FPGA Product Application Engineer providing technical support for Ethernet subsystems on Xilinx FPGAs, SoCs, and ACAPs, including tools, drivers, and IP. The role involves collaborating with customers and internal teams to resolve complex technical issues, enabling customer designs, and recommending product improvements. The environment is fast-moving with a focus on emerging technologies. | — | 0 |
| Lead / Staff Embedded Cybersecurity Engineer AMD is seeking an influential software engineer to join their core team, focusing on improving the performance of key applications and benchmarks. The role involves developing and driving security software for sophisticated new technology and product introduction projects (FPGA/SoC, embedded x86), defining security requirements, participating in customer support, reviewing security architectures, and collaborating with engineering teams throughout the product lifecycle. Responsibilities also include contributing to future architecture design, implementing security features like secure boot and cryptographic algorithms, and supporting Secure Development Lifecycle activities such as Threat Modeling and Penetration Testing. | — | 0 |
| Lead Automative Use Cases Validation Engineer Lead Automative Use Cases Validation Engineer at AMD, focusing on validating Automotive Virtualization on AMD platforms. The role involves validating Xen-based virtualization, multi-OS domains, IVI features, graphics, and Ryzen AI workloads across hypervisor, OS domains, drivers, and system level performance. | — | 0 |
| Senior RTL Design Engineer This role is for a Senior RTL Design Engineer at AMD, focusing on the front-end design and integration of Server SoC chips. The engineer will work with architects and IP design teams to define micro-architecture, implement SoC features, and ensure RTL quality. Experience with Verilog, scripting, and SoC design aspects is preferred. | — | 0 |
| Senior Staff Silicon Design Engineer (Analog) This role is for a Senior Staff Silicon Design Engineer specializing in Analog circuits for SerDes products at AMD. The engineer will design and verify high-speed analog circuits for data transmission and recovery, working with the latest CMOS FinFET nodes. Responsibilities include circuit design, verification, layout, floor-planning, and silicon bring-up. The role requires strong analytical skills and collaboration with global teams. | — | 0 |
| SoC Physical Design Lead Seeking a seasoned SoC Physical Design Lead with expertise in delivering high-quality physical design implementations for high-performance, low-power SoCs. Responsibilities include floorplanning, placement, clock tree synthesis, routing, timing closure, PnR strategy optimization for advanced nodes, and leading technical reviews. The role requires collaboration with RTL, architecture, CAD, and verification teams, and influencing design partitioning and hierarchical strategies. Experience with EDA tools and SoC architecture is preferred. | — | 0 |
| Physical Design Lead – Full Chip & Chiplet SoC This role is for a Physical Design Lead at AMD, focusing on the physical design of complex chiplets for advanced technology nodes. The responsibilities include full chip floorplan, PnR closure, timing targets, and signoff functions, while collaborating with various internal and external teams. The role emphasizes PPA (Power, Performance, Area) optimization and schedule adherence. Although the company mentions AI in its mission and for applicant screening, the core of this role is in hardware/silicon design, not AI/ML model development. | — | 0 |
| Senior Low Power Engineer – Physical Design & PnR Flows This role is for a Senior Low Power Engineer focused on Physical Design & Place and Route (PnR) flows at AMD. The engineer will be responsible for developing and automating low-power PnR flows for advanced technology nodes (3nm & 2nm), collaborating with design teams and EDA vendors, and supporting global design teams on P&R and ECO implementations. The role requires expertise in power grid construction, low-power implementation methodologies, and scripting for automation. | — | 0 |
| DFT Engineer Senior Manager Silicon Design Engineer (SOC Lead) at AMD, responsible for driving end-to-end SOC/ASIC execution from concept to tape-out and productization. This role involves leading cross-functional teams, managing project planning, schedule, and deliverables, and ensuring successful silicon checkout and debug. The position requires extensive experience in SOC development, integration, and implementation, with a strong emphasis on leadership, problem-solving, and stakeholder management. | — | 0 |
| MTS Silicon Design Engineer This role is for an MTS Silicon Design Engineer at AMD, focusing on architecting and delivering high-performance ASIC solutions for next-generation data center networking. The work involves the full development lifecycle from architecture to RTL implementation, verification, and validation, with a focus on solving system-level challenges for AI training and inference clusters. The role requires strong ASIC design experience and a system-level mindset, with a preference for experience in high-speed networking, data center, or AI infrastructure silicon. | — | 0 |
| FW/SW Technical Program Manager This role is a Firmware Technical Program Manager at AMD, responsible for leading cross-functional teams in the end-to-end development lifecycle of server platform FW/SW. The role involves managing project execution, collaborating with engineering leads, customers, and manufacturing partners, and ensuring timely delivery of products. While the company mentions AI and data centers, the core responsibilities of this TPM role are focused on traditional firmware and software development program management, not direct AI/ML model development or deployment. | — | 0 |
| Staff Product Development Engineer – System Level Test This role is for a Staff Product Development Engineer focused on system-level testing and characterization of AMD's embedded processor subsystems and other hardened IP. The responsibilities include developing and executing test suites, analyzing performance parameters, driving root-cause analysis, and improving test methodologies. While AI is mentioned as a product area for AMD, this specific role is not directly involved in AI/ML development. | — | 0 |
| MTS Product Development Engineer (SLT) This role is for a MTS Product Development Engineer focused on test hardware infrastructure for AMD's microprocessor and graphics products, including AI accelerators and GPUs. The role involves program ownership, cross-functional leadership, vendor management, and technical support for wafer sort, final test, and system level test. Experience in AI accelerator/GPU testing is a plus. | — | 0 |
| Senior Financial Accountant - Record To Report This role is for a Senior Financial Accountant focused on Record to Report (R2R) processes, including month-end close, ledger maintenance, financial reporting, and automation of financial processes. It requires strong accounting knowledge, analytical skills, and experience with accounting software and automation tools like Excel, VBA, Power BI, Power Query, or RPA. The role is not directly involved in AI/ML development but may contribute to automation initiatives within the finance function. | — | 0 |
| Sr. HRIS Analyst (SAP) This role is for a Sr. HRIS Analyst with expertise in SAP SuccessFactors Employee Central configuration, focusing on designing, configuring, and supporting the module, including integrating and managing 3rd party interfaces. The analyst will act as a subject matter expert, lead requirements gathering, and serve as a liaison between business users and technical teams. | — | 0 |
| Sr. Brand Marketing Specialist This role is for a Sr. Brand Marketing Specialist at AMD, focused on the operational execution of B2B marketing programs for the Commercial PC Segment. The role involves project management, content coordination, and cross-functional alignment to ensure timely and consistent delivery of marketing programs across various channels. Responsibilities include supporting thought leadership programs, developing B2B content, managing customer story programs, and stakeholder management. While the company mentions AI in its mission and future vision, this specific role is in marketing operations and does not involve direct AI/ML development or research. | — | 0 |
| DDR PHY AMS Engineer AMD is seeking a DDR PHY AMS Engineer to support the definition, specification, system simulation, and implementation of future LPDDR IPs. The role focuses on circuit architecture and design of high-speed analog and digital blocks, calibration algorithms, equalization, and developing models for link performance simulations. The candidate will have a strong track record in Memory Phys and High-speed IOs with successful tape-outs and productization, analytical thinking, and effective communication skills. | — | 0 |
| Senior Manager - Analog Design Senior Manager for Analog Design at AMD, focusing on Memory I/O design for future LPDDR IPs. Responsibilities include circuit architecture, specification definition, system simulation, and implementation of high-speed analog and digital blocks. The role involves managing a team, collaborating with various disciplines, and developing models for link performance simulation. | — | 0 |
| QEMU Lead Software Development Eng. Software Development Engineer focused on QEMU based virtual platforms, debugging, optimization, and improving future products. Requires C/C++ and virtual platform experience. | — | 0 |
| Silicon Design Engineer (SERDES) This role is for a Silicon Design Engineer focused on SERDES (Serializer/Deserializer) design for high-performance computing, including AI and data centers. The engineer will implement designs using advanced technology nodes, design circuit blocks, and analyze simulation results. The role requires a Bachelor's or Master's degree in Computer Engineering or Electrical Engineering. | — | 0 |
| EDA Software Development Eng. Software engineer to work on core logic synthesis and optimization technologies within the Vivado FPGA toolchain, improving performance, scalability, and quality of results for AMD's FPGA implementation software. | — | 0 |
| SMTS Packaging Engineer This role focuses on developing and maintaining analytics systems for yield analysis and variability reduction in advanced semiconductor packaging, specifically heterogeneous integration. The engineer will work with manufacturing partners to identify yield issues and deliver actionable solutions, design tools for data analysis, and act as a technical liaison. | — | 0 |
| Power and Performance Engineer AMD is looking for a Power and Performance Engineer to drive next-generation power architecture, firmware, algorithms, and software interfaces across AMD client and handheld SoCs. This role involves defining power-management architecture, collaborating with various teams, and optimizing power efficiency, performance-per-watt, and battery life. The ideal candidate will have strong technical, problem-solving, and communication skills, with experience in profiling, tuning, and algorithm development for complex datasets, as well as system and SoC control firmware. | — | 0 |
| Power and Performance Engineer AMD is seeking a technical leader for their Computing and Graphics business unit to drive next-generation power architecture, firmware, algorithms, and software interfaces across AMD client and handheld SoCs. This role involves defining power-management architecture, collaborating with various engineering teams, and driving innovation from concept to post-silicon validation. The ideal candidate will have strong technical, problem-solving, and communication skills, with experience in profiling software workloads, defining low-level software interfaces, SOC hardware design, and algorithm development. | — | 0 |
| Firmware Architect – High-Speed Interconnect (PCIe / OCI) This role is for a Firmware Architect at AMD, focusing on high-speed interconnects like PCIe and OCI for server platforms. The architect will define and drive firmware architecture, lead innovation in interconnect technologies, collaborate with cross-functional teams, and engage with industry standards. While the company mentions AI and AI-centric solutions, the core responsibilities of this specific role are in firmware architecture for hardware interconnects, not direct AI/ML model development or deployment. | — | 0 |
| Data Center Systems Engineer This role focuses on deploying, validating, and sustaining AMD's CPU and GPU platforms in large-scale data center environments. The engineer will be responsible for system-level debugging, platform reliability, and continuous improvement of tools and processes. The role involves hands-on work with hardware, firmware, and systems in a live data center setting. | — | 0 |
| Technical Program Manager - Windows Security (1 year contract) Technical Program Manager to lead co-engineering programs between AMD, Microsoft, and OEM partners, enabling Windows Security features across AMD platforms. This role requires strong program management skills combined with technical expertise to drive security initiatives from concept to production. | — | 0 |
| Software Performance Engineer Software Performance Engineer at AMD focused on improving the performance of key applications and benchmarks by building and maintaining automation, writing hardware-aware workloads, and developing cross-platform code. The role involves performance optimization and analysis across CPU, GPU, memory, storage, and other devices. | — | 0 |
| FAE Solution Architect FAE Solution Architect specializing in x86 architecture and performance tuning for AMD EPYC platforms, involving technical pre-sales support and customer issue resolution. | — | 0 |
| Design Verification Engineer - IP Seeking a Senior Design Verification Engineer (IP DV) to verify complex, reusable High-Performance Computing (HPC) IP blocks. The role emphasizes adoption of AI-assisted verification techniques to improve debug productivity, regression efficiency, and verification quality for performance-critical IPs. Responsibilities include owning IP-level functional verification, developing verification plans, building UVM environments, creating tests, driving coverage closure, and performing debug. The candidate will leverage AI-assisted verification techniques and mentor junior engineers on AI tools. | — | 0 |
| Section Manager Product Development Engineering - Test Development Section Manager for Product Development Engineering focusing on Test Development for next-generation processors used in high-performance computing, data centers, and enterprise servers. The role involves managing a team of test engineers, developing test content for Automatic Test Equipment (ATE), and collaborating with design and platform engineering to optimize test costs and product quality. | — | 0 |
| Product Development Engineer - Test Development This role is for a Product Development Engineer focused on test development for enterprise processors, including those used in AI and data centers. The engineer will collaborate with design teams to develop, validate, and release test programs for high-volume production, focusing on quality, yield, and test time performance. While the role supports products for AI and data centers, the core function is in test development and manufacturing solutions, not direct AI/ML model development. | — | 0 |
| Silicon Design Verification Engineer (AI debug/analysis) This role is for a Silicon Design Verification Engineer at AMD, focusing on AI debug and analysis within the context of next-generation AMD SoCs. The responsibilities include understanding verification requirements, owning functional verification from planning to sign-off, and implementing testbenches using UVM methodology. While AI is mentioned in the context of debug and analysis, the core craft is silicon design verification, not building AI models or systems. | — | 0 |