Intel
Building- HQ
- Santa Clara, US
- Founded
- 1968
- Size
- 120,000+
- Website
- intel.com
Currently tracking 64 active AI roles, up 216% versus the prior 4 weeks. Primary focus: Serve · Engineering. Salary range $122k–$414k (avg $253k).
Hiring
64 / 66
Momentum (4w)
↑+356 +216%
521 opens last 4w · 165 prior 4w
Salary range · avg $253k
$122k–$414k
USD · disclosed roles only
Tracked since
Feb 3
last role today
Hiring velocityscroll left for older weeks
Jobs (798)
| Title | Stage | AI score |
|---|---|---|
| Chassis IP Design Engineer Seeking an experienced Logic Design engineer for the Intel Chassis Group to deliver component and foundation IPs for SoC chassis. Responsibilities include logic design of routers, switches, arbiters, and protocol conversion bridges, with a focus on high-performance data and control planes. Familiarity with AMBA/CXL protocols and concepts like QoS, access control, and RAS is desired. Experience with AI to assist logic design is a plus. | — | 0 |
| GPU Software Development Engineer Intel is seeking GPU Software Development Engineers to develop software solutions for Media and Video acceleration on Intel's graphics architecture. The role involves developing cross-OS software for encode, decode, and processing, optimizing performance, and creating tools and infrastructure for next-generation GPU advancements. Responsibilities span the entire Intel Media SW stack, from drivers to application layer, including tools, infrastructure, and pre-Si enabling. | — | 0 |
| Back End Cloud Software Developer Experienced Full Stack Cloud Software Developer with a strong backend orientation to design, build, and maintain software components and tools used across the organization. Will work on complex software systems, collaborate with multiple teams, and contribute across the full software development lifecycle. | — | 0 |
| Firmware Development Engineer Develops firmware for Infrastructure Processing Units (IPUs) / Smart-NICs, which offload tasks from host CPUs for cloud data centers. The role involves collaborating with various teams, analyzing code, gathering requirements, developing algorithms, writing and debugging firmware on pre-silicon and silicon platforms, and troubleshooting complex issues. Additionally, the role will leverage AI tools to improve development and validation efficiency. | — | 0 |
| CPU RTL Design Engineer This role is for a CPU Logic Design Engineer responsible for designing and optimizing logic for Intel's processors. The engineer will develop RTL code, define architecture and microarchitecture features, and ensure design integrity for physical implementation. The role requires expertise in Verilog/System Verilog, modern energy-efficient design methods, and scripting languages. | — | 0 |
| Experienced Logic Design Engineer Experienced Logic Designer to join the Ethernet Silicon Engineering Group, focusing on developing state-of-the-art IPU and NIC products for Data Centers. The role involves leading full development cycles from architecture to tape-out, collaborating with various teams, and working with the latest silicon technologies. | — | 0 |
| Senior CPU Pre-Silicon Verification Engineer Senior CPU Pre-Silicon Verification Engineer role focused on leading and executing functional verification of CPU logic using UVM and System Verilog. Responsibilities include developing test benches, analyzing power and timing, debugging issues, and collaborating with cross-functional teams. The role requires experience in digital logic design and scripting languages, with preferred experience in AI agents in verification. | — | 0 |
| CPU Formal Verification Engineer This role focuses on the formal verification of CPU designs, ensuring the quality and reliability of Intel's cutting-edge CPU technologies. The engineer will develop strategies, create abstraction models, collaborate with design teams, and debug issues. While the role mentions AI and machine learning systems as applications of the CPUs, the core function is CPU verification, not AI/ML model development. | — | 0 |
| Senior CPU Circuit Design Engineer Senior CPU Circuit Design Engineer responsible for designing, developing, and building custom digital circuits for CPUs, including memory and caches. This involves floorplanning, circuit design, schematic entry, simulation, and verification to optimize for power, performance, area, timing, and yield. The role also includes creating DFT models, developing memory test tools, and optimizing CPU circuits for low power and performance. Requires a Master's or PhD in Electrical Engineering or related STEM field with significant experience in CMOS circuit design, VLSI, and memory design. | — | 0 |
| SoC Power Thermal Performance Val and Opt Engineer (Temporary Position) This role is for a pre-silicon power and performance engineer responsible for validating new and existing features for Intel's next-generation CPU products. The engineer will develop validation strategies, create test content, debug issues, and report results using simulation and emulation environments, focusing on power-performance correlation. | — | 0 |
| Quantum Computing Measurement Engineer This role is for a PhD-level Quantum Device Measurement Engineer focused on characterizing silicon spin qubits at millikelvin temperatures using electrical measurements and quantum circuit computations. The position involves designing experiments, analyzing device performance, and collaborating to advance Intel's quantum computing roadmap, operating within a research environment focused on semiconductor-based quantum systems. | — | 0 |
| Pre-Silicon Verification Engineer This role focuses on the pre-silicon verification of CPU logic to ensure designs meet specification requirements. Responsibilities include developing IP verification plans, test benches, and verification environments, executing these plans using system simulation models, debugging issues in the presilicon environment, and collaborating with design and architecture teams. The role requires experience with Design Verification and Validation methodologies, UVM, System Verilog, and EDA tools. | — | 0 |
| Sr. Substrates Development and Ramp Engineer Senior engineer focused on supply chain and logistics strategy, process and quality improvements, cost control, production yield optimization, and supplier management within Intel's semiconductor manufacturing environment. Requires deep knowledge of substrate manufacturing, raw materials, packaging technologies, and quality systems. | — | 0 |
| Sr. Substrates Development and Ramp Engineer This role focuses on process and quality improvements within Intel's supply chain and logistics strategy, specifically in the semiconductor manufacturing environment. The engineer will define inspection methodologies, conduct cost and yield studies, explore emerging technologies, and manage supplier relationships to ensure product and commodity performance compliance. The role requires strong analytical problem-solving, supplier management, and quality management skills, with in-depth knowledge of substrate manufacturing processes and operations. | — | 0 |
| Substrates Material Engineer This role focuses on supply chain engineering, optimizing global supply chain strategy, implementing process improvements, and ensuring quality, reliability, and efficiency. It involves collaborating with teams, exploring emerging technologies, defining inspection methodologies, monitoring trends, driving supplier performance, and managing quality excursions. | — | 0 |
| Senior Out-of-Order CPU Architect Senior Out-of-Order CPU Architect at Intel, responsible for defining and driving end-to-end CPU architecture specifications, exploring novel architectures, and influencing cross-functional roadmaps. Requires extensive experience in high-performance CPU design and out-of-order pipeline architecture. | — | 0 |
| Senior CPU Performance Architect This role focuses on designing and specifying CPU microarchitectures, modeling their performance and power characteristics, and collaborating with cross-functional teams to ensure designs meet stringent requirements. It involves developing end-to-end specifications, evaluating tradeoffs, and debugging performance issues from RTL to silicon. | — | 0 |
| Account Executive Saudi Government and Public Sector Account Executive for Intel in Saudi Arabia, focusing on the Government and Public Sector. The role involves growing Intel's business, building sales initiatives aligned with Saudi's 2030 vision to accelerate digital transformation and establish Saudi Arabia as an AI hub, and meeting sales KPIs. Responsibilities include developing customer base strategies, creating business partnerships, managing account plans and stakeholder relationships, and driving sales strategies. Requires experience working with government organizations, understanding the public sector business segment in Saudi Arabia, strong sales and communication skills, and native Arabic fluency. | — | 0 |
| Lead CPU Design Engineer Lead CPU Design Engineer at Intel, responsible for designing and developing logic architecture for CPUs, including RTL coding, simulation, optimization, and collaboration on architecture and microarchitecture features. Supports SoC customers for high-quality integration. | — | 0 |
| Senior Wet Etch Manufacturing Development Engineer Senior Wet Etch Manufacturing Development Engineer role at Intel, focusing on advancing next-generation semiconductor manufacturing processes. Responsibilities include leading process development, optimization, feasibility studies, technology roadmapping, and driving defect reduction and yield improvement in collaboration with internal teams and external suppliers. Requires experience in semiconductor manufacturing, process development, DOE, statistical process control, and root-cause analysis. | — | 0 |
| Design Engineer – AI SoC Development Develops logic design, RTL coding, and simulation for AI SoC development, focusing on power, performance, area, and timing goals. Integrates IP blocks, performs quality checks, and supports silicon bring-up. | — | 0 |
| Design Engineer – AI SoC Development This role is for an RTL Design Engineer focused on developing logic design, RTL coding, and simulation for AI System-on-Chip (SoC) development. The engineer will integrate IP blocks, define architecture and microarchitecture, and optimize logic for power, performance, area, and timing. The role involves close collaboration with verification teams, physical design teams, and IP providers, and supports silicon bring-up and validation. While the products power AI applications, the core craft of the role is hardware design (RTL, SoC integration, timing closure) rather than AI/ML model development or deployment. | — | 0 |
| WLA Yield Analysis Systems Eng This role focuses on adapting, developing, deploying, and sustaining yield analysis software solutions for advanced packaging in semiconductor manufacturing. It involves driving defect data pipeline workflows, collaborating with various engineering teams, and contributing to system integration projects. The role requires a strong foundation in data analysis, programming (Python), and experience with defect and yield analysis applications, with a preference for AI/ML experience in Automated Defect Classification. | — | 0 |
| Test Module Development Engineer The Test Module Development Engineer role at Intel focuses on developing and enabling test technologies for advanced semiconductor packaging, particularly for high-performance computing and AI applications. Responsibilities include test process development, equipment modification, and feasibility studies, with a focus on scaling packaging density and improving performance. The role requires experience in electrical test, statistical controls, and FMEA/DOE methodologies. | — | 0 |
| CPU Physical Design Automation Engineer This role focuses on the automation of CPU physical design, including synthesis, place and route, and signoff analysis. It involves developing and debugging tools and flows for high-performance CPUs, working with EDA vendors, and scripting for design automation. The role requires experience in hardware design, VLSI, and scripting languages like Python, Perl, or Tcl. | — | 0 |
| FVCTO - Formal Verification Engineer This role focuses on formal verification of IP and/or SoC microarchitecture using model checking and equivalence checking algorithms. The engineer will create verification plans, abstraction models, develop formal proofs, and maintain verification infrastructure. Collaboration with RTL developers and architects is key. | — | 0 |
| Board and System Debug Engineer This role is for a Board and System Debug Engineer at Intel, focusing on supporting ODM operations during NPI and HVM ramp. Responsibilities include providing debug support, delivering technical training, testing production failed parts, managing documentation, and collaborating with cross-functional teams. Requires a degree in Electrical/Electronic/Computer Engineering or equivalent, with strong debugging skills and familiarity with debug tools. Scripting knowledge (Python) is a plus. | — | 0 |
| CPU–SoC Mask Layout Designer (Diploma Level Contract role) - Silicon Engineering Group (SiG) Diploma level contract role for a CPU-SoC Mask Layout Designer at Intel, focusing on the training, design, and development of next-generation SOC/CPU. Responsibilities include creating mask layouts, running verification tools, designing floorplans, and troubleshooting layout issues. Requires a Diploma in Electrical and Electronic Engineering and offers hands-on experience in semiconductor design. | — | 0 |
| Manufacturing Operation Manager Manufacturing Operations Manager role at Intel in Malaysia, focused on leading teams to ensure factory operations, equipment maintenance, and repair for optimal performance. Responsibilities include managing workflow, responding to issues, collaborating with engineering, and developing long-term strategies for manufacturing capabilities. Requires a Bachelor's degree and 2 years of experience in manufacturing operations, with expertise in semiconductor manufacturing principles and factory floor planning. | — | 0 |
| Sr. Infrastructure Engineer - Observability and Monitoring This role focuses on deploying, configuring, and managing enterprise observability and monitoring infrastructure, specifically Elastic, Logstash, Kibana, and Kafka environments. It involves implementing automation scripts for efficiency and reliability, optimizing Elasticsearch performance, designing data ingestion pipelines, and creating dashboards for operational insights. The position requires expertise in infrastructure engineering and scripting languages. | — | 0 |
| Senior Phase Gates Engineer This role is for a Senior Phase Gate Engineer at Intel Foundry, focusing on managing and improving the phase gate process for semiconductor manufacturing. The role involves driving strategic outcomes, orchestrating cross-functional teams, optimizing performance, enabling innovation, and solving complex technical and business problems within the semiconductor industry. While the company emphasizes its role in the 'AI-Era', the core responsibilities are in program and process management for semiconductor production, not direct AI/ML model development or deployment. | — | 0 |
| IP Design Verification Engineer Intel is seeking an IP Design Verification Engineer with 6+ years of experience in Pre-Si verification. The role involves developing IP verification plans, test benches, and simulation models to ensure design specifications are met. Responsibilities include debugging issues, collaborating with cross-functional teams, and maintaining verification infrastructure. Requires strong skills in Specman “e” / System Verilog and understanding of verification methodologies. | — | 0 |
| Sr. Substrates Development and Ramp Engineer This role supports management in improving Intel's supply chain and logistics strategy, focusing on process and quality improvements, cost control, production yield, and exploring emerging technologies. The engineer will define material inspection methodology, support product long-range planning, lead supplier selections, perform risk mitigation, establish control standards, monitor KPIs, drive supplier process validation, and manage quality excursions. | — | 0 |
| Manufacturing Operators Manufacturing Operators at Intel in Malaysia are responsible for performing product manufacturing and assembly tasks, operating equipment, collecting and evaluating operating data, and driving process improvements to meet industry standards and customer specifications. The role involves working in shifts and requires basic computer literacy and problem-solving skills. | — | 0 |
| Advanced Packaging Materials Supply Chain Engineer Supply Chain Engineer at Intel responsible for developing and executing supply chain strategies, ensuring supplier process and product readiness, and managing supplier relationships to meet cost, quality, availability, technology, and environmental goals within the semiconductor industry. | — | 0 |
| Power and Performance Architect This role focuses on defining and optimizing power and performance targets for Intel's products, collaborating with various engineering teams. Responsibilities include driving SoC PnP projections, developing power and performance models, and defining targets across development phases. The role requires strong system-level thinking, technical judgment, and leadership skills. | — | 0 |
| Lead Design Verification Engineer Lead Design Verification Engineer for Intel's Silicon Chassis team, responsible for defining and executing verification strategy for critical chassis and interconnect IP programs. Requires deep DV expertise, protocol and memory subsystem knowledge, and collaboration across design, software, and methodology teams. The role involves leading the development of verification environments, driving functional signoffs, and mentoring engineers. AI-assisted workflows are integrated into daily development. | — | 0 |
| Factory Automation Support Engineer - Shift 5 Support Engineer for Factory Automation Applications, Databases, or Platforms/Infrastructure in semiconductor manufacturing factories. Requires troubleshooting, project work, and development in Java, Python, C#, or other object-oriented programming languages. Experience in Semiconductor Process Engineering, Semiconductor Manufacturing, or Factory Automation is required. | — | 0 |
| Graduate Talent (Memory Design) This role is for a Graduate Talent in Memory Design at Intel, focusing on the pathfinding and development of advanced memory technology and circuits. Responsibilities include PPA optimization, product/design enablement, IC layout, memory array/IP design, circuit innovation, testchip design, and pre/post-Si validation. The role requires a Bachelor/Master/PhD in Electrical Engineering or related STEM field, proficiency in programming languages like Python, and familiarity with Unix/Linux. | — | 0 |
| Graduate Talent (PDK QA Engineer) This role is for a Graduate Talent (PDK QA Engineer) within Intel's Design Technology Platform (DTP) organization, focusing on the Process Design Kit (PDK) group. Responsibilities include validating PDK quality for custom design components and developing regression test suites to ensure PDK accuracy across various EDA flows and process nodes. The role requires knowledge of VLSI semiconductor devices, electronic circuits, and familiarity with EDA tools. | — | 0 |
| Graduate Talent (Platform Hardware Design Engineer) Seeking a Graduate Talent Platform Hardware Engineer to support the architecture, bring-up, validation, and execution of platform hardware for test chip and validation programs. Responsibilities include board-level execution, power-on, debug, test plan execution, data collection, and documentation. The role involves collaboration with cross-functional teams and support for sustaining activities. | — | 0 |
| Reliability Verification Technical Manager This role manages a team of engineers responsible for developing, validating, and optimizing Process Design Kits (PDKs) and design methodologies for Intel's advanced process nodes. The focus is on ensuring the quality and robustness of PDK collateral for internal and external design communities, particularly in ASIC EM/IR, ESD PERC, and High Voltage domains. The manager will drive innovation in tools and flows, collaborate with manufacturing and design teams, and conduct root cause analyses for issues. | — | 0 |
| Graduate Talent (PDK QA Engineer) This role is for a Graduate Talent (PDK QA Engineer) at Intel, focusing on the Quality validation of ASIC Design components within the Design Technology Platform/Process Design Kit (PDK) group. Responsibilities include developing regression test suites, executing them to validate PDK elements like pcells and techfiles, developing layout designs for verification, and developing circuit designs for simulations. The role requires proficiency in programming languages like TCL, Perl, or Python, and Unix/Linux knowledge. | — | 0 |
| Analog and Mixed Signal Design Engineer Designs and develops analog and mixed-signal circuits for Intel's Advanced Design Foundational IP Organization, focusing on pathfinding and development of advanced logic, memory, and analog/mixed-signal circuits for Intel's process technology. | — | 0 |
| Accountant Accountant role at Intel in Malaysia, focusing on preparing, analyzing, and validating financial records, ensuring compliance with global financial standards (IFRS, US GAAP), managing auditor interactions, and driving process improvements. Requires proficiency in accounting principles, financial systems (SAP S4, SQL, Power BI), and SOX compliance. | — | 0 |
| Graduate Talent (Memory Design) This role is for a Graduate Talent in Memory Design at Intel, focusing on the pathfinding and development of advanced memory technology and circuits. Responsibilities include PPA optimization, product/design enablement, IC layout, memory array/IP design, circuit innovation, testchip design, and pre/post-Si validation. The role requires a Bachelor/Master/PhD in Electrical Engineering or related STEM field, proficiency in programming languages like Python, and familiarity with Unix/Linux. | — | 0 |
| Graduate Talent (Memory Design) This role is for a Graduate Talent in Memory Design at Intel, focusing on the pathfinding and development of advanced memory technology and circuits. Responsibilities include PPA optimization, product/design enablement, IC layout, memory array/IP design, circuit innovation, testchip design, and pre/post-Si validation. The role requires a Bachelor/Master/PhD in Electrical Engineering or related STEM field, proficiency in programming languages like Python, and familiarity with Unix/Linux. | — | 0 |
| Formal Verification Lead Lead formal verification efforts for complex CPU designs, developing environments, creating models and properties, analyzing failures, and guiding team members. Requires Master's degree and 8+ years of experience in formal verification, with proficiency in relevant tools and languages. | — | 0 |
| CPU Formal Verification Lead Lead formal verification efforts for complex CPU designs (i9, i7, i5, Xeon processors). Develop environments, create models and properties, analyze failures, and guide team members. Stay updated on formal verification technologies and develop new methodologies. | — | 0 |
| Semiconductor Manufacturing Engineer Semiconductor Manufacturing Engineer responsible for operational support, process optimization, and new product introduction in a fabrication facility. This role involves analyzing factory metrics, developing manufacturing plans, and collaborating with engineering and automation teams to ensure efficient production and delivery schedules. | — | 0 |