Intel
- HQ
- Santa Clara, US
- Founded
- 1968
- Size
- 120,000+
- Website
- intel.com
Intel currently has 84 active job listings related to artificial intelligence. The majority of these roles, 51%, are focused on serving infrastructure, with agents representing another significant portion at 24%. Engineering is the most frequent function for these positions. The company is actively hiring in the United States, China, and Mexico. Frequent technical tags include model serving, inference infrastructure, and agent orchestration. In the last 30 days, Intel has added 73 new AI roles, representing a 52% increase compared to the previous 30-day period.
Currently tracking 56 active AI roles, down 27% versus the prior 4 weeks. Primary focus: Serve · Engineering. Salary range $122k–$414k (avg $253k).
Intel currently has 59 active AI-related roles in our index. The most common open titles are: AI Software Engineering Intern (3), AI Software Engineer Intern (2), GenAI Software Solutions Engineer (2), Graduate Talent (GenAI Software Solutions Engineer) (2), AI Algorithm Engineer. Most positions are in Engineering and Research.
Intel's active AI hiring is concentrated in: serving infrastructure (49%), agents (29%), application (8%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
Intel is hiring AI talent in: United States (28 roles), China (7 roles), Mexico (6 roles), Malaysia (6 roles).
Job postings at Intel most frequently reference: model serving, inference infra, agent orchestration, rag, tool use.
In the past 30 days, Intel has posted 28 new AI-related roles. That is a -63% change versus the prior 30 days (75 → 28).
| Title | Stage | AI score |
|---|---|---|
| Process and Equipment Engineer (Contract) This role focuses on owning and optimizing high-volume manufacturing equipment and processes in the semiconductor industry. Responsibilities include recommending modifications for efficiency, managing maintenance and repair, driving continuous improvement for key performance indicators, and participating in technology transfer to global sites. The role also involves developing excursion prevention systems and managing equipment installation and qualification during factory ramps. | — | 0 |
| Identity Security - PKI Engineer This role focuses on designing, deploying, and managing enterprise-grade Public Key Infrastructure (PKI) solutions, including certificate lifecycle management and automation. It involves integrating PKI with Active Directory and other identity solutions, and ensuring compliance with regulatory requirements. The role requires a strong understanding of X.509 certificates and related protocols. | — | 0 |
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| Senior Member of Technical Staff (CMP) Engineer Senior Member of Technical Staff (CMP) Engineer at Intel Foundry responsible for driving module ownership and technical leadership in Chemical Mechanical Planarization (CMP) process development for advanced logic technologies. This role involves leading process development from concept to HVM implementation, cross-node standardization, problem resolution, and customer-centric delivery. | — | 0 |
| TA/Chief of Staff for CEG This role is a Chief of Staff/Technical Assistant for Intel's Central Engineering Group (CEG), focusing on strategic initiatives, operational excellence, and stakeholder management. It requires strong business acumen, program management skills, and a deep understanding of Intel's technology and business strategies, but is not directly involved in AI/ML development. | — | 0 |
| Network Systems and Solutions Engineer Senior Network Systems and Solutions Engineer to support Intel Ethernet products, focusing on technical enablement, debug, and issue resolution for discrete Ethernet controllers and integrated Ethernet IP on SOC. Requires strong analytical, problem-solving, and customer management skills, with experience in high-speed IO debug methods like PCIe or Ethernet. | — | 0 |
| System Firmware Engineer System Firmware Engineer responsible for developing, maintaining, and optimizing reusable components for seamless integration across Intel's client technology ecosystem. This role involves partnering with customers and vendors, establishing architecture standards, researching and prototyping firmware, evangelizing tools, and driving product improvements. Requires expertise in system firmware, software debug, and low-level software engineering. | — | 0 |
| Senior Process Engineer - Dry Etch Senior Process Engineer - Dry Etch role focused on technology development and manufacturing of semiconductor fabrication processes, specifically dry etch for advanced nodes like 18A and GAA FETs. Responsibilities include process integration, optimization, feasibility studies, and collaboration with development and manufacturing teams to support foundry customers. | — | 0 |
| Senior Metals Deposition Engineer Senior Metals Deposition Engineer role focused on driving process performance and manufacturability for advanced metals deposition modules in semiconductor manufacturing. This role involves bridging Technology Development, High Volume Manufacturing, and Customer Engineering, requiring technical problem-solving, collaboration across teams, and staying current with industry trends. | — | 0 |
| Advanced Packaging Supplier Technology Development Program Manager Program Manager for Advanced Packaging technology, focusing on supplier capacity expansion and qualification to meet foundry customer demand for EMIB-T technology. Requires project management, technical risk assessment, and supplier management skills. | — | 0 |
| Sr Manager, Treasury Capital Markets Senior Manager role in Intel's Capital Markets Group, managing a $50B debt portfolio, asset liability management, shareholder distributions, credit facilities, and relationships with credit rating agencies and banking partners. Responsibilities include capital structure planning, board presentations, and ensuring regulatory compliance in collaboration with legal, tax, and accounting teams. Requires strong financial analysis, problem-solving, and communication skills. | — | 0 |
| Account Sales This is an account sales role focused on driving Intel product adoption, building customer partnerships, and generating revenue. Responsibilities include account planning, identifying growth opportunities, converting design wins to revenue, and gathering customer feedback. It requires understanding customer technology and business strategies, and translating needs into technical value propositions. The role is commissioned and directly tied to revenue generation and customer success. | — | 0 |
| Senior Account Sales Manager Senior Account Sales Manager responsible for leading a sales team, understanding customer technology needs, building partnerships, and securing design wins to drive revenue and expand Intel's product adoption. This role focuses on account planning, revenue generation, customer feedback analysis, and influencing customer decisions for long-term growth. | — | 0 |
| Director-Analog Design & Infrastructure Design Automation Director of Analog Design & Infrastructure Design Automation to lead the development, deployment, and governance of analog/mixed-signal design environments and CAD infrastructure. This role owns EDA tool ecosystems, PDK integration, compute infrastructure, design data governance, and tapeout manifest management to ensure high productivity, reproducibility, and audit readiness across silicon programs. | — | 0 |
| GPU Performance Engineer This role focuses on optimizing Intel's new Graphics Processing Units (GPUs) for modern workloads, emphasizing 3D graphics rendering, workload analysis, hardware/software debugging, and performance bottleneck identification within a multi-disciplinary team. | — | 0 |
| Graduate Talent (Standard Cell Library Design Engineer) This role involves the design, development, verification, and delivery of standard cell libraries for Intel's next-generation SoCs and Intel Foundry customers, utilizing leading-edge process technologies. Responsibilities include circuit design, parasitic extraction and optimization, automation flow development, library characterization, and supporting library releases for product teams and external customers. The ideal candidate will have a degree in Electrical Engineering or a related field, knowledge of digital circuit design, familiarity with EDA tools, and scripting experience. | — | 0 |
| Graduate Talent (Standard Cell Library Design Engineer) This role involves the design, development, verification, and delivery of standard cell libraries for Intel's next-generation SoCs and Intel Foundry customers, utilizing leading-edge process technologies. Responsibilities include circuit design, parasitic extraction and optimization, automation flow development, library characterization, and supporting library releases for product teams and external customers. The ideal candidate will have a degree in Electrical Engineering or a related field, knowledge of digital circuit design, familiarity with EDA tools, and scripting experience. | — | 0 |
| Graduate Talent (Physical Design) This role involves the physical design implementation of custom IP and SoC designs from RTL to GDS, covering synthesis, place and route, timing analysis, power distribution, reliability, and verification/signoff. It also includes optimizing designs for power, frequency, and area, and contributing to the development of physical design methodologies and flow automation. | — | 0 |
| Graduate Talent [E-core (Atom) CPU Circuit Design] Designs, develops, and builds custom digital circuits for a CPU, including memory and caches. This involves floorplanning, schematic entry, simulation, and verification to optimize for power, performance, area, timing, and yield. The role also includes creating DFT models, developing memory test tools, and collaborating cross-functionally to resolve design issues. Familiarity with EDA tools and advanced CMOS technology is required. | — | 0 |
| GPU Validation Engineer The GPU Validation Engineer role at Intel focuses on the pre-silicon validation of GPUs, including their interaction with media, display, and system-level features. The role involves defining, developing, and performing functional validation, applying various tools and techniques to meet performance, power, and area goals. Responsibilities include reviewing design changes, developing validation methodologies, executing validation plans, debugging pre-silicon issues, influencing validation infrastructure, publishing reports, and collaborating with architecture, design, verification, and platform teams. | — | 0 |
| Accounting Technical Specialist The Accounting Technical Specialist role at Intel in Malaysia focuses on end-to-end statutory audit processes, governmental filings, ensuring compliance with accounting standards (IFRS, US GAAP), managing month-end/quarter-end close activities, and acting as a technical advisor for complex accounting issues and upcoming regulations. The role also involves supporting legal entity restructuring, collaborating with internal stakeholders, leading projects, and potentially participating in SAP S4 system design and implementation. | — | 0 |
| Senior CPU Verification Engineer Senior CPU Verification Engineer responsible for ensuring the functional correctness of CPU logic designs through pre-silicon verification methodologies, including developing UVM-based testbenches, running simulations, debugging issues, and collaborating with architects and designers. | — | 0 |
| Graduate Talent (Memory Design) Memory Design Graduate Talent role at Intel, focusing on pathfinding, development, and optimization of advanced memory technology and circuits. Responsibilities include DTCO, product enablement, IC layout, memory array/IP design, circuit innovation, and pre/post-Si validation. | — | 0 |
| Practical Engineering Student for Intel Kiryat Gat Practical Engineering student role in a semiconductor manufacturing facility, focusing on operating and supporting advanced equipment, learning maintenance, and assisting engineering teams with troubleshooting and process improvement. Requires enrollment in a Mechanical or Mechatronics Practical Engineering program with at least three semesters remaining. | — | 0 |
| Thermal Engineering Intern Seeking a Thermal Intern to support thermal engineers with lab testing, data collection, and documentation. Responsibilities include assisting with thermal modeling setup, analyzing airflow and temperature data, and documenting results. The role involves working within a cross-functional Architecture/Engineering team focused on Co-Engineering Custom Design Systems with strategic customers and driving new platform-level innovations. | — | 0 |
| Semiconductor Foundry Demand Senior Business Strategist Develops and maintains bottom-up wafer demand models for assigned end markets, including AI accelerators, and delivers comprehensive analyses of competitive dynamics within the advanced node foundry market. Authors white papers with strategic recommendations for Intel Foundry. | — | 0 |
| Semiconductor Foundry Demand Business Strategist Develops market intelligence and demand models for semiconductor foundry services, focusing on end markets like AI accelerators and discrete GPUs, to provide strategic recommendations for Intel Foundry. | — | 0 |
| Physical Design Engineer Physical Design Engineer responsible for the implementation of custom IP and SoC designs from RTL to GDS, covering synthesis, place and route, timing analysis, and verification for Intel's advanced process nodes. | — | 0 |
| SoC Power and Performance Engineer Senior Power and Performance (PnP) Engineer responsible for PnP product execution focused on measurements, analysis, and projections/estimates of Intel's unlaunched notebook and desktop products. Will help influence OEM customers, internal marketing teams, internal engineering teams, debug Intel silicon/platform on PnP issues, and be an integral part for Intel product launches. | — | 0 |
| E-Core CPU Design Automation Engineer This role is for a Design Automation Engineer focused on supporting and developing CAD solutions for Intel's E-core CPU design. Responsibilities include defining and implementing verification flows for backend signoff, working with designers on various verification aspects, developing and testing EDA tools, and creating scripts to analyze design methodologies. A preferred qualification includes using Machine Learning/AI methods for circuit design automation to improve performance and power. | — | 0 |
| System Validation Engineer System Validation Engineer at Intel responsible for defining, developing, and performing functional validation for Thunderbolt technology. This involves engaging from early product stages to define HW/FW hooks, developing methodologies and test plans, executing plans, and collaborating with engineers for design optimization, troubleshooting, and failure analysis. The role requires FPGA and Silicon debug, understanding the full stack (HW/FW, driver, OS), and applying various tools and techniques to ensure validation coverage. The engineer will publish validation reports, work with cross-functional teams (architecture, design, verification, etc.) to improve debug and validation strategies, and develop content for IP interactions. The role also involves engaging in all product life cycle phases, developing and validating content and infrastructure, and performing bug hunts in simulation, emulation, and FPGAs to ensure silicon readiness. | — | 0 |
| E-Core/Quark CPU Pre-Silicon Validation Design Engineer This role focuses on the pre-silicon validation of CPU logic, developing verification plans, test benches, and simulation models to ensure design specifications are met. It involves debugging, root-causing issues, and collaborating with architects and developers to improve verification of complex features. The position requires a Bachelor's degree in Electrical/Electronics or Computer Engineering with knowledge of computer system architecture and digital logic design. | — | 0 |
| Compiler Engineer Intel is seeking an experienced MSVC Compiler Engineer to work on core compiler backend components, drive performance improvements, and collaborate with hardware architecture teams for Intel platforms. Responsibilities include designing, implementing, and maintaining compiler backend optimizers and code generation, developing optimization techniques, and collaborating with hardware architects. The role also involves testing, validation, performance bottleneck analysis, staying current with compiler research, and mentoring junior engineers. | — | 0 |
| Senior Physical Design Application Engineer Senior Physical Design Application Engineer at Intel Foundry, focusing on providing technical support for Cadence tool suites, PDKs, and digital reference flows to customers. The role involves driving quality improvements in design kits, supporting successful tape-outs, and developing/optimizing digital design implementation flows for advanced CMOS processes. | — | 0 |
| IP Enablement Application Engineer Intel Foundry Services is seeking an IP Enablement Application Engineer to provide technical support to customers on IP integration challenges. This role involves working with design teams and customers throughout the IP development lifecycle, resolving issues, and providing hands-on debug. Responsibilities include customer support, cross-functional collaboration, developing integration methodologies, and creating training materials. The role requires strong problem-solving skills and experience in SOC IP Integration, RTL design, and ASIC/SoC development. | — | 0 |
| Memory Design Application Engineer This role provides technical support to Intel Foundry Services customers on memory compiler generation and integration for advanced semiconductor applications, focusing on resolving integration issues, improving collaterals, and guiding memory design methodologies for aerospace, defense, and government customers. The role requires expertise in memory design and integration, customer engagement, and problem-solving within a collaborative environment. | — | 0 |
| Senior Analog / Mixed Signal Application Engineer Senior Analog/Mixed Signal Application Engineer at Intel Foundry Services, providing technical support to customers on PDKs, design methodologies, and implementation flows for semiconductor manufacturing, focusing on successful customer tape-outs and quality improvements in design kits and documentation. | — | 0 |
| DFT Application Engineer DFT Application Engineer providing technical support to Intel Foundry Services customers on PDKs, DFT/DFM insertion, and ATPG validation methodologies for Aerospace, Defense, and Government (ADG) customers. The role involves customer technical support, driving quality improvements in DFT/DFM and ATPG validation methodology, and developing technical content and training. | — | 0 |
| Experienced Post Silicon Validation Engineer Experienced Post Silicon Validation Engineer needed to join Intel's CPU CORE Validation team. Responsibilities include validating product features, debugging functional bugs, and working with architecture and design teams. Requires BSC/MSC in Electrical Engineering, Computer Engineering, Software Engineering, or Computer Science with 2-7 years of expertise in Post Silicon chip functional validation. Python and Assembly programming skills are advantageous. | — | 0 |
| Graduate Talent (Solution Enabling Engineer) This role focuses on enabling Intel software products by providing debugging support, contributing to solution development, and performing testing and validation. It requires programming skills in Python, C, C++, and JavaScript. | — | 0 |
| Linux Driver Wifi developer Software developer for Linux Wifi team at Intel, contributing to open-source code for Intel's wifi devices on Linux. Role involves working on the Linux kernel in C, focusing on networking, PCI, and the wifi stack. | — | 0 |
| Senior Formal Verification Engineer – AI SoC Development This role focuses on ensuring the functional correctness of complex digital designs for AI SoCs using formal methods. The engineer will own the formal verification strategy, develop environments, write properties, collaborate with design teams, and contribute to pre-silicon verification and post-silicon debug. The role also involves defining verification plans, executing them using simulation and emulation, debugging issues, and incorporating security verification activities. | — | 0 |
| Senior Photonic-Integrated-Circuit Engineer Senior Photonic-Integrated-Circuit Engineer at Intel, responsible for the end-to-end development of silicon photonic integrated circuits, from concept and design to high-volume manufacturing. This includes system-level planning, component design and optimization, simulation, layout, testing, validation, and performance debug, working cross-functionally with various teams and foundries. Requires expertise in PIC design, simulation tools (Lumerical, RSoft, Matlab, Python), and layout tools (Cadence, KLayout). | — | 0 |
| Atom CPU Layout Design Engineer Intel is hiring an Atom CPU Layout Design Engineer in Guadalajara, Mexico. The role involves the physical implementation of memory compilers, custom IP blocks, and layout partitions for future-generation Intel Atom microprocessors. Responsibilities include ensuring best-in-class layout methodologies, performing complex physical design assignments, interpreting schematics, contributing to the full design flow, and partnering with SoC teams. The ideal candidate will have 2+ years of layout design experience and strong analytical skills. A Master's degree and experience with VLSI/CMOS logic circuit design are preferred. | — | 0 |
| TFM and PPA Physical Design Engineer This role is for a TFM and PPA Physical Design Engineer in the CPU team at Intel, focusing on developing and automating backend physical design flows for high-performance CPUs. Responsibilities include synthesis, place-and-route, floor planning, timing analysis, power consumption estimation, and working with EDA vendors to enhance tool capabilities. Requires a Master's degree with 6+ years of experience or a Bachelor's degree with 8+ years of experience, with expertise in physical design tools and scripting. | — | 0 |
| Memory Debug Engineer Memory Debug Engineer at Intel, focusing on enabling, validating, and debugging memory subsystems for next-generation Intel IA-based platforms. Responsibilities include strategic oversight of memory IO interfaces, ensuring electrical performance and stability, leading complex issue resolution, and optimizing Memory Reference Code (MRC). Requires BS/MS/PhD in EE/CE with 4+ years of experience in DDR/LPDDR protocols and debug tools like oscilloscopes and logic analyzers. | — | 0 |
| Platform Power and Performance Architect Intel is seeking a Platform Power and Performance Architect to influence and drive technical direction across Intel and industry for client platforms. Responsibilities include developing test plans for deep learning models, defining and conducting power/performance experiments, analyzing workloads using tracing techniques, developing tools for analysis, and researching power optimization technologies. The role requires a Bachelor's or Master's degree in a related field with significant experience in computing system architecture, processor architecture, power management, or thermal management. | — | 0 |
| PHY Technology Enablement Engineer This role focuses on enabling next-generation high-speed I/O technologies by leading PHY and SerDes IP validation and integration for future platforms. Responsibilities include pre-silicon validation of PHY IPs for standards like PCIe Gen7 and Ethernet 1.6T, evaluating internal and third-party IPs, defining IP requirements, developing integration guidelines, and debugging test chips. Requires a Bachelor's degree in Electrical Engineering with 3+ years of experience in electrical validation and debugging, and a solid understanding of SerDes architectures. | — | 0 |
| NPI Integrator This role focuses on integrating new products into Intel's manufacturing processes, managing technology transfers, improving quality and yield, and ensuring readiness for high-volume production. It involves data analysis, problem-solving, and cross-functional collaboration. | — | 0 |
| Soc Functional Validation Engineering Intern Internship role supporting SoC (System on Chip) development activities, focusing on learning about functionality, performance, and quality validation of integrated SoCs. Responsibilities include assisting in developing and executing Pre-Silicon validation plans and supporting Post-Silicon validation activities under supervision. | — | 0 |