Intel

This role focuses on the integration and debug of Mixed Signal Intellectual Property (IP) for Intel's Hard IP Development Group. Responsibilities include partnering with customers and design teams, developing test plans using AI-driven tools and scripting, conducting design reviews, performing simulations, leading silicon validation and debug, and driving root cause analysis for IP-related issues. The role requires experience in IP integration, pre-silicon verification, post-silicon validation, and debug of serial or parallel IOs, along with lab hardware and software experience.

This role focuses on enabling and debugging mixed-signal IP (Intellectual Property) for Intel's Hard IP Development Group. Responsibilities include customer support, IP documentation, integration and debug support, developing test plans using AI-driven tools and scripting, conducting design reviews, and performing signal/power integrity simulations. The role also involves silicon validation, leading issue identification and resolution, and root cause analysis. The ideal candidate will have experience in IP integration, pre-silicon verification, post-silicon validation, and debug of serial or parallel IOs, with strong lab hardware/software skills and experience with test equipment.

This role is for an MDM Software Application Development Engineer at Intel, focusing on designing, configuring, and developing SAP MDG and S4 HANA solutions. Responsibilities include defining software application solutions, recommending design choices for manageability and scalability, identifying business requirements, configuring systems, collaborating with stakeholders, performing pathfinding, and troubleshooting production issues. The role also involves acting as a technical lead for subsystems and managing projects. The ideal candidate will have extensive experience with SAP MDM and S4 HANA, ABAP, SAP Fiori, and SQL queries, with preferred experience in data cleansing, governance, and integration.

Industrial Engineer responsible for developing metrics to measure factory capacity and output, identifying bottlenecks, and implementing plans for facility modifications and operating methods. The role involves integrating new products, analyzing capacity requirements, leading teams to remove roadblocks, conducting capacity assessments, validating product performance, studying equipment mechanisms, designing equipment metric models, and providing solutions for virtual factory capacity and resource optimization to meet schedules and cost targets. Requires structured problem solving, data analysis and visualization, and experience in capacity improvement projects.

Develops and establishes process flow, FMEA assessment, procedures, drawings review, and equipment configuration for direct lid/stiffener attach module in semiconductor packaging. Selects and develops materials and equipment, conducts experiments, establishes process control systems, and supports new factory start-up.

This role focuses on the design, implementation, verification, and support of EDA (Electronic Design Automation) tools and hardware design methodologies. The engineer will work on optimizing design automation workflows, improving efficiency, power, and performance of hardware designs, and collaborating with EDA vendors. The role requires strong programming and scripting skills, and a deep understanding of digital design processes.

Internship role focused on manufacturing operations within Intel's Advanced Packaging Technology Manufacturing (APTM) plant. Responsibilities include equipment setup, monitoring production processes, quality checks, and assisting with troubleshooting and optimization. The role involves hands-on experience in a fast-paced, challenging environment supporting wafer movement and production goals, with a focus on learning and skill development.

This role is for a CPU Physical Design Engineer at Intel. The engineer will be responsible for the physical design implementation of custom CPU designs from RTL to GDS, including synthesis, place and route, clock tree synthesis, static timing analysis, and power/clock distribution. The role involves verification and signoff, optimization for power, frequency, and area, and working with EDA vendors to enhance tool capabilities. While the company works in AI, this specific role focuses on the hardware design of CPUs that may be used in AI applications, rather than the AI/ML development itself.

The Identity Security - PKI Engineer role at Intel focuses on designing, deploying, and managing enterprise-grade Public Key Infrastructure (PKI) solutions. This involves leading certificate lifecycle management, automating PKI tasks, integrating PKI with various platforms, and enforcing security policies. The role requires a Bachelor's or Master's degree and relevant experience in PKI integration, X.509 certificates, and key management standards. A US Government Security Clearance is required.

This role involves the physical design implementation of custom CPU designs from RTL to GDS, covering synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power/noise analysis. It also includes verification and signoff, working with EDA vendors, and optimizing CPU designs for power, frequency, and area. The role requires collaboration with various engineering teams and participation in methodology improvements.

This role involves the physical design implementation of custom CPU designs from RTL to GDS, covering synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power/noise analysis. It also includes verification and signoff, working with EDA vendors, and optimizing CPU design for power, frequency, and area.

This role is for an Enterprise Systems Analyst at Intel, focusing on supply chain transformation and the internal foundry model. The analyst will work with Windchill PLM, gather requirements, document processes, develop training, and support end-users. The role involves data and system management, and integration with other enterprise systems. While the company mentions AI, this specific role is focused on PLM and supply chain systems, not direct AI/ML model development or deployment.

This role focuses on the development and validation of tools, flows, and collaterals for standard cell library reliability, including electromigration, thermal effects, and voltage drop. Responsibilities involve workflow optimization, vendor and foundry engagement, and documentation/collateral generation and validation.

This role focuses on graphics driver/application validation and debug, integrating upcoming graphics features, triaging failures, and developing debug tools to improve graphics validation efficiency. It involves scaling across display, media, 3D, compute, and power conservation components, and enabling new features for AI domains to improve functionality and performance on graphics products.

Develops logic design, RTL coding, and simulation for mixed signal and/or highspeed IPs for integration in full chip designs. Participates in architecture and microarchitecture definition, applies strategies for mixed signal designs, writes RTL, and optimizes logic to meet power, performance, area, and timing goals. Reviews verification plans, resolves failing RTL tests, and supports SoC customers for IP block integration.

This role is for a Post-Silicon Validation Engineer at Intel, focusing on ensuring the quality and functionality of CPU products for laptops, desktops, and gaming systems. Responsibilities include developing and executing validation plans, designing and debugging tests, analyzing issues, leading debug task forces, driving automation, and mentoring junior engineers. Requires experience in post-silicon validation, CPU/SOC architecture, and scripting languages.

Sr. Software Engineering Manager for Intel's Foundry Automation Infrastructure and Security group, leading teams responsible for scalable distributed systems, cloud-native infrastructure, and security frameworks in a high-volume automated manufacturing semiconductor fab environment. Requires deep technical expertise in systems architecture and experience scaling engineering organizations.

This role focuses on designing, developing, and building custom memory circuits (SRAMs, ROMs, register files, caches) for Intel CPUs and SOCs. Responsibilities include technical readiness, circuit design, characterization, simulations, PPA optimization, and methodology definition within advanced CMOS process technologies.

CPU Memory Design Engineer responsible for designing, developing, and building full-custom and compiler-based SRAMs, Large Signal Arrays, ROMs, custom memories, digital circuits, and Caches for Intel CPUs and SOCs. Involves technical readiness, circuit design, characterization, simulations, cache design, critical path simulations, PPA optimization, bit-cell and periphery IC design, automation, IP design, and methodology definition.

Software Engineer role focused on designing, developing, testing, and debugging software tools, flows, and methodologies for design automation in the semiconductor industry. Responsibilities include capturing requirements, writing functional and test code, automating build/deployment, and performing testing. The role also involves designing web-based interfaces for tool configuration and control, and supporting Linux EDA tool infrastructure.

Production Line Engineer responsible for managing shift loop operations to meet quality and output goals in a semiconductor fabrication environment. Key responsibilities include strategic WIP management, optimizing loop performance, coordinating maintenance, gathering tool status, documenting utilization gaps, and understanding root causes for missed goals. Requires strong analytical, communication, and problem-solving skills, with experience in manufacturing or semiconductor operations.

Mechanical Design Engineer responsible for designing Tape and Reel packaging, substrates, heat spreaders, and other mechanical components for semiconductor packaging and assembly. Requires CAD skills and collaboration with cross-functional teams.

This role involves characterizing semiconductor nano-devices using advanced transmission electron microscopy (TEM) to support technology development, process development, and process integration. The engineer will perform imaging and analysis using TEM, EELS, EDX, and 4D STEM, with a focus on improving time-to-information-return for critical manufacturing processes.

Drives technology development and enablement for semiconductor manufacturing, focusing on process integration, equipment solutions, and feasibility studies for new product designs. The role involves leading the design and development of manufacturing processes, including material selection, parameter optimization, and equipment metrology, with a strong emphasis on dry etch semiconductor manufacturing. Responsibilities include performing pathfinding activities, recommending modifications to operating equipment, partnering with suppliers, and conducting process technology feasibility studies. The role requires expertise in plasma etch fundamentals, statistical analysis, and DOE methodologies, with a demonstrated record of improving yield, reliability, performance, or manufacturability for advanced technology nodes.

Drives technology development and enablement for semiconductor manufacturing, focusing on process integration, equipment solutions, and feasibility studies. Leads design and development of manufacturing processes, including material selection, parameter optimization, and equipment metrology. Performs pathfinding activities for process and hardware development, enabling innovative device architectures and developing roadmaps. Recommends and implements modifications to operating equipment to improve production efficiency and output. Partners with suppliers for technology enablement. Requires PhD/Master's/Bachelor's in a semiconductor-related STEM field with relevant experience in dry etch semiconductor processing, plasma etch fundamentals, process development, optimization, and characterization. Proficiency in statistical data analysis and DOE tools is expected.

Module Process / Equipment Engineer at Intel Ireland supporting development and high-volume manufacturing of advanced semiconductor technologies. Responsibilities include ownership of module/equipment performance, qualification, monitoring, continuous improvement, preventative maintenance, troubleshooting, and partnering with cross-functional teams to solve technical challenges and improve operational performance. Requires a Bachelor's/Master's in Engineering/Science with 0-4 years of experience, strong interest in semiconductor manufacturing, and analytical/problem-solving skills.

Junior Design-for-Test (DFT) Engineer role focused on developing, integrating, and validating DFT solutions for CPU core designs, including ATPG generation, fault coverage analysis, and pattern debug. Responsibilities involve RTL-level DFT implementation, script development for automation, and collaboration with cross-functional teams for silicon bring-up and test flows.

Seeking a Modeling Development Engineer to join Intel's modeling engineering team, focusing on integrating and validating software for microcontroller firmware and hardware models within the semiconductor product development lifecycle. Requires strong C software engineering practices and experience with source control tools.

This role focuses on developing and manufacturing advanced semiconductor process technologies, including designing, executing, and analyzing experiments to meet engineering specifications. It involves integrating manufacturing steps, ramping to production volumes, and transferring technology to manufacturing counterparts. The role requires a Ph.D. in a relevant STEM field and significant semiconductor industry experience, with specific expertise in overlay development and understanding of modern semiconductor manufacturing processes.

Develops and executes lithography manufacturing processes for semiconductor devices, ensuring manufacturing viability and high-volume production. This role involves designing experiments, analyzing data, collaborating with partners and suppliers, and transferring technology to other factories.

This role focuses on the development and execution of lithography manufacturing processes for semiconductor devices. Responsibilities include designing and analyzing experiments, developing intellectual property, collaborating with equipment suppliers, installing and qualifying High Volume Manufacturing (HVM) capacity, and transferring technology to other Intel factories. It is an entry-level position requiring a Master's degree in a relevant science or engineering field and some experimental lab work.

Module Equipment Technician role at Intel focused on maintaining and optimizing manufacturing equipment for semiconductor fabrication, specifically in Dry Etch, Diffusion, and Thin Films processes. Responsibilities include equipment maintenance, repair, troubleshooting, and defect reduction. Requires STEM education or equivalent experience and strong problem-solving skills.

Physical Design Engineer for Core IP at Intel, responsible for the implementation of custom CPU designs from RTL to GDS, including synthesis, place and route, timing analysis, and verification. The role involves optimizing CPU designs for power, frequency, and area, and working with EDA vendors to enhance tool capabilities.

Internship role focused on Power Integrity/Delivery Electrical analysis for IC packages, involving extraction, analysis, and optimization of high-performance interfaces. Requires Masters/PhD in Electrical Engineering and experience with simulation tools.

Analog Circuit Design Engineer role at Intel, focusing on designing, developing, and optimizing high-performance analog circuits for advanced process nodes. Responsibilities include circuit design, simulation, verification, and collaboration with cross-functional teams. Requires expertise in high-speed analog circuit design and proficiency in EDA tools.

Senior Physical Design Engineer specializing in Static Timing Analysis (STA) for Intel's mixed-signal IPs. Responsibilities include timing analysis, optimization, constraint generation, timing rollups, and clock network development to meet performance, power, and functionality goals for next-generation client, server, and ASIC hard-IP portfolios.

This role focuses on the architecture of CPUs, specifically on improving methodologies and infrastructure for power and performance modeling, analysis, and workload bring-up for next-generation client products. The individual will research and drive ideas to enhance SoC power and performance modeling, collaborate with design teams, and analyze bottlenecks to propose solutions.

Performs functional verification of mixed signal logic components, including analog behavioral modeling, to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to mixed signal microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with digital and analog architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Requires BS/MS with 10+ years of experience in Design verification, System Verilog and OVM/UVM. Experience in validation flow, testbench architecture, verification closure, debug, coverage, simulations, and GLS is essential. Knowledge of DDRPHY validation, DFI/DDR/LPDDR protocols, Python/Perl scripting, Formal Property Verification, and Git is preferred. Exposure to AI tools like GitHub CoPilot is a plus.

Facility engineer role focused on project management for lab modifications and space projects, ensuring process and safety compliance, assisting with project filing, data management, and coordination. Requires construction management experience, technical knowledge of project management software, strong communication, attention to detail, multitasking, and basic financial concepts. Bachelor's degree required.

Senior Pre-Si Verification Engineer for Intel's E-Core CPU team, responsible for verifying new and existing features for next-generation CPU IP using simulation-based environments and formal verification. Requires expertise in hardware description languages, test bench development (System Verilog UVM/OVM), programming languages, and functional coverage analysis.

Student position in the UPW group focusing on system verification, maintenance, and monitoring of equipment in a semiconductor manufacturing facility. Requires a Practical Engineer degree and proficiency in Excel and Microsoft Office.

Network Security Engineer role focused on designing, architecting, and building secure classified network products for USG operations, requiring experience with load balancing, network security infrastructure, and hardening systems in accordance with federal guidance. Requires active Top Secret clearance.

This role focuses on designing, deploying, and managing Public Key Infrastructure (PKI) solutions, including certificate lifecycle management and automation. It involves collaboration with security, infrastructure, and DevOps teams, and ensuring compliance with internal and regulatory requirements. The position requires a Bachelor's or Master's degree in a relevant field and experience with PKI integration, X.509 certificates, and related standards.

Manufacturing Operators at Intel in Penang, Malaysia, are responsible for performing product manufacturing and assembly tasks, operating equipment, collecting and evaluating operating data, maintaining production efficiency, and ensuring quality control of raw materials and finished products. The role involves setting up and operating production equipment, supporting installation and training of new equipment, and collaborating with management to meet output requirements. Key responsibilities include operating machinery, monitoring production processes, assisting with material handling, maintaining work area cleanliness, meeting production targets, and participating in training.

Develops logic design, RTL coding, and simulation for IP blocks, optimizing for power, performance, area, and timing. Supports SoC customers and ensures quality integration and verification of IP blocks for full chip designs. Requires expertise in microarchitecture, high-speed designs, timing convergence, low-power techniques, and protocols like PCIe and CXL.

Construction Project Manager role at Intel, focusing on building semiconductor manufacturing factories. Responsibilities include planning and delivering projects from initiation to closeout, managing scope, schedules, budgets, contracting, EHS, and quality. Requires experience with project/construction management on major industrial facilities and large scope base build construction projects.

This role focuses on CPU validation and verification for next-generation Intel processor designs, involving developing test plans, creating test content and tools, and debugging silicon bugs. It requires proficiency in Python and scripting languages, and a strong understanding of CPU architecture and validation methodologies.

This role focuses on Static Timing Analysis (STA) for next-generation SoCs, ensuring optimal performance and efficiency. Responsibilities include performing timing analysis and optimization, generating and verifying timing constraints, resolving timing violations, conducting timing rollups, developing power-optimized clock networks, and defining methodologies for quality timing models. The role requires collaboration with various engineering teams to achieve clocking balance and power delivery optimization.