Intel
- HQ
- Santa Clara, US
- Founded
- 1968
- Size
- 120,000+
- Website
- intel.com
Currently tracking 56 active AI roles, down 27% versus the prior 4 weeks. Primary focus: Serve · Engineering. Salary range $122k–$414k (avg $253k).
Intel currently has 84 active job listings related to artificial intelligence. The majority of these roles, 51%, are focused on serving infrastructure, with agents representing another significant portion at 24%. Engineering is the most frequent function for these positions. The company is actively hiring in the United States, China, and Mexico. Frequent technical tags include model serving, inference infrastructure, and agent orchestration. In the last 30 days, Intel has added 73 new AI roles, representing a 52% increase compared to the previous 30-day period.
Intel currently has 59 active AI-related roles in our index. The most common open titles are: AI Software Engineering Intern (3), AI Software Engineer Intern (2), GenAI Software Solutions Engineer (2), Graduate Talent (GenAI Software Solutions Engineer) (2), AI Algorithm Engineer. Most positions are in Engineering and Research.
Intel's active AI hiring is concentrated in: serving infrastructure (49%), agents (29%), application (8%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
Intel is hiring AI talent in: United States (28 roles), China (7 roles), Mexico (6 roles), Malaysia (6 roles).
Job postings at Intel most frequently reference: model serving, inference infra, agent orchestration, rag, tool use.
In the past 30 days, Intel has posted 28 new AI-related roles. That is a -63% change versus the prior 30 days (75 → 28).
| Title | Stage | AI score |
|---|---|---|
| Senior Director, AI SOC Design Verification Directs and manages a team of design verification engineers responsible for Subsystem and SoC design verification, focusing on AI GPU and AI-accelerated systems. Requires expertise in SystemVerilog, UVM, and industry-standard protocols, with experience in hardware emulation platforms preferred. | — | 0 |
| Senior Product Manager - Server CPU This role is for a Senior Product Manager responsible for Intel Xeon server CPUs, focusing on product definition, roadmap planning, launch, and lifecycle management. The role requires owning the product end-to-end, translating ambiguous inputs into clear decisions, defining workload-based success metrics, and aligning cross-functional teams. Experience with server/datacenter platforms, competitive positioning, and workload-based performance frameworks is preferred. | — | 0 |
| Compiler Engineer Compiler Engineer role at Intel focused on developing and maintaining an LLVM-based compiler stack (C, C++, SYCL, Fortran) for Intel's processor platforms, impacting AI, HPC, and other domains. Responsibilities include designing features, collaborating with hardware teams, contributing to open-source communities, and ensuring performance. |
| — |
| 0 |
| System Software Engineer Intel is seeking a Senior System Software/Firmware Engineer to design, develop, and validate system software and firmware for data center hardware, including AI platforms. The role involves collaborating with cross-functional teams, implementing low-level hardware abstractions, and participating in power-on and bring-up activities. Responsibilities include design, implementation, testing, and validation of firmware components like UEFI, BMC, and device drivers for operating systems such as Linux. | — | 0 |
| Foundry Customer Integration Engineer Customer Integration Engineer role in the semiconductor industry, focusing on process integration, yield improvement, and customer support for advanced node technologies. Requires extensive experience in FEOL Process Integration and semiconductor development/manufacturing. | — | 0 |
| Senior Silicon Design Engineer Senior Silicon Design Engineer at Intel, focusing on physical design implementation of custom IP and SoC designs from RTL to GDS. Responsibilities include synthesis, place and route, clock tree synthesis, static timing analysis, power/clock distribution, reliability analysis, and verification/signoff. The role involves optimizing designs for power, frequency, and area, and participating in methodology development. Requires Btech/Mtech with 10+ years of complex ASIC/SOC implementation experience, understanding of system/processor architecture, and proficiency in scripting languages. | — | 0 |
| Module Equipment Technician (Contract) Module Equipment Technician responsible for maintaining and troubleshooting precision equipment in a manufacturing environment. Requires a technical diploma and basic understanding of mechanical, electronic, or mechatronic systems. Experience with troubleshooting and maintenance is preferred. | — | 0 |
| Senior Data Scientist (Quality Systems) The role focuses on quality engineering within Intel Foundry's advanced package substrate roadmap. It involves leading the application of advanced statistical methods like SPC, conducting operational audits, introducing and enforcing quality standards, and driving continuous improvement initiatives. The goal is to elevate quality standards internally and at suppliers to meet customer expectations in a competitive foundry environment. | — | 0 |
| SoC Functional Validation Engineer This role focuses on the functional validation of System-on-Chip (SoC) designs, ensuring the quality and reliability of Intel's silicon solutions. Responsibilities include developing and executing pre-silicon and post-silicon validation strategies, system simulation, emulation, debugging, and collaborating with cross-functional teams to resolve issues and optimize designs. | — | 0 |
| Senior CPU Power Management Architect This role focuses on CPU power management architecture, including defining microarchitecture specifications, exploring new power management solutions, and collaborating with hardware and software teams. It involves defining mechanisms for DVFS, power states, thermal control, and using machine learning algorithms for power and performance optimization. The role also includes post-silicon debug and tuning. | — | 0 |
| Senior Standard Cell Library Design Manager This role manages a team responsible for the development and optimization of standard cell libraries for Intel's technology nodes, focusing on circuit design, layout, characterization, and modeling to achieve best-in-class PPA for both internal and external customers. It involves technical leadership in circuit design, managing engineers, and collaborating with process technologists and EDA vendors. | — | 0 |
| SoC/IP Design Verification Engineer SoC/IP Design Verification Engineer responsible for verification planning, UVM testbench development, test content creation, coverage closure, and debug across block, subsystem, and SoC levels. Collaborates with design, architecture, firmware, and validation teams. | — | 0 |
| Physical Design Engineer Physical Design Engineer at Intel responsible for the physical design implementation of custom IP and SoC designs, transforming RTL to GDS, optimizing power, performance, and area for advanced semiconductor technology. | — | 0 |
| Process Technology Design Engineer Electrical Engineer to drive silicon processes and collaterals for advanced Intel wireless products, working with foundries to deliver next-generation wireless solutions. | — | 0 |
| Senior VLSI Design Engineer Senior VLSI Process Design Engineer role focused on optimizing Intel's process technology for power, performance, and area (PPA) of Intel IPs. Responsibilities include conducting experiments, defining methodologies, building tools, analyzing results, and collaborating with design teams. | — | 0 |
| Firmware Architect Firmware Architect role at Intel focusing on designing and developing embedded software solutions, emphasizing security and performance. Responsibilities include defining architectural frameworks, translating requirements, developing algorithms, leading vulnerability assessments, and collaborating with engineering teams on implementation and new technology adoption. Requires strong C/low-level Linux driver experience and firmware architecture/system-level design. | — | 0 |
| Software Application Development Engineer Software Applications Development Engineer to create full stack integrated software solutions for new product introduction workflows management, execution readiness and controls, build readiness and logistics capabilities, and Design of Experiments (DOE) planning applications. The role involves the complete software project lifecycle, working with stakeholders from Assembly Test Technology Development (ATTD) and Logic Technology Dev (LTD) Fabs. | — | 0 |
| Substrate Supplier Enablement Engineer This role focuses on enabling new manufacturing capacity for advanced packaging suppliers by leading substrate supplier development and qualification activities. The engineer will drive technical enablement, manage readiness milestones, and collaborate with cross-functional teams and suppliers on various substrate technologies and processes. | — | 0 |
| CPU Performance Architect This role focuses on CPU performance architecture, developing and optimizing CPU logic for power, performance, and area. Responsibilities include defining CPU architecture specifications, modeling performance and power, analyzing bottlenecks, developing tests, and collaborating with engineering teams. Requires a degree in a related field and experience with C++. | — | 0 |
| Senior Middleware Development Engineer Senior Middleware Development Engineer to join a communication runtimes team, developing and optimizing libraries like Intel SHMEM, Intel MPI, MPICH, and Intel oneCCL. The role involves working with the latest Intel GPUs and CPUs, collaborating with scientists and engineers on supercomputers, and improving scientific computing and machine learning. Requires understanding of communication stacks, strong analytical skills, and excellent communication. | — | 0 |
| GPU IP Engineering Program Manager This role is for a GPU IP Engineering Program Manager at Intel, responsible for supporting the General Manager and staff in the development, integration, and execution of GPU IP. The position involves understanding the state of IP development, managing staff operations, driving cross-team projects, and ensuring effective operating rhythms. It requires strong technical fluency in Intel's technologies and engineering processes, as well as excellent program management and communication skills. | — | 0 |
| Package Design Rule Owner (DRO) Seeking an experienced Package Design Rule Owner (DRO) to define, validate, and deploy design rules for package substrate design, collaborating with product design, manufacturing, and assembly teams to ensure competitive product designs that meet cost and manufacturability requirements. The role involves working from early technology stages through product design tape out, driving a consistent Design Rule strategy and a forward-looking roadmap, and interacting with cross-disciplinary stakeholders, external suppliers, and customers. | — | 0 |
| Back End Cloud Software Developer Experienced Full Stack Cloud Software Developer with a strong backend orientation to design, build, and maintain software components and tools used across the organization. Will work on complex software systems, collaborate with multiple teams, and contribute across the full software development lifecycle. | — | 0 |
| Senior CPU Pre-Silicon Verification Engineer Senior CPU Pre-Silicon Verification Engineer role focused on leading and executing functional verification of CPU logic using UVM and System Verilog. Responsibilities include developing test benches, analyzing power and timing, debugging issues, and collaborating with cross-functional teams. The role requires experience in digital logic design and scripting languages, with preferred experience in AI agents in verification. | — | 0 |
| CPU Formal Verification Engineer This role focuses on the formal verification of CPU designs, ensuring the quality and reliability of Intel's cutting-edge CPU technologies. The engineer will develop strategies, create abstraction models, collaborate with design teams, and debug issues. While the role mentions AI and machine learning systems as applications of the CPUs, the core function is CPU verification, not AI/ML model development. | — | 0 |
| Senior Out-of-Order CPU Architect Senior Out-of-Order CPU Architect at Intel, responsible for defining and driving end-to-end CPU architecture specifications, exploring novel architectures, and influencing cross-functional roadmaps. Requires extensive experience in high-performance CPU design and out-of-order pipeline architecture. | — | 0 |
| Senior CPU Performance Architect This role focuses on designing and specifying CPU microarchitectures, modeling their performance and power characteristics, and collaborating with cross-functional teams to ensure designs meet stringent requirements. It involves developing end-to-end specifications, evaluating tradeoffs, and debugging performance issues from RTL to silicon. | — | 0 |
| Design Engineer – AI SoC Development Develops logic design, RTL coding, and simulation for AI SoC development, focusing on power, performance, area, and timing goals. Integrates IP blocks, performs quality checks, and supports silicon bring-up. | — | 0 |
| Design Engineer – AI SoC Development This role is for an RTL Design Engineer focused on developing logic design, RTL coding, and simulation for AI System-on-Chip (SoC) development. The engineer will integrate IP blocks, define architecture and microarchitecture, and optimize logic for power, performance, area, and timing. The role involves close collaboration with verification teams, physical design teams, and IP providers, and supports silicon bring-up and validation. While the products power AI applications, the core craft of the role is hardware design (RTL, SoC integration, timing closure) rather than AI/ML model development or deployment. | — | 0 |
| CPU–SoC Mask Layout Designer (Diploma Level Contract role) - Silicon Engineering Group (SiG) Diploma level contract role for a CPU-SoC Mask Layout Designer at Intel, focusing on the training, design, and development of next-generation SOC/CPU. Responsibilities include creating mask layouts, running verification tools, designing floorplans, and troubleshooting layout issues. Requires a Diploma in Electrical and Electronic Engineering and offers hands-on experience in semiconductor design. | — | 0 |
| IP Design Verification Engineer Intel is seeking an IP Design Verification Engineer with 6+ years of experience in Pre-Si verification. The role involves developing IP verification plans, test benches, and simulation models to ensure design specifications are met. Responsibilities include debugging issues, collaborating with cross-functional teams, and maintaining verification infrastructure. Requires strong skills in Specman “e” / System Verilog and understanding of verification methodologies. | — | 0 |
| Sr. Substrates Development and Ramp Engineer This role supports management in improving Intel's supply chain and logistics strategy, focusing on process and quality improvements, cost control, production yield, and exploring emerging technologies. The engineer will define material inspection methodology, support product long-range planning, lead supplier selections, perform risk mitigation, establish control standards, monitor KPIs, drive supplier process validation, and manage quality excursions. | — | 0 |
| Manufacturing Operators Manufacturing Operators at Intel in Malaysia are responsible for performing product manufacturing and assembly tasks, operating equipment, collecting and evaluating operating data, and driving process improvements to meet industry standards and customer specifications. The role involves working in shifts and requires basic computer literacy and problem-solving skills. | — | 0 |
| Advanced Packaging Materials Supply Chain Engineer Supply Chain Engineer at Intel responsible for developing and executing supply chain strategies, ensuring supplier process and product readiness, and managing supplier relationships to meet cost, quality, availability, technology, and environmental goals within the semiconductor industry. | — | 0 |
| Graduate Talent (PDK QA Engineer) This role is for a Graduate Talent (PDK QA Engineer) within Intel's Design Technology Platform (DTP) organization, focusing on the Process Design Kit (PDK) group. Responsibilities include validating PDK quality for custom design components and developing regression test suites to ensure PDK accuracy across various EDA flows and process nodes. The role requires knowledge of VLSI semiconductor devices, electronic circuits, and familiarity with EDA tools. | — | 0 |
| Analog and Mixed Signal Design Engineer Designs and develops analog and mixed-signal circuits for Intel's Advanced Design Foundational IP Organization, focusing on pathfinding and development of advanced logic, memory, and analog/mixed-signal circuits for Intel's process technology. | — | 0 |
| Graduate Talent (Memory Design) This role is for a Graduate Talent in Memory Design at Intel, focusing on the pathfinding and development of advanced memory technology and circuits. Responsibilities include PPA optimization, product/design enablement, IC layout, memory array/IP design, circuit innovation, testchip design, and pre/post-Si validation. The role requires a Bachelor/Master/PhD in Electrical Engineering or related STEM field, proficiency in programming languages like Python, and familiarity with Unix/Linux. | — | 0 |
| CPU Formal Verification Lead Lead formal verification efforts for complex CPU designs (i9, i7, i5, Xeon processors). Develop environments, create models and properties, analyze failures, and guide team members. Stay updated on formal verification technologies and develop new methodologies. | — | 0 |
| Semiconductor Manufacturing Engineer Semiconductor Manufacturing Engineer responsible for operational support, process optimization, and new product introduction in a fabrication facility. This role involves analyzing factory metrics, developing manufacturing plans, and collaborating with engineering and automation teams to ensure efficient production and delivery schedules. | — | 0 |
| Process and Equipment Engineer Process and Equipment Engineer at Intel in Malaysia, responsible for optimizing high-volume manufacturing equipment and processes for integrated circuit production. This role involves ensuring precision, quality, cost efficiency, and technology scaling, with opportunities for global process transfer and continuous improvement. | — | 0 |
| Process and Equipment Engineer Process and Equipment Engineer at Intel in Malaysia, focusing on optimizing high-volume manufacturing equipment and processes for integrated circuits. Responsibilities include testing, defect minimization, implementing process modifications, building capacity, executing maintenance, developing excursion prevention systems, managing equipment installation, and collaborating with cross-functional teams for technology transfer. | — | 0 |
| Industrial Engineer (Data Analytics) (Contract role) Industrial Engineer specializing in automation for semiconductor manufacturing, focusing on designing and implementing solutions to enhance operational efficiency. The role involves programming (Python), data management (SQL, NoSQL), data analysis, process optimization, and utilizing visualization tools. | — | 0 |
| Senior Technical Lead -Power & BatteryLife Designs, develops, and executes power and performance plans for IPs and SoCs. Identifies, builds, and maintains power, thermal, performance/watt optimizations, and characterizations for IPSoC power and performance goals. Conducts feature analysis from power and performance standpoint and drives to close any gaps between observed behavior and target on platforms in development. Provides recommendations for future architectures. Develops and enhances innovative tools for architectural performance analysis. Develops methodologies and models to drive continuous improvements in optimization of power and performance configurations to meet market requirements. Ensures platform and its components are optimized for performance and power balance. Identifies power activity zones and works with design, architecture, binning/technology, and manufacturing teams on ways to meet power consumption goals. Works cross functionally on analysis, validation, and tuning of architectures and features that advance the state of art in performance and efficiency. | — | 0 |
| Senior CPU Physical Design Engineer Senior CPU Physical Design Engineer responsible for the design and delivery of high-performance CPU blocks from RTL to GDS, including synthesis, floorplanning, place and route, CTS, timing closure, and verification. Requires 10+ years of experience with industry-standard EDA tools. | — | 0 |
| CPU Physical Design Engineer This role is for a CPU Physical Design Engineer at Intel, focusing on the design and delivery of high-performance CPU blocks from RTL to GDS. Responsibilities include executing the full physical design flow, leading verification and sign-off, and optimizing designs for power, performance, and area using industry-standard EDA tools. The role requires a BSc or MSc degree in Electrical or Computer Engineering and at least 7 years of experience in physical design. | — | 0 |
| Mixed Signal Logic Verification Engineer Senior/Staff VLSI Verification Engineer with 11-15 years of experience in complex SoC/ASIC verification, focusing on UVM/System Verilog testbench architecture, Mix signal IP verification strategy, and post-silicon debug. Responsibilities include defining verification plans, mentoring junior engineers, ensuring coverage closure, and collaborating with architects. Experience with formal verification methods is also required. | — | 0 |
| CPU Pre-Silicon Verification Lead Lead a team responsible for pre-Silicon functional verification of Intel's latest CPUs, developing test plans, simulation models, and test benches to ensure design requirements are met. Focus on driving strategic tool/flow/methodology initiatives to reduce validation cycle time and ensure first-pass silicon success. Requires technical leadership and managerial experience in pre-Silicon verification environments. | — | 0 |
| TA/Chief of Staff for CEG This role is a Chief of Staff/Technical Assistant for Intel's Central Engineering Group (CEG), focusing on strategic initiatives, operational excellence, and stakeholder management. It requires strong business acumen, program management skills, and a deep understanding of Intel's technology and business strategies, but is not directly involved in AI/ML development. | — | 0 |
| Director-Analog Design & Infrastructure Design Automation Director of Analog Design & Infrastructure Design Automation to lead the development, deployment, and governance of analog/mixed-signal design environments and CAD infrastructure. This role owns EDA tool ecosystems, PDK integration, compute infrastructure, design data governance, and tapeout manifest management to ensure high productivity, reproducibility, and audit readiness across silicon programs. | — | 0 |
| GPU Validation Engineer The GPU Validation Engineer role at Intel focuses on the pre-silicon validation of GPUs, including their interaction with media, display, and system-level features. The role involves defining, developing, and performing functional validation, applying various tools and techniques to meet performance, power, and area goals. Responsibilities include reviewing design changes, developing validation methodologies, executing validation plans, debugging pre-silicon issues, influencing validation infrastructure, publishing reports, and collaborating with architecture, design, verification, and platform teams. | — | 0 |