AMD currently has 62 active AI-related roles in our index. The most common open titles are: DC-GPU Performance Modeling Engineer (3), Data Center Engineer (2), Lead Packaging Automation Engineer (2), 3D IC and ADVANCED PACKAGING CAD ENGINEER , AI Framework Engineer. Most positions are in Engineering and Research.
AMD's active AI hiring is concentrated in: serving infrastructure (73%), agents (13%), application (6%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
AMD is hiring AI talent in: United States (27 roles), India (13 roles), China (7 roles), Canada (6 roles).
Job postings at AMD most frequently mention: GPU Computing, Computer Architecture, Compiler Design, Python, Performance Profiling.
In the past 30 days, AMD has posted 50 new AI-related roles. That is a -28% change versus the prior 30 days (69 → 50).
AMD currently has 35 active AI-related job listings. The majority of these roles, 66%, are focused on serving infrastructure. Engineering is the dominant function, with 32 positions. Frequent technical tags include model_serving, inference_infra, and evals, suggesting a focus on the deployment and evaluation of AI models. In the last 30 days, AMD posted 37 new AI roles.
| Title | Stage | AI score |
|---|---|---|
| CPU Core High Performance Physical Design Engineer This role is for a CPU Core High Performance Physical Design Engineer at AMD. The engineer will be responsible for owning a portion of the core from Synthesis to a Placed and Routed design, working with external disciplines like CAD, DFT, and Architecture. Key responsibilities include implementing logic and transistor level circuit design, innovating for lower power and higher performance, preparing schedules, and making technical recommendations. | — | 0 |
| Fellow Software Development Engineer (Network Technology Group) Software engineer, architect, and technical lead for embedded firmware on AMD networking products, focusing on next-generation networking for cloud, hyperscale data centers, and AMD's AI systems. Involves hardware/software interface, C programming, system-level problem-solving, and collaboration with silicon, driver, and test teams. | — | 0 |
| Design Verification Engineer Design Verification Engineer at AMD working on networking technologies for data centers, including AI and data center applications. Responsibilities include developing UVM-based testbench architectures, execution of verification plans, debugging complex issues, and collaborating with cross-functional teams. Requires expertise in SystemVerilog, UVM, and industry protocols like PCIe and Ethernet. Preferred qualifications include experience with performance verification, networking pipelines, and FPGA/HAPS validation. |
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| SOC Debug tools validation Engineer This role is for a SOC Debug tools validation Engineer at AMD, focusing on the validation and debugging of Silicon Debug Tools products. The engineer will be responsible for creating test strategies, executing test plans, coordinating debug efforts, and ensuring product quality across various engineering teams. While AI is mentioned in the company's mission and a general statement about AI use in screening, the core responsibilities of this specific role are not AI/ML-centric. | — | 0 |
| Sr. Firmware Engineer Sr. Firmware Engineer at AMD working on x86 embedded platforms for embedded and commercial applications. The role involves integrating AMD processor automotive products, debugging issues, validating software features, and providing technical guidance to customers and internal teams. Requires strong knowledge in computer technologies, software engineering, and systems architecture. | — | 0 |
| Director, Data Center Global System Integrator (GSI) Enablement This role is for a Director to lead AMD's Global System Integrator (GSI) business enablement within the Data Center segment, focusing on Enterprise and Datacenter solutions. The individual will drive strategy, build executive relationships with GSIs, develop enablement plans (including sales and pre-sales training), identify challenges, and establish operational capabilities with KPIs. Experience leveraging AI to scale enablement is preferred. | — | 0 |
| Staff Silicon Design Engineer - Emulation This role is for a Staff Silicon Design Engineer focused on emulation at AMD. The responsibilities include executing emulation test plans, collaborating with design and verification teams, contributing to test bench design, and debugging. Experience with SystemVerilog, C/C++, UVM, and emulation methodologies is preferred. The role is not directly involved in building or researching AI/ML models. | — | 0 |
| ASIC/SoC Design Engineer This role is for an ASIC/SoC Design Engineer at AMD, focusing on the microarchitectural design and RTL implementation of Adaptive SoC and FPGA configuration systems. The responsibilities include authoring specifications, RTL coding, collaborating with hardware/firmware/software teams, driving design through all phases of silicon development, and optimizing for performance, power, and area. While the company mentions AI and data centers as areas of focus, this specific role is in core hardware design and implementation, not directly building AI models or systems. | — | 0 |
| Sr. STAFF Silicon Design Engineer This role is for a Sr. Staff Silicon Design Engineer focused on designing high-performance RF ADCs and DACs for FPGA devices. Responsibilities include developing circuit architectures, simulation, verification, layout collaboration, EMIR and reliability validation, design reviews, and post-silicon validation. Requires at least 5 years of experience in data converters and/or high-speed circuits, with a Bachelor's or Master's degree in Electronic Engineering. | — | 0 |
| IP Verification Lead This role focuses on planning, building, and executing the verification of new and existing features for AMD's graphics processor IP, ensuring no bugs in the final design. It involves collaborating with architects, hardware, and firmware engineers, building test plans, writing directed and random verification tests, debugging failures, and reviewing coverage metrics. | — | 0 |
| Product Development Engineer (Server Platform) This role focuses on optimizing power and performance for AMD EPYC server platforms in datacenter environments, working with customers to diagnose and resolve efficiency challenges. It involves deep dives into BIOS, OS, I/O, and application-level workloads, requiring strong analytical and cross-functional collaboration skills. | — | 0 |
| SOC verification Manager/Lead Seeking an experienced SOC Verification Manager/Lead with deep expertise in SoC-level verification, power management verification, low-power verification methodologies, and SoC verification architecture development. The role involves defining verification strategies, architecting verification environments, driving functional and power-aware verification closure, and mentoring teams. Responsibilities include leading end-to-end verification planning, execution, coverage closure, and sign-off activities, collaborating with cross-functional teams, and supporting various verification environments (simulation, emulation, FPGA, post-silicon). | — | 0 |
| Senior Design Verification Engineer – Security IP This role is for a Senior Design Verification Engineer focused on Security IP (SECIP) development at AMD. The engineer will be responsible for block-level functional verification and subsystem-level integration and verification of embedded micro-processor subsystems and hardware accelerators. The role involves developing verification architectures, testbenches, and test plans using SystemVerilog/UVM, C-DPI, and formal verification methodologies. Key responsibilities include debugging simulations, analyzing coverage, collaborating with design teams, and providing technical leadership in verification methodology and problem resolution. While the company mentions AI and its role in computing experiences, this specific position is centered on hardware verification, not AI model development or deployment. | — | 0 |
| Product Development Engineer This role focuses on evaluating the performance of AMD Adaptive System-on-Chip (SoC) and FPGA products, including processor subsystems. The engineer will develop and execute characterization test patterns to ensure design margins, speed specifications, and silicon performance across various operating conditions. Responsibilities include porting test patterns, analyzing data, and collaborating with cross-functional teams to resolve issues. Experience with SoC/FPGA pre- or post-silicon validation, scripting languages, and C/C++ is preferred. | — | 0 |
| Product Development Eng. This role focuses on building and enabling GPU platforms for data center solutions with partners and customers, involving NPI, design reviews, validation, and system bring-up. It requires experience in complex server system design and debugging, with a strong emphasis on customer collaboration and program management for successful product launches. | — | 0 |
| Datacenter Infrastructure & Quality Excellence Leader This role focuses on driving datacenter quality excellence by applying aerospace/automotive-grade rigor to datacenter infrastructure, ensuring reliability across manufacturing, OEM/ODM quality, component qualification, and material integrity. The leader will define and enforce quality standards, lead failure analysis, and collaborate with cross-functional teams to embed design-for-quality principles. | — | 0 |
| Product Engineer - FPGA/Emulation & ACAP Compilation Tools Product Engineer at AMD focusing on FPGA/Emulation & ACAP Compilation Tools. This role involves owning emulation and prototyping product areas, driving customer escalations, triaging issues, exploring innovative methodologies, and developing training materials. Requires MS or equivalent experience with 8+ years in Electrical Engineering or similar, with strong knowledge of RTL design flows, pre-silicon validation, emulation/prototyping, and scripting. | — | 0 |
| Lab Engineer (Post Silicon Validation) The Lab Engineer (Post Silicon Validation) role at AMD is responsible for managing, maintaining, assembling, and supporting a large volume of compute systems used for platform bring-up, validation, and firmware development. This includes system assembly, firmware flashing, remote access enablement, boot failure triage, and thermal setup management, ensuring the reliable operation of lab systems. The role also involves meticulous record-keeping of hardware assets and coordinating with various teams for lab readiness and safety. | — | 0 |
| Firmware Manager-IP Diagnostic This role is for a Firmware Manager at AMD, leading a software development team focused on IP diagnostic suites and debugging for pre-silicon and post-silicon environments. The role involves team leadership, talent development, setting priorities, execution plans, and cross-functional collaboration. Experience in software/firmware development with C/C++ and Linux is required, along with leadership experience. While the company mentions AI and data centers, the core responsibilities of this specific role are in firmware and IP diagnostics, not direct AI/ML model development. | — | 0 |
| Product Development Engineer, Product Operations Drives the development and manufacturing launch of cutting-edge datacenter hardware (server and rack systems), collaborating with cross-functional teams to ensure new products meet design standards, quality targets, and production timelines. Focuses on NPI, DFM reviews, project scheduling, prototype oversight, and production support. | — | 0 |
| Packaging Engineer This role is for a Packaging Engineer at AMD, focusing on bringing up and sustaining various package types for AMD products, including those for AI and data centers. The responsibilities include manufacturing readiness, yield, quality, cost improvements, process standardization, and supplier management. While the company works on AI products, this specific role is in hardware packaging engineering, not directly building AI models or systems. | — | 0 |
| Sr. Software Development Engineer (1-Year Contract) This role is for a Senior Software Development Engineer at AMD, focusing on developing and enhancing software for new technology and product introduction projects. The role involves validating new software features, collaborating with multiple teams, and contributing to system architecture design. While the company mentions AI and data centers as areas of focus and notes the potential use of AI in the screening process, the core responsibilities of this specific role are centered on general software engineering principles and product development, not on building or researching AI models themselves. | — | 0 |
| Design Verification Engineer (1-Year Contract) AMD is seeking a Design Verification Engineer for a 1-year contract role focused on chiplet technology. The role involves developing testbenches, writing test cases, analyzing coverage, debugging regressions, and deploying verification methodologies like UVM and Formal Verification. The position requires proficiency in Verilog, System Verilog, UVM, and ASIC design knowledge, with experience in scripting languages like Python. | — | 0 |
| Product Development Engineer, Product Operations This role focuses on the product development and manufacturing launch of datacenter hardware, including server and rack systems. The engineer will collaborate with cross-functional teams to ensure products meet design standards, quality targets, and production timelines, driving new product introductions from concept through production. | — | 0 |
| Program Manager – Value Added Services Program Manager for AMD's Value Added Services (VAS) portfolio, focusing on scaling services to meet business and customer needs. This role involves aligning VAS priorities with business unit strategies, commercial opportunities, and operational capabilities, and partnering with various departments to translate requirements into scalable VAS solutions. The PM will drive integration of new product requirements, improve efficiency, and develop executive-ready materials for program reviews. | — | 0 |
| Program Manager – Value Added Services Program Manager for AMD's Value-Added Services (VAS) portfolio, focusing on scaling offerings, aligning with business strategies, and driving operational capabilities. This role involves cross-functional partnership with Business Units, Sales, Legal, and Finance to translate market and customer needs into scalable VAS solutions. The PM will manage strategic execution, improve efficiency, and develop executive-level communications. | — | 0 |
| Senior Finance Manager - AI Group Senior Finance Manager role within AMD's Finance organization, supporting the Artificial Intelligence Group Business Unit. This position serves as the key business partner to the BU leadership team, providing financial leadership, insight, and strategic support to drive performance and achieve business objectives. The role will work cross-functionally with various AMD operations stakeholders, finance counterparts and technical accounting. | — | 0 |
| Program Manager – Diagnostics Program Manager responsible for driving planning, execution, and delivery of diagnostic, debug, validation, and enablement software for complex silicon programs, with a focus on AI and data center technologies. This role coordinates globally distributed teams, manages program readiness, supports customer-facing debug activities, and ensures timely delivery of diagnostics to support silicon bring-up, validation, production readiness, and customer enablement. | — | 0 |
| Senior Corporate Counsel - Privacy Senior Corporate Counsel - Privacy role at AMD, focusing on global privacy program with primary emphasis on European operations. Responsibilities include advising on European data protection regulations (GDPR, ePrivacy), privacy-by-design for products and AI-enabled technologies, Data Protection Impact Assessments, drafting policies, and advising on international data transfers. Requires in-house experience at a global tech company and deep knowledge of European privacy laws. | — | 0 |
| Software BIOS/BMC Engineer (Datacenter Platform) Software BIOS/BMC Engineer responsible for developing, debugging, and testing BMC and Security firmware for DCGPU products, collaborating with cross-functional teams and customers to enhance manageability, reliability, and security. | — | 0 |
| Lead IP Verification Engineer Lead IP Verification Engineer at AMD, responsible for planning, building, and executing verification of graphics processor IP features to ensure no bugs in the final design. This role involves collaboration with architects and engineers, test plan development, test building, debugging, and coverage analysis. | — | 0 |
| Lead DPDK Optimization Engineer Lead DPDK Optimization Engineer at AMD in Bangalore, India. Focuses on performance optimization and benchmarking of DPDK-based data plane applications across CPU/GPU/NPU platforms. Requires mandatory DPDK development experience and strong Linux systems knowledge. | — | 0 |
| PMTS Product Application Engineer This role is for a Product Application Engineer at AMD, focusing on customer technical leadership for the MI455 program, which is related to AI and data centers. The engineer will be responsible for system bring-up, validation enablement, design reviews, issue triage, cross-functional orchestration, customer communication, enablement, manufacturing support, sustaining support, and gathering customer feedback. The role requires strong system-level debugging skills, familiarity with data center server platforms, and the ability to lead technical execution across multiple stakeholders. While the company mentions AI and data centers, the core responsibilities are in platform engineering and customer-facing technical support, not direct AI/ML model development or research. | — | 0 |
| Sr. Lead IP/RTL Design Engineer This role is for a Sr. Lead IP/RTL Design Engineer focused on Data Fabric and NoC architecture within AMD. The engineer will micro-architect, design, and deliver RTL components, manage power, performance, and area targets, and collaborate with architecture, verification, and physical design teams. The role involves defining features, driving technical specifications, leading discussions on core interfacing, and supporting various design and verification stages, including post-silicon debug. While the company mentions AI and data centers, the core responsibilities are in hardware design (RTL, NoC, IP) rather than AI model development or deployment. | — | 0 |
| Finance Manager This is a Finance Manager role at AMD, focusing on accounting activities, compliance with US GAAP, and supporting business programs. It requires extensive experience in accounting, contract analysis, and working within a multinational corporation. The role does not involve direct AI/ML development. | — | 0 |
| Enterprise AI Lead Systems Engineer This role is for a Lead Systems Engineer on the AMD EPYC Server team, focusing on silicon validation, program execution, and driving Post-Si engineering initiatives for server CPUs. It involves defining validation strategies, managing technical constraints, and overseeing test plan execution to ensure high-quality silicon delivery. The role requires strong technical leadership and collaboration across hardware, firmware, software, and validation teams. | — | 0 |
| Semicustom DFT Strategy Lead This role is for a Semicustom DFT Strategy Lead at AMD, focusing on Design-for-Test (DFT) and Design-for-Debug (DFD) for complex semiconductor products like APUs, GPUs, and game consoles. The lead will influence strategy, drive adoption of DFT standards, analyze post-silicon experiments, and manage relationships with EDA and ATE industries. While the company mentions AI and data centers, the core responsibilities are in semiconductor DFT, not direct AI/ML model development. | — | 0 |
| Director Silicon Design Engineering Director of Silicon Design Engineering responsible for technical leadership and sign-off of Adaptive & Embedded Computing Group (AECG) device programs from conception to manufacturing release. This role involves problem-solving across the entire device development cycle, including architecture, RTL, analog design, verification, physical design, tapeout, and post-silicon validation. The position requires extensive ASIC design experience, leadership skills, and the ability to resolve inter-team technical issues. | — | 0 |
| Lead System Debug Engineer - Server Validation Lead System Debug Engineer for AMD EPYC Server & Instinct products, focusing on post-silicon validation, system and silicon debug, and driving improvements to debug methodology. This role involves leading complex debug efforts, managing technical issues, and communicating program status to stakeholders. | — | 0 |
| Hardware Systems Design Engineer – x86 Embedded Solutions (San Jose/Austin) This role is for a Hardware Systems Design Engineer focused on x86 embedded solutions for networking and storage customers. The engineer will act as a technical leader, guiding customers on integrating AMD processors, performing architecture and schematic reviews, debugging hardware issues, and providing technical guidance. The role requires expertise in hardware architecture, SoC/x86 platform debugging, signal integrity, and familiarity with various hardware standards and scripting languages. | — | 0 |
| CPU Core Physical Design Staff Engineer This role is for a CPU Core Physical Design Staff Engineer at AMD. The primary responsibilities involve owning a portion of the IP from Synthesis to a Placed and Routed design, working with external disciplines like CAD, DFT, and Architecture. The role requires innovation, improving design for lower power and higher performance, preparing schedules, and making technical recommendations. While the company mentions AI and its role in shaping the future, this specific position focuses on core physical design of CPUs, not on building or researching AI/ML models. | — | 0 |
| Infinity Fabric Senior Staff Verification Engineer This role is for a Senior Staff Verification Engineer at AMD, focusing on the Infinity Fabric transport layer. The engineer will be responsible for pre-silicon verification of configurable switches and die-to-die interconnects, which are critical components in AMD's products across various markets including AI and data centers. The role involves defining verification strategies, developing verification environments, debugging complex issues, and leading verification efforts. While the company mentions AI and data centers as markets, the core function of this role is hardware verification, not AI/ML model development. | — | 0 |
| System Design & Debug Manager – AI Customer Engineering This role is a System Design & Debug Manager within AMD's AI Customer Engineering organization. The primary focus is on driving complex silicon, system, and fleet-level issues to resolution for AI-related customer programs. It involves leading debug execution, coordinating cross-functional efforts, managing field failures, and improving debug processes. While the role is within the AI Customer Engineering organization, the core responsibilities are in system design and debug of hardware and infrastructure, not in building or researching AI models themselves. | — | 0 |
| Product Development Engineering Debug Manager This role manages a customer RMA debug team focused on diagnosing and resolving failures in products, including those for AI and data centers. The team uses various test platforms and data analysis to identify issues in silicon, test, package, and system levels, driving improvements in product quality and reliability. The manager coordinates cross-functional efforts and communicates with internal teams and external customers. | — | 0 |
| Senior UEFI/BIOS Firmware Engineer This role is for a Senior UEFI/BIOS Firmware Engineer at AMD, focusing on designing, developing, and debugging firmware for internal and external systems using AMD APUs/CPUs. The position involves C language programming, power management, security features, and collaboration with various internal and external teams. While AMD's broader mission includes AI, this specific role is centered on traditional firmware engineering. | — | 0 |
| Manufacturing Operation Engineer (Datacenter Platform) This role focuses on manufacturing operations and engineering for data center platforms, including AI and other advanced computing experiences. The engineer will lead the development of manufacturing test strategies, support NPI, analyze yield data, and collaborate with internal and external teams to ensure reliable and scalable production of complex hardware. | — | 0 |
| C++ Lead Software System Design Eng Lead Software System Design Engineer with C++ expertise to develop validation SW tools for next-generation AMD microprocessors, focusing on platform validation and cross-functional collaboration. | — | 0 |
| Senior Staff Product Development Engineer (SOC / Characterization) This role is for a Senior Staff Product Development Engineer at AMD, focusing on the characterization of Memory Controller IPs for next-generation SoCs. The responsibilities include evaluating product performance, developing test strategies, debugging issues, and driving continuous improvement in automated test scripts and frameworks. The role requires expertise in post-silicon validation, SoC architecture, memory protocols, and data analysis, with a preference for experience in Linux environments and scripting languages like Python. | — | 0 |
| HSIO Enablement Lead This role is for a HSIO Enablement Lead at AMD, focusing on the post-silicon enablement of High Speed interfaces (Ethernet, PCIe, Display, USB). The responsibilities include end-to-end enablement, feature coverage, debug, and developing validation plans. While the company mentions AI and its use in screening, this specific role is not directly involved in AI/ML development. | — | 0 |
| Materials Coordinator This role is for a Materials Coordinator at AMD, responsible for managing NPI material flow, inventory accuracy, and logistics operations to support build phases and enhance operational efficiency. It involves coordinating with various teams, managing warehouses, and ensuring compliance with company policies. | — | 0 |