Intel
Building- HQ
- Santa Clara, US
- Founded
- 1968
- Size
- 120,000+
- Website
- intel.com
Currently tracking 64 active AI roles, up 216% versus the prior 4 weeks. Primary focus: Serve · Engineering. Salary range $122k–$414k (avg $253k).
Hiring
64 / 66
Momentum (4w)
↑+356 +216%
521 opens last 4w · 165 prior 4w
Salary range · avg $253k
$122k–$414k
USD · disclosed roles only
Tracked since
Feb 3
last role today
Hiring velocityscroll left for older weeks
Jobs (734)
| Title | Stage | AI score |
|---|---|---|
| Principal Analog Circuit Design Engineer - SerDes Seeking a Principal Analog Design Engineer to lead the design and validation of high-speed analog circuits for SerDes applications. Requires expertise in analog/mixed-signal design, high-speed communication standards, and silicon bring-up. Will mentor junior engineers and collaborate with cross-functional teams. | — | 0 |
| SoC Debug Engineer Early-career FPGA Developer role focused on RTL design and verification (VHDL/Verilog/System Verilog) for a proprietary JTAG-based debug tool used in microprocessor and SoC bring-up and validation. Responsibilities include implementing FPGA RTL, assisting with integration, writing simulations, debugging RTL and hardware issues, and contributing to FPGA build flows. The role involves collaboration with software, validation, and hardware teams. | — | 0 |
| Software Application Development Engineer Software Application Development Engineer for Intel's Foundry Automation team, focusing on developing and implementing solutions for automated factories. The role involves partnering with end-users, gathering requirements, analyzing processes, managing projects, and providing L3 support in a 24/7 manufacturing environment. Requires PL/SQL and RDBMS schema design experience, with a strong emphasis on collaboration and technical problem-solving within manufacturing systems. | — | 0 |
| Software Engineer Software Performance Engineer role focused on optimizing application workloads through device driver enhancements, performance analysis, and optimization techniques. Requires strong C/C++ and Python skills, system-level programming, and understanding of computer architecture and compilers. | — | 0 |
| Density Fill Development Engineer Intern This internship focuses on the development and optimization of engineering tools like compilers, debuggers, profilers, and build systems to improve developer productivity and streamline workflows. The role involves collaborating with cross-functional teams to align tool capabilities with platform needs and solve complex technical challenges. | — | 0 |
| Lab Engineering Technician Lab Engineering Technician at Intel supporting the development of next-generation packaging technologies by preparing samples, executing experimental measurements, maintaining lab equipment, and helping develop new tools, fixtures, and test methods. This is a hands-on role in a dynamic R&D environment. | — | 0 |
| Senior Manager, U.S. Domestic Tax Compliance Senior Manager for U.S. Domestic Tax Compliance at Intel, responsible for leading complex tax work, ensuring accurate and timely execution of U.S. domestic tax compliance and filings, including partnerships and consolidated returns. Requires strong analytical skills, judgment, and end-to-end ownership. | — | 0 |
| Qubit Control IC Designer Design and test complex mixed-signal system-on-chip (SoC) and FPGA solutions for quantum computer control electronics, interfacing with qubits and generating control signals. Requires expertise in RF/analog/mixed-signal circuit design, silicon prototyping, and signal integrity analysis. | — | 0 |
| Strategic Account Manager - Google Account Strategic Account Manager for Google Account at Intel, focusing on driving business growth, managing executive relationships, and influencing product roadmaps for Client and Edge innovations. This role involves cross-functional coordination, go-to-market strategy execution, and customer success management within a sales and business development context. | — | 0 |
| RTL Design Engineer Develops logic design, RTL coding, and simulation for CPU cell libraries, functional units, and IP blocks. Participates in architecture and microarchitecture definition, optimizes logic for power, performance, area, and timing, and reviews verification plans. Documents microarchitectural specs and supports SoC customers. | — | 0 |
| Revenue and Data Analyst This role is for a Revenue and Data Analyst who will analyze business problems, gather requirements, identify automation opportunities, test prototypes, conduct user acceptance testing, and manage projects. The role involves working with business and development teams, providing input to system design, and monitoring project KPIs. Familiarity with Microsoft Excel and Power Platform is required, with programming concepts being a plus. The role is within Intel's Sales and Marketing Group. | — | 0 |
| Yield Development Engineer This role focuses on driving manufacturing excellence and yield improvements in semiconductor packaging through data-driven initiatives, advanced analytics, and model-based problem solving. The engineer will extract insights from manufacturing data, monitor yield performance, and communicate findings to shape manufacturing decisions. | — | 0 |
| SOC Functional Validation Engineer- Security Seeking a skilled SoC Security Validation Engineer with expertise in SoC architecture, OS fundamentals, CPU memory subsystems, and advanced security technologies like secure boot, trusted computing, and confidential computing. Responsibilities include leading security validation, developing threat models, designing penetration tests, validating security mechanisms, and developing automated test scripts using C, C++, and Python. Requires 7+ years of experience and strong programming skills. | — | 0 |
| Board Level Power Delivery Design Engineer Hardware Board Design Engineer with expertise in Power Delivery design and debug for Intel Core and Atom CPUs. Responsibilities include schematic capture, PCB design, power integrity simulation, board power-on and debugging, and customer technical support. | — | 0 |
| IP Design Verification Engineer This role focuses on the functional verification of IP and subsystem logic for AI-accelerated systems within Intel's Data Center Group. The engineer will develop verification plans, test benches, and environments, execute these plans through simulation, and debug issues in the presilicon environment. Collaboration with architects, RTL developers, and physical design teams is key, as is maintaining and improving the verification infrastructure. | — | 0 |
| System Modelling Engineer This role is for a System Modelling Engineer at Intel, focusing on the architecture, modeling, and performance analysis of 224Gbps SerDes IP. The engineer will develop end-to-end PHY system models, analyze electrical channels, optimize equalization algorithms, and perform clocking, jitter, and noise analysis. The role also involves supporting industry standards, defining test methodologies, and collaborating with cross-functional teams. The position requires a strong background in analog circuit design and high-speed design techniques. | — | 0 |
| Payroll Specialist (Contract) This role is for a Payroll Specialist within Intel's HR Services organization, focusing on delivering day-to-day administration for payroll and benefits processes across assigned countries. Responsibilities include managing daily tasks, working with external vendors, understanding legal and tax requirements, handling employee queries, partnering with HR teams, ensuring compliance with audit requirements, and recommending process improvements. The role requires a Bachelor's degree in a relevant field, strong attention to detail, proficiency in English, business partnering skills, computer literacy, and advanced Microsoft Excel skills. Experience in payroll accounting, SOX, and automation are considered advantages. | — | 0 |
| Module Engineering Intern Internship role focused on supporting the development and implementation of manufacturing processes for semiconductor modules, including equipment troubleshooting, maintenance, and optimization of process control. Requires a chemical science discipline and analytical skills. | — | 0 |
| Graduate Talent (IP Design Verification Engineer) This role involves the design, development, and verification of Mix Signal IPs, including proprietary Intel IPs, for Intel's client products. Responsibilities include collaborating with cross-functional teams, developing and executing simulations, debugging issues, creating technical documentation, and improving IP development processes. Requires a Bachelor's degree in a relevant field and proficiency in HDLs, digital design, simulation tools, and scripting languages. | — | 0 |
| Graduate Talent (IP Logic Design Engineer) This role focuses on the design, development, and verification of Intel proprietary IPs for client products, involving collaboration with cross-functional teams, documentation, simulation, testing, and automation. It requires proficiency in HDLs like Verilog/VHDL and scripting languages like Python. | — | 0 |
| Systems and Hardware Enabling Engineer Intel is seeking a Systems and Hardware Enabling Engineer to design and develop firmware for next-generation client platforms, interfacing directly with hardware components like microcode, FPGA, and IP-specific firmware. The role involves abstracting low-level hardware details, ensuring seamless integration, and optimizing performance and reliability. Responsibilities include firmware design, development, testing, validation, and collaboration with cross-functional teams, adhering to secure development lifecycle practices. | — | 0 |
| Supply Chain Engineer Supply Chain Engineer responsible for direct material issues in the ATM assembly test process, managing quality, new product introductions, cost reduction, and continuous improvement. The role involves defining inspection methodologies, optimizing the supply chain, and collaborating with suppliers. It also includes leading and mentoring junior engineers and contributing to future technology definitions. | — | 0 |
| GPU Logic Design Engineer Develops and optimizes RTL code for GPU IPs, ensuring alignment with architecture and microarchitecture specifications. Performs power, performance, area, and timing optimization, and executes unit-level verification. Collaborates with SoC customers for seamless integration. | — | 0 |
| CPU Core Logic Designer Seeking a CPU Core Logic Designer to develop logic design, RTL coding, and simulation for CPU IP blocks. Responsibilities include defining architecture and microarchitecture features, optimizing logic for power, performance, area, and timing, and reviewing verification plans. The role requires experience with System Verilog/Verilog/VHDL, logic design, and computer architecture. | — | 0 |
| Process Integration Development Manager Manager for Process Integration Development Engineering within Intel's Fab Sort Manufacturing (FSM) organization, focusing on qualifying innovative integrated process solutions for advanced and mature node semiconductor technologies to meet quality, yield, and output targets. The role involves leading a team, collaborating with global development teams, developing yield analysis tools, and driving root cause analysis for yield and performance issues. | — | 0 |
| IP Design Verification Engineer Seeking an IP Design Verification Engineer to ensure the functional integrity of intellectual property designs. Responsibilities include developing verification environments, executing test plans, debugging issues, and collaborating with cross-functional teams. The role also involves exploring and implementing AI/ML-driven verification techniques and custom automation scripts to improve efficiency. | — | 0 |
| Test Module Development Engineer Develops and implements test technology for advanced semiconductor packaging, focusing on high-mix, low-volume testing and future technologies. This role involves process integration, equipment solutions, feasibility studies, and modifications to improve efficiency and output, supporting Intel's advanced packaging roadmap for AI and edge computing. | — | 0 |
| Physical Design Timing Engineer This role focuses on the physical design and timing analysis of DDRPHY IP, ensuring high performance and low power consumption. Responsibilities include chip/block-level timing analysis, optimization, clock network design, and collaboration with various engineering teams. The role requires expertise in static timing analysis tools, clock design, and TCL scripting. | — | 0 |
| CPU Validation Engineer This role focuses on the functional validation of CPUs, ensuring performance, power, and area goals are met. Responsibilities include developing validation methodologies, executing test plans, performing silicon debug, and collaborating with various engineering teams throughout the product lifecycle. The role requires knowledge of CPU architecture, coding in C/C++ or Python, and experience with hardware/software validation tools. | — | 0 |
| CPU Validation Engineer Intel is seeking a CPU Validation Engineer to define, develop, and perform functional validation for CPUs, focusing on CPU internals and integration in system-level features. The role involves applying hardware and software tools, developing validation methodologies and test plans, executing these plans, and collaborating with other engineers for design optimization and troubleshooting. Responsibilities include silicon debug, root cause analysis, testing feature interactions, developing post-silicon validation infrastructure, publishing validation reports, and working with cross-functional teams (architecture, design, verification, board, platform, manufacturing) to improve debug and validation strategies. The engineer will also develop content to increase specific IP interactions and engage in all product life cycle phases, including bug hunting in simulation, emulation, and FPGAs. | — | 0 |
| Practical Engineering Student for Intel Kiryat Gat Seeking a Practical Engineering student for a semiconductor manufacturing facility to support advanced equipment, learn maintenance and troubleshooting, and collaborate with engineering teams. Role involves hands-on experience in a high-volume, cutting-edge fabrication environment. | — | 0 |
| Design Verification Student Worker Student worker role focused on pre-silicon verification of hardware designs for Intel's next-generation IPs, ensuring bug-free final designs through RTL validation, test plan development, and debugging. | — | 0 |
| Packaging Module Development ENgineer Develops and optimizes processes and equipment for Intel's advanced packaging platform technologies, focusing on manufacturability, reliability, quality, cost, yield, and productivity. Collaborates with cross-functional teams to solve engineering challenges and design processes. | — | 0 |
| Packaging Module Development Engineer Develops and optimizes semiconductor packaging technologies, focusing on interconnects and thermal solutions. Collaborates on equipment, materials, and processes for high-volume manufacturing, requiring a PhD or Master's in a related engineering/science field and experience in mechanical design or manufacturing systems. | — | 0 |
| Facility Category Manager This role is for a Facility Category Manager at Intel, responsible for managing supply chain strategies, supplier relationships, and procurement processes for facilities services, real estate, construction, and maintenance programs. The candidate will develop commodity strategies, manage supplier performance, and ensure cost-effectiveness and sustainability. | — | 0 |
| Server Product Manager Seeking a strategic Server Product Manager to drive product platform strategies and manage critical supply chain operations for Intel's Data Center and Network Supply team. This role involves optimizing supply and demand across the data center product portfolio, managing product supply health, developing supply strategies, and collaborating with cross-functional teams. | — | 0 |
| Infrastructure and DevOps Engineer This role is for a Senior Infrastructure and Design Automation Engineer within Intel Foundry Automation - Government Programs. The engineer will be responsible for planning, provisioning, installation, configuration, maintenance, and operations of software infrastructure for building, validating, and releasing hardware and software products. Key tasks include identifying automation opportunities, implementing solutions for increased automation and reliability, deriving infrastructure design requirements, and maintaining systems within Intel's enterprise infrastructure constraints. The role requires experience with EDA tools, scripting languages (Python, Perl, Tcl, shell), Linux OS, networking, workload management platforms, and license management. Experience with government security clearances and customer-facing roles is preferred. | — | 0 |
| Analog Circuit Design Engineer Analog Circuit Design Engineer at Intel focusing on PLLs and clocking circuits, involving design, validation, and reliability. Requires strong fundamentals in CMOS design and semiconductor device physics. | — | 0 |
| Analog Circuit Design Engineer Analog Circuit Design Engineer responsible for designing and developing analog circuits in advanced process nodes for analog and mixed-signal IPs, optimizing for power, performance, area, timing, and yield. Requires experience in PLLs, clocking circuits, LC VCO/DCO design, and CMOS fundamentals. | — | 0 |
| Analog Circuit Design Engineer Analog Circuit Design Engineer at Intel focusing on high-speed interconnect solutions, designing and verifying analog circuits in advanced process nodes. Responsibilities include transistor-level design, simulation, optimization, and post-silicon validation for SerDes PHY analog blocks. | — | 0 |
| Analog Circuit Design Engineer Intel is seeking an Analog Circuit Design Engineer to design, simulate, and verify analog circuits for advanced process nodes, focusing on high-speed SerDes (112/224Gbps). The role involves optimizing circuits for power, performance, area, and yield, and collaborating with cross-functional teams. Experience with EDA tools and CMOS technologies is required. | — | 0 |
| Analog Circuit Design Engineer Analog Circuit Design Engineer at Intel, focusing on designing, developing, and optimizing high-speed analog circuits in advanced process nodes for next-generation memory interface PHYs. Responsibilities include circuit design, simulation, optimization for power/performance/area, test plan creation, collaboration with cross-functional teams, layout reviews, and post-silicon debug. | — | 0 |
| Manufacturing Operator (Contract) Manufacturing Operator role focused on product manufacturing, assembly, equipment operation, data collection, and process optimization in an industrial setting. Requires technical aptitude and adherence to SOPs. | — | 0 |
| SerDes Circuit Design Engineer Design, develop, and optimize high-speed SerDes circuits for Intel's next-generation technologies, collaborating with cross-functional teams and supporting silicon validation. | — | 0 |
| IP Functional Validation Engineer This role focuses on the functional validation of Accelerator IPs within Intel's Data Center Group. The engineer will define, develop, and perform validation for IP internals and their integration into system-level features, covering both pre- and post-silicon stages. Responsibilities include developing test plans, methodologies, and infrastructure, performing silicon debug, and collaborating with other engineering teams. The role requires strong programming skills in C/C++/Python for automation and experience with hardware architectures and lab equipment. | — | 0 |
| IP Logic Design Engineer Intel is seeking an experienced Micro Architect/Senior Design Engineer to design, develop, and implement advanced Digital IO Controllers like PCIe/CXL/UCIe systems for next-generation data center and AI chips. This role requires microarchitectural expertise and hands-on RTL coding skills, with a deep understanding of high-speed IOs and interconnect protocols. Responsibilities include architecting memory coherency protocols, designing critical components of PCIe/UCIe controllers, collaborating with cross-functional teams, and staying updated on emerging technologies in AI/ML hardware. | — | 0 |
| Analog Circuit Design Engineer Analog Circuit Design Engineer at Intel, responsible for designing, developing, and optimizing high-speed analog circuits in advanced process nodes. This role involves circuit design, validation, simulation, optimization for power/performance/area/timing/yield, test plan creation, cross-functional collaboration, and post-silicon debug. Requires expertise in high-speed analog circuits like TX/RX blocks, PLLs, DLLs, SerDes, and voltage regulators, with proficiency in industry-standard tools. | — | 0 |
| Analog Circuit Design Engineer Analog Circuit Design Engineer at Intel responsible for designing, developing, and optimizing high-speed analog circuits in advanced process nodes, contributing to next-generation memory interface PHYs and analog/mixed-signal IPs. Involves circuit design, simulation, validation, optimization for power/performance/area, test plan creation, collaboration with cross-functional teams, layout reviews, and post-silicon debug. | — | 0 |
| Analog Circuit Design Engineer Analog Circuit Design Engineer at Intel responsible for designing, developing, and optimizing high-speed analog circuits in advanced process nodes, contributing to next-generation memory interface PHYs and analog/mixed-signal IPs. Involves circuit design, simulation, validation, optimization for power/performance/area, test plan creation, collaboration with cross-functional teams, layout reviews, and post-silicon debug. | — | 0 |
| Network Device Driver Development Engineer Develop, optimize, and maintain high-performance network solutions and device drivers for Intel's innovative products. Responsibilities include driver development across OS platforms, optimizing packet processing, debugging software stacks, implementing Ethernet standards, and working with virtualization technologies. Collaboration with firmware, hardware, validation teams, and OS vendors is key. The role also involves analyzing and improving OS kernel components and contributing to programming standards. | — | 0 |