Intel
- HQ
- Santa Clara, US
- Founded
- 1968
- Size
- 120,000+
- Website
- intel.com
Currently tracking 56 active AI roles, down 27% versus the prior 4 weeks. Primary focus: Serve · Engineering. Salary range $122k–$414k (avg $253k).
Intel currently has 84 active job listings related to artificial intelligence. The majority of these roles, 51%, are focused on serving infrastructure, with agents representing another significant portion at 24%. Engineering is the most frequent function for these positions. The company is actively hiring in the United States, China, and Mexico. Frequent technical tags include model serving, inference infrastructure, and agent orchestration. In the last 30 days, Intel has added 73 new AI roles, representing a 52% increase compared to the previous 30-day period.
Intel currently has 59 active AI-related roles in our index. The most common open titles are: AI Software Engineering Intern (3), AI Software Engineer Intern (2), GenAI Software Solutions Engineer (2), Graduate Talent (GenAI Software Solutions Engineer) (2), AI Algorithm Engineer. Most positions are in Engineering and Research.
Intel's active AI hiring is concentrated in: serving infrastructure (49%), agents (29%), application (8%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
Intel is hiring AI talent in: United States (28 roles), China (7 roles), Mexico (6 roles), Malaysia (6 roles).
Job postings at Intel most frequently reference: model serving, inference infra, agent orchestration, rag, tool use.
In the past 30 days, Intel has posted 28 new AI-related roles. That is a -63% change versus the prior 30 days (75 → 28).
| Title | Stage | AI score |
|---|---|---|
| Memory Circuit Design Engineer Seeking a Memory Circuit Design Engineer to design, develop, and build custom memory circuits (SRAMs, ROMs, Caches) for Intel CPUs and SOCs. Responsibilities include technical readiness, simulation, characterization, PPA optimization, and innovation in memory design on advanced CMOS process technologies. | — | 0 |
| Mixed Signal Design Verification Engineer This role involves performing functional verification of mixed-signal logic components, including analog behavioral modeling, to ensure design specifications are met. Responsibilities include developing IP verification plans, test benches, and verification environments, executing verification plans, running system simulation models, analyzing power and timing, debugging issues, and collaborating with digital and analog architects, RTL developers, and physical design teams. The role also requires maintaining and improving verification infrastructure and methodology. | — | 0 |
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| ADCE Packaging Design Architect Drives end-to-end development for substrate design from concept through tape out and implements physical layout and routing of the package design. Performs substrate fit and routing studies to establish design, performance, and cost tradeoffs. Works closely with silicon and hardware teams to optimize silicon-package-board performance and pinout. Defines substrate design rules, conducts internal and external reviews, analyzes data, and resolves DRCs to optimize package design. Completes documentation and collateral into the product lifecycle management system of record. | — | 0 |
| Advanced Packaging Supplier Technology Development Program Manager The Advanced Packaging Substrate Integration Team is seeking a Program Manager to oversee on-time supplier capacity expansion for advanced heterogeneous packaging technology (EMIB-T). This role involves qualifying new process tools, supplier lines, and factories to meet foundry customer demand. Responsibilities include scoping, planning, CapEx project execution, capability transfer from internal lines to suppliers, and regular management updates. The position requires strong project management, technical risk assessment, problem-solving, and supplier/stakeholder management skills, with extensive interaction with supplier and internal teams, including international travel. | — | 0 |
| FCO Strategic/Development Functional Area Industrial Engineer This role is for an Industrial Engineer focused on factory capacity planning, capital equipment planning, and site space optimization within Intel's manufacturing operations. The role involves analyzing business data, developing data-driven models, forecasting build plans, and collaborating with cross-functional teams to drive manufacturing strategies and operational excellence. While the company mentions "AI everywhere" and "AI product development" in a general context, the core responsibilities of this role are centered on traditional industrial engineering principles for manufacturing and capacity planning, not on building or directly working with AI/ML models or systems. | — | 0 |
| OTF IFA AMHS Equipment Technician This role involves performing electrical and mechanical troubleshooting, repair, and maintenance of manufacturing equipment within Intel's Automated Material Handling System (AMHS) in a cleanroom environment. The technician will also support engineering teams with experiments and data collection, and collaborate during factory ramps. | — | 0 |
| Product Development Engineer Product Development Engineer in the Parametric Test area supporting electric test programs for discrete devices to measure and improve performance and reliability of new process technologies and designs. Responsibilities include defining test content, validating designs, developing test programs, validating results on silicon, and improving testing methods and systems. Also involves defining high volume systems and meeting capacity constraints. | — | 0 |
| Foundry Strategic Industrial Engineer Intel Foundry is seeking a Strategic/Development Industrial Engineer to coordinate data, systems, decision analysis, business processes, and modeling with a focus on capacity and cost. The role involves driving strategies to enhance manufacturing and operational capabilities, forecasting, designing plans aligned with market trends, and empowering stakeholders with data-driven decisions. Responsibilities include developing and maintaining data systems, models, and business processes, providing strategic guidance through data analysis, facilitating business processes, coordinating scenario-based analysis, developing financial models, and defining long-range capacity strategy. | — | 0 |
| Physical Design Engineer- Foundry Services Physical Design Engineer for Intel Foundry Services, focusing on Si Interposer and Bridge designs. Responsibilities include full physical design flow (floor planning, place and route, verification, analysis), optimization for performance/power/area, and methodology development. Requires a Bachelor's or Master's degree in Electrical Engineering or related field with significant experience in EDA tools and physical design aspects. | — | 0 |
| Mixed Signal Design Verification Engineer Mixed Signal Design Verification Engineer responsible for ensuring the quality and functionality of mixed signal components like PCIE, UCIE, and USB4/Type-C PHYs using methodologies like System Verilog, UVM, and Verilog. The role involves developing verification plans, test benches, simulation models, and conducting root cause analysis. Scripting skills in Python, Perl, or Tcl are required, along with familiarity with standard protocols and EDA tools. | — | 0 |
| Power Delivery Engineer This role focuses on designing and developing power delivery solutions for Intel's platforms, ensuring optimal energy efficiency and performance. Responsibilities include defining, analyzing, and implementing power delivery networks, designing power conversion and management solutions, and collaborating with architects. The role requires expertise in power delivery modeling, PCB design tools, and debugging power systems. | — | 0 |
| Packaging Thermal Engineer Seeking a Thermal Engineer with 5+ years of experience in semiconductor packaging thermal analysis, simulation (CFD), and measurement validation. Responsibilities include designing Thermal Test Vehicles (TTVs), architecting product designs with thermal simulation, scouting thermal innovations, and developing compact thermal models. Requires expertise in heat transfer, electronics cooling, CFD tools, and thermal measurement techniques. | — | 0 |
| Mask Manufacturing Technician This role involves performing manufacturing and assembly tasks in a production process, ensuring products meet industry standards and customer specifications. Responsibilities include operating equipment, collecting and evaluating operating data for process optimization, maintaining production efficiency, setting up and operating production equipment, supporting installation and maintenance of equipment, driving utilization of automated systems, producing product that meets output requirements, supporting process improvements, troubleshooting production line issues, and conducting quality checks on raw materials and final products. | — | 0 |
| CPU Core Senior Physical Design Engineer Senior Physical Design Engineer for CPU core development, responsible for the full physical design flow from RTL to GDS, including synthesis, place and route, timing analysis, power analysis, and verification. Collaborates with other engineering teams and EDA vendors to optimize CPU design for power, frequency, and area. | — | 0 |
| Mechanical Project Engineer Mechanical Project Engineer for Intel's Global Construction Engineering organization, responsible for the design and engineering of semiconductor manufacturing facilities. This role involves assessing project feasibility, developing scope, providing technical guidance to supply chain partners, and ensuring cost management for mechanical systems like HVAC, chillers, boilers, and process vacuum systems. The position requires collaboration across disciplines and a focus on safety and innovation within the semiconductor industry. | — | 0 |
| Module Development Engineer This role focuses on the development and optimization of advanced semiconductor manufacturing processes, including material selection, parameter adjustments, equipment metrology, and system design. It involves feasibility studies, process technology development, and collaboration with suppliers to integrate new technologies into manufacturing. The role requires a PhD in a STEM discipline and fundamental knowledge of plasma physics, surface reactions, thin film processes, and semiconductor materials. | — | 0 |
| NPI/Foundry Operational Analyst This role supports new product/process introduction and start-up readiness in a manufacturing environment. Responsibilities include optimizing business processes, analyzing data for improvements, and preparing reports. It requires strong analytical skills and proficiency in Microsoft Office and data analysis tools. | — | 0 |
| Senior Physical Design Engineer Senior Physical Design Engineer at Intel responsible for the physical design of custom IP and SoC designs, impacting products in Client, Data Center, AI, and Automotive sectors. The role involves the full RTL to GDS flow, optimizing power, performance, and area, and technical leadership for SoC/Subsystem implementation. | — | 0 |
| SOC Design Verification Engineer Intel is seeking a SOC Design Verification Engineer in Bangalore, India, to ensure the functionality, quality, and security of cutting-edge System-on-Chip (SoC) designs. Responsibilities include developing verification plans, test benches, and environments; executing verification plans using emulation and simulation; debugging presilicon issues; collaborating with cross-functional teams; and enhancing verification infrastructure. The role requires proficiency in System Verilog, OVM/UVM, and SoC test environment development, along with strong hardware design knowledge. | — | 0 |
| Senior Post Silicon CPU Debug Engineer Seeking a Senior CPU Debug Engineer to lead logical debugging of Core CPU designs, collaborate with Architecture and Design teams, and provide customer debug support. Responsibilities include analyzing and resolving complex logic issues, developing debugging tools, and improving debug processes. | — | 0 |
| Ethernet Product Manager Product Manager for Intel's Ethernet controllers and adapters, focusing on defining software requirements, managing the product lifecycle, conducting market research, and driving adoption. Requires strong technical background, market insight, and collaboration with engineering, marketing, and sales. | — | 0 |
| IA Core Post Silicon Validation Engineer Intel is seeking a Post Silicon Validation Engineer for their All Cores Engineering (ACE) Group. This role focuses on core level validation of leading CPU products for Xeon Server products. Responsibilities include developing validation plans, powering on new systems, validating product features, and debugging functional bugs. The role requires expertise in CPU Post-Si debug and validation, test generators, and various validation techniques. | — | 0 |
| Post-silicon Validation and Debug Engineer This role focuses on post-silicon validation and debug engineering for Intel's System-on-Chip (SoC) products, ensuring seamless performance by working at the intersection of hardware, firmware, and software. Responsibilities include performing low-level debug, developing validation plans, implementing debug techniques, conducting root cause analysis, and collaborating with cross-disciplinary teams. | — | 0 |
| Principal Engineer, Hybrid Bonding Module This Principal Engineer role focuses on defining and scaling next-generation advanced packaging technologies, specifically die-to-wafer hybrid bonding (HBI), for high-performance computing, AI, and chiplet architectures. The role involves driving hybrid bonding capability from platform development through high-volume manufacturing, focusing on equipment and process development, yield and reliability improvement, and platform innovation. | — | 0 |
| FCO Functional Area Industrial Engineer This role is for a Factory Capacity Optimization (FCO) Functional Area Industrial Engineer focused on Assembly. The candidate will design, develop, validate, and deploy models to solve complex manufacturing and supply chain problems. Responsibilities include identifying risks and opportunities for toolset roadmaps, defining long-range capacity strategy, forecasting build plans, leveraging data analysis for insights, creating capacity requirements, developing execution plans, monitoring toolset performance, and investigating/designing production capacity models and data systems. The role also involves developing mathematical equipment run rate models and supporting ramp/end-of-life plans. | — | 0 |
| SoC Functional Validation Intern Internship role supporting the functional validation of System on Chip (SoC) devices and systems, involving test content development, data analysis, and validation infrastructure. Requires programming experience in Python, C, or C++ and advanced English. | — | 0 |
| Supply Chain Engineer Supply Chain Engineer role at Intel focused on optimizing semiconductor manufacturing processes, managing supplier quality, and driving cost control and yield improvements. Requires experience in semiconductor factory operations, supply chain engineering, or supplier management, with a strong emphasis on root cause analysis and performance tracking. | — | 0 |
| Software Enabling and Optimization Engineer This role focuses on enabling next-generation programmable Infrastructure Processing Units (IPUs) for Intel's Networking Solutions Group (NSG) by working with lead customers. The engineer will define and develop IPU solutions, perform system-level testing, collaborate with engineering teams and customers for debugging, create technical collaterals, and engage with industry technologists to evaluate feasibility and influence engineering direction. The role requires strong programming skills in Python, experience with build tools, and knowledge of Linux networking stacks. | — | 0 |
| Mixed Signal Logic Design Engineer This role focuses on the design of mixed-signal logic for high-speed IP at Intel. Responsibilities include developing architecture and microarchitecture specifications, implementing designs in RTL, behavioral modeling, simulation, debugging, and supporting physical design and validation teams. The role requires experience with digital design concepts, SystemVerilog, computer architecture, and analog/mixed-signal design. Experience with AI tools for productivity is a plus. | — | 0 |
| Senior Mixed Signal IP Enablement and Debug Engineer This role focuses on the integration and debug of Mixed Signal Intellectual Property (IP) for Intel's Hard IP Development Group. Responsibilities include partnering with customers and design teams, developing test plans using AI-driven tools and scripting, conducting design reviews, performing simulations, leading silicon validation and debug, and driving root cause analysis for IP-related issues. The role requires experience in IP integration, pre-silicon verification, post-silicon validation, and debug of serial or parallel IOs, along with lab hardware and software experience. | — | 0 |
| Senior Staff Mixed Signal IP Enablement and Debug Engineer This role focuses on enabling and debugging mixed-signal IP (Intellectual Property) for Intel's Hard IP Development Group. Responsibilities include customer support, IP documentation, integration and debug support, developing test plans using AI-driven tools and scripting, conducting design reviews, and performing signal/power integrity simulations. The role also involves silicon validation, leading issue identification and resolution, and root cause analysis. The ideal candidate will have experience in IP integration, pre-silicon verification, post-silicon validation, and debug of serial or parallel IOs, with strong lab hardware/software skills and experience with test equipment. | — | 0 |
| MDM Software Application Development Engineer This role is for an MDM Software Application Development Engineer at Intel, focusing on designing, configuring, and developing SAP MDG and S4 HANA solutions. Responsibilities include defining software application solutions, recommending design choices for manageability and scalability, identifying business requirements, configuring systems, collaborating with stakeholders, performing pathfinding, and troubleshooting production issues. The role also involves acting as a technical lead for subsystems and managing projects. The ideal candidate will have extensive experience with SAP MDM and S4 HANA, ABAP, SAP Fiori, and SQL queries, with preferred experience in data cleansing, governance, and integration. | — | 0 |
| Industrial Engineer Industrial Engineer responsible for developing metrics to measure factory capacity and output, identifying bottlenecks, and implementing plans for facility modifications and operating methods. The role involves integrating new products, analyzing capacity requirements, leading teams to remove roadblocks, conducting capacity assessments, validating product performance, studying equipment mechanisms, designing equipment metric models, and providing solutions for virtual factory capacity and resource optimization to meet schedules and cost targets. Requires structured problem solving, data analysis and visualization, and experience in capacity improvement projects. | — | 0 |
| Direct Lid/Stiffener Attach Packaging Module Development Engineer Develops and establishes process flow, FMEA assessment, procedures, drawings review, and equipment configuration for direct lid/stiffener attach module in semiconductor packaging. Selects and develops materials and equipment, conducts experiments, establishes process control systems, and supports new factory start-up. | — | 0 |
| EDA Tools Hardware Engineer This role focuses on the design, implementation, verification, and support of EDA (Electronic Design Automation) tools and hardware design methodologies. The engineer will work on optimizing design automation workflows, improving efficiency, power, and performance of hardware designs, and collaborating with EDA vendors. The role requires strong programming and scripting skills, and a deep understanding of digital design processes. | — | 0 |
| New Mexico Manufacturing Technician Internship Internship role focused on manufacturing operations within Intel's Advanced Packaging Technology Manufacturing (APTM) plant. Responsibilities include equipment setup, monitoring production processes, quality checks, and assisting with troubleshooting and optimization. The role involves hands-on experience in a fast-paced, challenging environment supporting wafer movement and production goals, with a focus on learning and skill development. | — | 0 |
| CPU Physical Design Engineer This role is for a CPU Physical Design Engineer at Intel. The engineer will be responsible for the physical design implementation of custom CPU designs from RTL to GDS, including synthesis, place and route, clock tree synthesis, static timing analysis, and power/clock distribution. The role involves verification and signoff, optimization for power, frequency, and area, and working with EDA vendors to enhance tool capabilities. While the company works in AI, this specific role focuses on the hardware design of CPUs that may be used in AI applications, rather than the AI/ML development itself. | — | 0 |
| Identity Security - PKI Engineer The Identity Security - PKI Engineer role at Intel focuses on designing, deploying, and managing enterprise-grade Public Key Infrastructure (PKI) solutions. This involves leading certificate lifecycle management, automating PKI tasks, integrating PKI with various platforms, and enforcing security policies. The role requires a Bachelor's or Master's degree and relevant experience in PKI integration, X.509 certificates, and key management standards. A US Government Security Clearance is required. | — | 0 |
| CPU Physical Design Engineer This role involves the physical design implementation of custom CPU designs from RTL to GDS, covering synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power/noise analysis. It also includes verification and signoff, working with EDA vendors, and optimizing CPU designs for power, frequency, and area. The role requires collaboration with various engineering teams and participation in methodology improvements. | — | 0 |
| CPU Physical Design Engineer This role involves the physical design implementation of custom CPU designs from RTL to GDS, covering synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power/noise analysis. It also includes verification and signoff, working with EDA vendors, and optimizing CPU design for power, frequency, and area. | — | 0 |
| Enterprise Systems Analyst This role is for an Enterprise Systems Analyst at Intel, focusing on supply chain transformation and the internal foundry model. The analyst will work with Windchill PLM, gather requirements, document processes, develop training, and support end-users. The role involves data and system management, and integration with other enterprise systems. While the company mentions AI, this specific role is focused on PLM and supply chain systems, not direct AI/ML model development or deployment. | — | 0 |
| Materials Planning Analyst This role focuses on supply chain planning and optimization, including developing schedules, forecasts, and managing inventory to meet customer demands and business objectives. It involves data analysis, scenario planning, and collaboration with suppliers and internal teams. | — | 0 |
| Standard Cell Library Engineer This role focuses on the development and validation of tools, flows, and collaterals for standard cell library reliability, including electromigration, thermal effects, and voltage drop. Responsibilities involve workflow optimization, vendor and foundry engagement, and documentation/collateral generation and validation. | — | 0 |
| GPU Software Development Engineer This role focuses on graphics driver/application validation and debug, integrating upcoming graphics features, triaging failures, and developing debug tools to improve graphics validation efficiency. It involves scaling across display, media, 3D, compute, and power conservation components, and enabling new features for AI domains to improve functionality and performance on graphics products. | — | 0 |
| Mixed Signal Logic Design Engineer Develops logic design, RTL coding, and simulation for mixed signal and/or highspeed IPs for integration in full chip designs. Participates in architecture and microarchitecture definition, applies strategies for mixed signal designs, writes RTL, and optimizes logic to meet power, performance, area, and timing goals. Reviews verification plans, resolves failing RTL tests, and supports SoC customers for IP block integration. | — | 0 |
| Post-silicon Validation and Debug Engineer This role is for a Post-Silicon Validation Engineer at Intel, focusing on ensuring the quality and functionality of CPU products for laptops, desktops, and gaming systems. Responsibilities include developing and executing validation plans, designing and debugging tests, analyzing issues, leading debug task forces, driving automation, and mentoring junior engineers. Requires experience in post-silicon validation, CPU/SOC architecture, and scripting languages. | — | 0 |
| Sr. Software Engineering Manager – Infrastructure and Security Sr. Software Engineering Manager for Intel's Foundry Automation Infrastructure and Security group, leading teams responsible for scalable distributed systems, cloud-native infrastructure, and security frameworks in a high-volume automated manufacturing semiconductor fab environment. Requires deep technical expertise in systems architecture and experience scaling engineering organizations. | — | 0 |
| CPU Memory Design Engineer This role focuses on designing, developing, and building custom memory circuits (SRAMs, ROMs, register files, caches) for Intel CPUs and SOCs. Responsibilities include technical readiness, circuit design, characterization, simulations, PPA optimization, and methodology definition within advanced CMOS process technologies. | — | 0 |
| CPU Memory Design Engineer CPU Memory Design Engineer responsible for designing, developing, and building full-custom and compiler-based SRAMs, Large Signal Arrays, ROMs, custom memories, digital circuits, and Caches for Intel CPUs and SOCs. Involves technical readiness, circuit design, characterization, simulations, cache design, critical path simulations, PPA optimization, bit-cell and periphery IC design, automation, IP design, and methodology definition. | — | 0 |