Intel
- HQ
- Santa Clara, US
- Founded
- 1968
- Size
- 120,000+
- Website
- intel.com
Currently tracking 56 active AI roles, down 27% versus the prior 4 weeks. Primary focus: Serve · Engineering. Salary range $122k–$414k (avg $253k).
Intel currently has 84 active job listings related to artificial intelligence. The majority of these roles, 51%, are focused on serving infrastructure, with agents representing another significant portion at 24%. Engineering is the most frequent function for these positions. The company is actively hiring in the United States, China, and Mexico. Frequent technical tags include model serving, inference infrastructure, and agent orchestration. In the last 30 days, Intel has added 73 new AI roles, representing a 52% increase compared to the previous 30-day period.
Intel currently has 59 active AI-related roles in our index. The most common open titles are: AI Software Engineering Intern (3), AI Software Engineer Intern (2), GenAI Software Solutions Engineer (2), Graduate Talent (GenAI Software Solutions Engineer) (2), AI Algorithm Engineer. Most positions are in Engineering and Research.
Intel's active AI hiring is concentrated in: serving infrastructure (49%), agents (29%), application (8%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
Intel is hiring AI talent in: United States (28 roles), China (7 roles), Mexico (6 roles), Malaysia (6 roles).
Job postings at Intel most frequently reference: model serving, inference infra, agent orchestration, rag, tool use.
In the past 30 days, Intel has posted 28 new AI-related roles. That is a -63% change versus the prior 30 days (75 → 28).
| Title | Stage | AI score |
|---|---|---|
| IT Business Operations Manager This role is for an IT Business Operations Manager at Intel, responsible for establishing consistent strategies and practices within Global IT. The manager will partner with segment leadership to ensure financial discipline, optimize processes, identify cost-saving opportunities, and drive operational excellence. Key responsibilities include overseeing daily operations, leading health-of-business reviews, developing plans of record, identifying cost reduction opportunities, leading continuous improvement initiatives, providing counsel on people-related issues, developing employee engagement strategies, managing hiring coordination, and delivering analytical insights. The role requires a Bachelor's degree, 3+ years of industry experience, experience in organizational communication and presenting analytical data, and hands-on experience with business data and analytics, including proficiency with Microsoft Office suite and Power BI. | — | 0 |
| Senior Physical Design Integration Engineer This role focuses on the physical design integration of custom CPU designs, from RTL to GDS, for manufacturing. It involves synthesis, place and route, timing analysis, and verification, with a focus on optimizing CPU designs for power, frequency, and area. The role collaborates with various teams and EDA vendors to improve design methodologies and flow automation, contributing to AI-accelerated systems. |
| — |
| 0 |
| Atom CPU Architecture Engineer This role focuses on CPU architecture and microarchitecture engineering at Intel, involving the design, development, and optimization of CPU logic for performance, power, and area. Responsibilities include defining specifications, evaluating trade-offs, modeling performance, and collaborating with cross-functional teams. The role requires a degree in a relevant engineering field and experience with CPU simulators and C++. | — | 0 |
| Analog Circuit Design Engineer Analog Circuit Design Engineer responsible for designing critical foundational collateral (e.g., Metal Finger Capacitors, Thin Film Resistors, inductors) on leading edge Intel processes. This involves collaborating with process/device, PDK/modeling, EDA, and product design teams to co-optimize design and technology (DTCO) and deliver silicon proven solutions through test chips. Responsibilities include driving on-time library PDK release, ensuring timely development and test coverage, defining foundational IP, and designing/characterizing library collateral schematics and layouts. | — | 0 |
| IP Design Verification Engineer This role focuses on pre-silicon IP design verification for client SOCs, involving validation of IP/features, creating test plans, debugging failures, and developing validation tools. It requires experience with RTL code, verification methodologies, and object-oriented programming. | — | 0 |
| Senior Executive Compensation Analyst This role is for a Senior Executive Compensation Analyst responsible for designing and managing compensation programs, including base salary, variable pay, benefits, and recognition programs. The analyst will prepare materials for the Compensation Committee, conduct market research, model compensation scenarios, administer incentive plans, and ensure compliance with SEC, IRS, and FASB standards. The role requires experience with SEC regulations, proxy disclosures, and compensation analysis. | — | 0 |
| FTM Portland Community College Quick Start Semiconductor Training Program This role is for an entry-level Module Equipment Technician in semiconductor manufacturing. Responsibilities include operating, maintaining, repairing, and troubleshooting specialized processing equipment in a clean room environment, collecting data, and optimizing equipment and processes. The role requires physical stamina and adherence to clean room protocols. A high school diploma and completion of a specific training program are required. | — | 0 |
| IP Functional Validation Engineer This role is for an IP Functional Validation Engineer responsible for functional validation in pre-silicon or post-silicon environments. The engineer will understand architecture specifications, develop test plans, create infrastructure and automation, perform debugging, and work with stakeholders. Experience with High Speed IO (PCIE) and scripting languages like Python or C/C++ is required. | — | 0 |
| Global Training Engineer Intern This is an intern role focused on developing and delivering technical training programs for a manufacturing environment at Intel. The role involves assessing skill gaps, designing and delivering training using various methods, managing an LMS, and measuring training effectiveness. While AI is mentioned as a potential advantage, it is not the core focus of the role. | — | 0 |
| FW PAE Intern Internship role focused on developing, validating, and debugging embedded software and firmware for Intel's technology platforms, involving system-level challenges and collaboration with engineers. Responsibilities include assisting in design, debugging, validation, code reviews, and scripting. | — | 0 |
| Senior Logic Design Verification Engineer Senior Logic Design Verification Engineer responsible for developing verification testbenches, RTL models, and test content for power management controller IPs. The role involves validating new architectural features, debugging RTL tests, and collaborating with cross-organizational partners. Requires at least 8 years of experience with UVM and System Verilog. | — | 0 |
| Supply Chain Planning Analyst This role focuses on optimizing supply chain planning, including schedules, forecasts, materials, and capacity requirements. It involves data-driven decision-making, scenario planning, and continuous process improvement using LEAN methodologies. The analyst will also manage new product planning readiness and address execution issues to ensure smooth factory operations. | — | 0 |
| PDK LVS Development Engineer Develop and maintain Process Design Kits (PDKs) for semiconductor manufacturing, focusing on physical verification runsets (DRC/LVS/PERC) using EDA tools like Calibre/ICV/Pegasus. This role involves scripting, collaboration with technology and EDA partners, and ensuring the quality and operability of PDK collaterals for Intel's product design teams. | — | 0 |
| Product SoC Architect This role is for a Senior IPU SoC Architect responsible for defining the architectural vision for Infrastructure Processing Unit (IPU) and Data Processing Unit (DPU) platforms, focusing on compute, memory, and coherency architectures for next-generation data center solutions. The role involves strategic planning, interconnect and memory subsystem design, virtualization architecture, performance engineering, and technical leadership across cross-functional teams. While the role operates within the context of data center solutions that may support AI workloads, the core craft is SoC architecture and performance engineering, not AI/ML model development. | — | 0 |
| Manager - Mechanical and Thermal Engineering Manager for Mechanical and Thermal Engineering at Intel, leading a team in hardware design for networking products. Responsibilities include team leadership, technical strategy, and operational management for board design. | — | 0 |
| Senior Technical Solutions Engineer - Advanced Packaging This role is for a Senior Technical Solutions Engineer focused on Advanced Packaging technologies within Intel Foundry. The primary responsibility is to serve as the main customer interface, providing technical consultation on packaging solutions, managing the customer engagement lifecycle, and collaborating with internal teams to ensure customer success. While the role supports the 'AI era' by enabling advanced packaging for AI chips, it does not directly involve building or researching AI models. | — | 0 |
| Head of Government Affairs - Intel Costa Rica This role is for a Head of Government Affairs in Costa Rica, responsible for developing and implementing legislative, regulatory, and policy advocacy strategies for Intel. The position involves building relationships with government entities, representing Intel in high-level meetings, monitoring policy environments, and managing external advocacy efforts. The ideal candidate will have extensive experience in government affairs and stakeholder management. | — | 0 |
| Silicon Packaging Design Engineer This role focuses on the physical design and layout of silicon packaging, including substrate design, routing, and optimization for performance, cost, and manufacturability. It involves collaboration with silicon and hardware teams and requires experience with specific package design tools and microelectronic package physical layout. | — | 0 |
| Wafer Packaging Manufacturing US/EUR Sort Leader Lead Wafer Packaging Manufacturing (WPM) Sort factories in the US and Europe regions, responsible for E-Test, Wafer Sort, and Die Sort. Manage a team of managers, engineers, and technicians, driving continuous improvement in safety, quality, output, and cost. Ensure compliance with safety and environmental regulations, meet quality goals, and own output commits. Lead technical problem-solving and implement root cause solutions for process and tool issues. Manage process transfers and maintain process synchronization across Sort floors. | — | 0 |
| Analog Design Engineer Analog Circuit Design Engineer responsible for designing, developing, and optimizing analog and mixed-signal circuits in advanced process nodes, contributing to Intel's IP solutions and shaping the future of computing and communication systems. | — | 0 |
| WiFi System Integration Team Lead Lead a system integration team for Intel's WiFi products, focusing on delivering best-in-class wireless performance, defining and driving system POCs, and integrating new features and hardware. The role involves leading and mentoring engineers, enhancing integration capabilities, and driving group targets, with an emphasis on using automation and AI-based capabilities to improve efficiency. | — | 0 |
| Module Engineer Module Engineer responsible for critical high volume manufacturing equipment and processes in semiconductor manufacturing, focusing on efficiency, yield, and technology transfer. This role involves testing, modification, maintenance, and continuous improvement of equipment and processes to meet safety, quality, and cost goals. | — | 0 |
| Senior Equipment Spare Program Manager This role focuses on managing equipment spare parts for Intel's manufacturing operations, ensuring readiness for New Product Introduction (NPI) and High-Volume Manufacturing (HVM). It involves supply chain optimization, inventory management, cost efficiency, supplier coordination, and risk assessment for bills of materials. The position requires collaboration with engineering, project management, and manufacturing teams to align material requirements with program goals and ensure on-time delivery and operational efficiency. | — | 0 |
| Design Engineer Design Engineer at Intel responsible for microarchitecture and design of soft IP cores for Intel’s next generation chips (including SOCs). Requires relevant ASIC design/validation experience in front end processes including RTL development, functional and performance verification. Expertise in verilog and system verilog based logic design, design quality check tools, and potentially PCI_Express or AMBA standards. Knowledge of AI tools like Github Copilot is mentioned. | — | 0 |
| Graduate Talent (Payroll Specialist) This role is responsible for preparing and processing payroll, managing employee master data, ensuring accurate payments and benefits, and maintaining payroll records. It involves collaborating with finance, legal, and tax departments, conducting audits, and ensuring compliance with internal policies and external government requirements. The role also focuses on process improvement and championing lean methodologies. | — | 0 |
| GPU Validation Engineer This role is for a GPU Design Verification Engineer at Intel, focusing on ensuring the quality of advanced graphics solutions, including those for AI-based graphics products. The engineer will perform functional verification, develop test benches, debug issues, and collaborate with cross-functional teams to meet functional, performance, and power goals. The role requires a Bachelor's or Master's degree with significant experience in silicon design development, validation methodologies, and simulation/emulation debugging, along with proficiency in C/C++/Python and SystemVerilog. | — | 0 |
| Analytical Chemistry Lab Technician - Shift 7 Seeking an analytical chemist with ICPMS experience for trace metal analysis in a clean room laboratory. Responsibilities include sample preparation, analysis, maintenance of lab equipment, and ensuring compliance with standard procedures. The role supports manufacturing operations and requires strong organizational and troubleshooting skills. | — | 0 |
| GPU Software Development Engineer Software Engineer role focused on developing and maintaining tools for Intel Graphics hardware specifications, including structured content creation, consumption, validation, and code generation. The role involves full-stack web development (.NET, ASP.NET, SQL Server), Windows services, REST APIs, and integration with development infrastructure. A key aspect is leveraging AI-assisted development tools to enhance productivity. | — | 0 |
| Process Integration and Development Engineer Process Integration and Development Engineer at Intel, focusing on developing cutting-edge semiconductor process technologies. Responsibilities include feasibility studies, experiment design, material/equipment selection, and ensuring product quality and reliability. Requires a Ph.D. in a related field and experience with semiconductor fabrication and reliability. | — | 0 |
| Strategic Sales Application Engineer - Windows Platform This role is for a Strategic Sales Application Engineer focused on the Windows platform at Intel. It involves aligning silicon architecture with Microsoft's requirements, driving ecosystem enablement for next-generation PCs, and acting as a bridge between Microsoft and Intel's engineering teams to grow Intel's PC business. The role requires strong communication, influence, and strategic thinking skills, with a focus on translating technical details into business impact. | — | 0 |
| IP Design Verification Engineer Intel is seeking an IP Design Verification Engineer to join their Devices Development Group. The role involves researching, designing, developing, and testing Client SOCs, focusing on pre-silicon IP design verification. Responsibilities include validating IP/features, creating validation plans and tests, debugging failures, developing and utilizing validation tools, and engaging with IP providers. Minimum qualifications include a BS/MS in CS/CE/EE with 1-2 years of experience in IP/SoC development, verification, or integration using Verilog/SystemVerilog and OVM/UVM, along with experience in writing validation plans and object-oriented programming. | — | 0 |
| Intel Process Integration Engineer - (BE) This role focuses on developing and optimizing integrated process flows for interconnect modules in semiconductor manufacturing. Responsibilities include coordinating with various engineering teams, optimizing RC performance, establishing process windows, identifying and reducing yield loss mechanisms, performing root cause analysis, implementing control plans, ensuring reliability margins, and supporting technology transfer from R&D to high-volume manufacturing. The role requires a PhD in a relevant engineering or science field and experience in semiconductor fabrication or characterization. | — | 0 |
| Intel Process Integration Engineer - (FE) Process Integration Engineer at Intel, focusing on developing integrated front-end process flows for new technology nodes, analyzing yield loss, and optimizing device performance. Requires a PhD in a relevant engineering or science field and experience in semiconductor fabrication or device characterization. | — | 0 |
| Infrastructure and DevOps Engineer Infrastructure and DevOps Engineer responsible for designing, deploying, and maintaining scalable infrastructure systems, building and optimizing CI/CD pipelines, and collaborating with development teams to implement technical solutions. Requires expertise in automation tools, DevOps methodologies, and Windows Server administration. | — | 0 |
| Accountant Accountant role at Intel focusing on preparing and maintaining financial records, managing audits, preparing internal and regulatory financial reports, developing finance policies, defining accounting system roadmaps, validating month-end accounts, and coordinating with statutory auditors. Requires a Bachelor's degree or Professional Degree in Accountancy, a Professional Accounting Qualification (CA/ACCA/CPA), and a minimum of 5 years of experience in a global organization. External auditor experience or knowledge of SAP S4 is preferred. | — | 0 |
| Software Development Engineer Software Development Engineer role focused on designing, developing, and testing cloud-native applications and microservices with a strong emphasis on security best practices and automated testing within a government programs context. Requires experience with Azure cloud solutions, APIs, and container technologies. | — | 0 |
| Trainee Manufacturing Technician Trainee Manufacturing Technician role at Intel Ireland supporting wafer manufacturing operations in a semiconductor environment. Responsibilities include equipment operation, maintenance, troubleshooting, and following procedures, with a focus on developing technical skills through structured training. | — | 0 |
| Analog Post-Si Engineer Executes functional validation and performance characterization for on-chip power delivery IP, identifies and resolves power delivery issues, and partners with cross-functional engineering teams to drive design optimization. | — | 0 |
| Source To Pay Solutions - Senior Lead This role is for a Senior Lead in Source To Pay Solutions, focusing on Supply Chain IT systems, SAP procurement modules, and end-to-end business process design. The candidate will lead FIT/GAP analysis, design and implement solutions in SAP MM and Inventory Management, and support SAP Ariba modules. Experience with SAP ECC/S4, Ariba, EDI standards, and procurement processes is required. Knowledge of newer SAP technologies like BTP, SAP Core AI, SAP Build, Agentic, CAP, and Fiori/UI5 is preferred. | — | 0 |
| Sr. Infrastructure Engineer – Windows OS Sr. Infrastructure Engineer - Windows OS role focused on deploying, configuring, and managing Windows Server OS and layered applications for Intel's Foundry Automation group, with an emphasis on automation and security within a government programs context. | — | 0 |
| Sr. Infrastructure Engineer – Storage This role focuses on the infrastructure and storage engineering for government programs within Intel's Foundry Automation group. The engineer will be responsible for developing, optimizing, and integrating advanced storage technologies (object, file, block, SDS) across various service models (bare metal, IaaS, PaaS). Key responsibilities include planning, managing, and optimizing storage and backup solutions, designing scalable infrastructure, ensuring data protection and regulatory compliance, and troubleshooting storage issues. The role requires in-depth knowledge of SAN, NAS, SDS, and object storage, enterprise backup solutions, and automation tools like Ansible and Python. A strong understanding of general system administration and solutions architecture is also necessary. | — | 0 |
| Sr. Infrastructure Engineer – Virtualization and Cloud Platforms This role focuses on engineering, deploying, and managing on-prem cloud infrastructure and virtualization environments (VMware), with a strong emphasis on CI/CD, infrastructure-as-code, and adherence to NIST security standards. It involves collaboration with cross-functional teams and advanced troubleshooting within these environments. The role requires experience with government programs and the ability to obtain security clearance. | — | 0 |
| Middleware Development Engineer Develops the offloading runtime (liboffload) for heterogeneous compute (GPUs and CPUs) within the LLVM ecosystem, bridging languages like SYCL and OpenMP to driver-level backends. Responsibilities include API design, backend implementation, upstream LLVM contributions, and community engagement. | — | 0 |
| Silicon Packaging Design Engineer This role focuses on the physical layout design of Intel's silicon for packaging technology, involving optimization for performance, reliability, and manufacturability. It requires developing custom layouts, performing detailed planning and routing, verifying standard cell libraries, and executing layout verification processes. The engineer will use EDA tools, troubleshoot design issues, and collaborate with cross-functional teams to ensure seamless execution of silicon tape-in, driving innovative layout methodologies. | — | 0 |
| Design Verification Eng Graduate Intern This is an internship role for a Design Verification Engineer focused on verifying the functional logic of silicon designs, ensuring alignment with architecture specifications. Responsibilities include developing verification plans, test benches, and environments, performing emulation and simulation, and debugging design issues. The role requires proficiency in SystemVerilog/Verilog and understanding of verification methodologies like OVM/UVM. | — | 0 |
| Module Development Engineer - CMP Chemical Mechanical Planarization (CMP) Process Development Engineer in Logic Technology Development (LTD) organization, responsible for developing and sustaining planarization techniques for semiconductor manufacturing. This role involves process integration, equipment solutions, feasibility studies, and roadmap development for innovative device architectures. Requires collaboration with suppliers and staying updated on industry trends. | — | 0 |
| GPU Software Development Engineer GPU Software Development Engineer focused on validation and debug of graphics IP, integrating features, triaging failures, and developing debug tools. The role involves scaling across display, media, 3D, compute, and power conservation components, and enabling features for AI domains to improve performance on graphics products. Requires strong analytical and problem-solving skills, with experience in C, C++, Python, and graphics/GPU hardware/software. | — | 0 |
| Senior CPU Power Delivery Engineer Senior CPU Power Delivery Engineer role at Intel, focusing on the design, verification, and integration of power delivery networks for next-generation CPUs. Requires expertise in VLSI, physical design, and power delivery analysis tools. | — | 0 |
| Network Systems and Solutions Engineer This role focuses on providing technical support and engineering solutions for Intel's programmable Infrastructure Processing Units (IPUs) to customers, involving hardware and software integration, system bring-up, driver configuration, and use case testing. The engineer will also develop technical collateral, evaluate tools, and analyze customer feedback to drive product improvements. | — | 0 |
| CPU Formal Verification Engineer Intel is seeking a Formal Verification Engineer to ensure the reliability and functionality of their IP and SoC microarchitectures. This role involves using advanced formal verification tools and methodologies, developing test and coverage plans, creating abstraction models, and developing formal proofs. The engineer will collaborate with architects, RTL developers, and physical design teams, and maintain the verification infrastructure. | — | 0 |