Intel

Lead formal verification efforts for complex CPU designs (i9, i7, i5, Xeon processors). Develop environments, create models and properties, analyze failures, and guide team members. Stay updated on formal verification technologies and develop new methodologies.

Semiconductor Manufacturing Engineer responsible for operational support, process optimization, and new product introduction in a fabrication facility. This role involves analyzing factory metrics, developing manufacturing plans, and collaborating with engineering and automation teams to ensure efficient production and delivery schedules.

Process and Equipment Engineer at Intel in Malaysia, responsible for optimizing high-volume manufacturing equipment and processes for integrated circuit production. This role involves ensuring precision, quality, cost efficiency, and technology scaling, with opportunities for global process transfer and continuous improvement.

Process and Equipment Engineer at Intel in Malaysia, focusing on optimizing high-volume manufacturing equipment and processes for integrated circuits. Responsibilities include testing, defect minimization, implementing process modifications, building capacity, executing maintenance, developing excursion prevention systems, managing equipment installation, and collaborating with cross-functional teams for technology transfer.

Industrial Engineer specializing in automation for semiconductor manufacturing, focusing on designing and implementing solutions to enhance operational efficiency. The role involves programming (Python), data management (SQL, NoSQL), data analysis, process optimization, and utilizing visualization tools.

Designs, develops, and executes power and performance plans for IPs and SoCs. Identifies, builds, and maintains power, thermal, performance/watt optimizations, and characterizations for IPSoC power and performance goals. Conducts feature analysis from power and performance standpoint and drives to close any gaps between observed behavior and target on platforms in development. Provides recommendations for future architectures. Develops and enhances innovative tools for architectural performance analysis. Develops methodologies and models to drive continuous improvements in optimization of power and performance configurations to meet market requirements. Ensures platform and its components are optimized for performance and power balance. Identifies power activity zones and works with design, architecture, binning/technology, and manufacturing teams on ways to meet power consumption goals. Works cross functionally on analysis, validation, and tuning of architectures and features that advance the state of art in performance and efficiency.

Senior CPU Physical Design Engineer responsible for the design and delivery of high-performance CPU blocks from RTL to GDS, including synthesis, floorplanning, place and route, CTS, timing closure, and verification. Requires 10+ years of experience with industry-standard EDA tools.

This role is for a CPU Physical Design Engineer at Intel, focusing on the design and delivery of high-performance CPU blocks from RTL to GDS. Responsibilities include executing the full physical design flow, leading verification and sign-off, and optimizing designs for power, performance, and area using industry-standard EDA tools. The role requires a BSc or MSc degree in Electrical or Computer Engineering and at least 7 years of experience in physical design.

Senior/Staff VLSI Verification Engineer with 11-15 years of experience in complex SoC/ASIC verification, focusing on UVM/System Verilog testbench architecture, Mix signal IP verification strategy, and post-silicon debug. Responsibilities include defining verification plans, mentoring junior engineers, ensuring coverage closure, and collaborating with architects. Experience with formal verification methods is also required.

Lead a team responsible for pre-Silicon functional verification of Intel's latest CPUs, developing test plans, simulation models, and test benches to ensure design requirements are met. Focus on driving strategic tool/flow/methodology initiatives to reduce validation cycle time and ensure first-pass silicon success. Requires technical leadership and managerial experience in pre-Silicon verification environments.

Director of Analog Design & Infrastructure Design Automation to lead the development, deployment, and governance of analog/mixed-signal design environments and CAD infrastructure. This role owns EDA tool ecosystems, PDK integration, compute infrastructure, design data governance, and tapeout manifest management to ensure high productivity, reproducibility, and audit readiness across silicon programs.

The GPU Validation Engineer role at Intel focuses on the pre-silicon validation of GPUs, including their interaction with media, display, and system-level features. The role involves defining, developing, and performing functional validation, applying various tools and techniques to meet performance, power, and area goals. Responsibilities include reviewing design changes, developing validation methodologies, executing validation plans, debugging pre-silicon issues, influencing validation infrastructure, publishing reports, and collaborating with architecture, design, verification, and platform teams.

Senior CPU Verification Engineer responsible for ensuring the functional correctness of CPU logic designs through pre-silicon verification methodologies, including developing UVM-based testbenches, running simulations, debugging issues, and collaborating with architects and designers.

Practical Engineering student role in a semiconductor manufacturing facility, focusing on operating and supporting advanced equipment, learning maintenance, and assisting engineering teams with troubleshooting and process improvement. Requires enrollment in a Mechanical or Mechatronics Practical Engineering program with at least three semesters remaining.

System Validation Engineer at Intel responsible for defining, developing, and performing functional validation for Thunderbolt technology. This involves engaging from early product stages to define HW/FW hooks, developing methodologies and test plans, executing plans, and collaborating with engineers for design optimization, troubleshooting, and failure analysis. The role requires FPGA and Silicon debug, understanding the full stack (HW/FW, driver, OS), and applying various tools and techniques to ensure validation coverage. The engineer will publish validation reports, work with cross-functional teams (architecture, design, verification, etc.) to improve debug and validation strategies, and develop content for IP interactions. The role also involves engaging in all product life cycle phases, developing and validating content and infrastructure, and performing bug hunts in simulation, emulation, and FPGAs to ensure silicon readiness.

This role focuses on the pre-silicon validation of CPU logic, developing verification plans, test benches, and simulation models to ensure design specifications are met. It involves debugging, root-causing issues, and collaborating with architects and developers to improve verification of complex features. The position requires a Bachelor's degree in Electrical/Electronics or Computer Engineering with knowledge of computer system architecture and digital logic design.

Intel is seeking an experienced MSVC Compiler Engineer to work on core compiler backend components, drive performance improvements, and collaborate with hardware architecture teams for Intel platforms. Responsibilities include designing, implementing, and maintaining compiler backend optimizers and code generation, developing optimization techniques, and collaborating with hardware architects. The role also involves testing, validation, performance bottleneck analysis, staying current with compiler research, and mentoring junior engineers.

Intel Foundry Services is seeking an IP Enablement Application Engineer to provide technical support to customers on IP integration challenges. This role involves working with design teams and customers throughout the IP development lifecycle, resolving issues, and providing hands-on debug. Responsibilities include customer support, cross-functional collaboration, developing integration methodologies, and creating training materials. The role requires strong problem-solving skills and experience in SOC IP Integration, RTL design, and ASIC/SoC development.

Senior Analog/Mixed Signal Application Engineer at Intel Foundry Services, providing technical support to customers on PDKs, design methodologies, and implementation flows for semiconductor manufacturing, focusing on successful customer tape-outs and quality improvements in design kits and documentation.

DFT Application Engineer providing technical support to Intel Foundry Services customers on PDKs, DFT/DFM insertion, and ATPG validation methodologies for Aerospace, Defense, and Government (ADG) customers. The role involves customer technical support, driving quality improvements in DFT/DFM and ATPG validation methodology, and developing technical content and training.

Software developer for Linux Wifi team at Intel, contributing to open-source code for Intel's wifi devices on Linux. Role involves working on the Linux kernel in C, focusing on networking, PCI, and the wifi stack.

This role focuses on ensuring the functional correctness of complex digital designs for AI SoCs using formal methods. The engineer will own the formal verification strategy, develop environments, write properties, collaborate with design teams, and contribute to pre-silicon verification and post-silicon debug. The role also involves defining verification plans, executing them using simulation and emulation, debugging issues, and incorporating security verification activities.

Senior Photonic-Integrated-Circuit Engineer at Intel, responsible for the end-to-end development of silicon photonic integrated circuits, from concept and design to high-volume manufacturing. This includes system-level planning, component design and optimization, simulation, layout, testing, validation, and performance debug, working cross-functionally with various teams and foundries. Requires expertise in PIC design, simulation tools (Lumerical, RSoft, Matlab, Python), and layout tools (Cadence, KLayout).

This role is a Facilities Mechanical Project Coordinator responsible for supporting project management activities, ensuring smooth project execution, and leading engineering teams on mechanical, electrical, and chemical systems for specific facilities. The role involves planning, organizing, coordinating activities, maintaining documentation, tracking milestones, and preparing reports. Qualifications include project coordination experience, technical skills in CAD and project management tools, and experience with mechanical systems in facilities.

Senior Device Engineer role at Intel, focusing on developing and customizing CMOS device technology for foundry customers. Responsibilities include collaborating with development and manufacturing teams, owning NPI, performing device optimizations, and utilizing data analysis for learning. Requires strong CMOS device physics knowledge and experience in advanced transistor architectures, preferably in a foundry environment.

Intel is seeking an experienced RTL/Logic Design Engineer to develop and maintain RTL designs using Verilog/System Verilog for FPGA and ASIC solutions. The role involves functional simulation, verification, debugging, and collaboration with cross-functional teams to ensure design quality and meet specifications. Experience with packet-based protocols and agentic AI is considered an advantage.

This role focuses on formal verification of microarchitecture using industry-standard tools and algorithms for server, client, and graphics IPs. The engineer will define verification scope, deploy strategies, create abstraction models, and ensure design correctness and quality on schedule. Experience with RTL languages, assertion languages, and formal verification principles is required.

Seeking a Senior Design Engineer with 10+ years of experience in Block Level design and 3+ years in Cache systems to join the AI industry's Habana group at Intel. Responsibilities include designing and implementing IP solutions, collaborating with cross-functional teams, and ensuring the quality and performance of IP designs. Requires B.Sc. in Electrical Engineering or Computer Engineering and strong RTL skills in System Verilog.

Senior Pre-Silicon Verification Engineer specializing in mixed-signal verification for semiconductor designs. Responsibilities include developing verification strategies, creating behavioral models, executing verification plans, and debugging pre-silicon environments.

Senior CPU Pre-Silicon Verification Engineer responsible for ensuring the functional correctness and robustness of CPU logic designs through pre-silicon verification methodologies. This involves developing and maintaining verification environments, test plans, coverage models, and debugging RTL and testbench failures. The role requires close collaboration with microarchitecture, design, and post-silicon teams to deliver high-performance, power-efficient, and reliable CPU IP.

Principal Engineer role focused on the architecture, design, and integration of SoC-wide clocking networks. Responsibilities include defining PPA trade-offs, collaborating with cross-functional teams, owning the technical roadmap, mentoring junior designers, and ensuring robust silicon correlation and yield. Requires extensive hands-on experience in SoC clocking, custom analog/digital circuit design, and timing architecture.

Senior Physical Design Technical Lead at Intel, responsible for leading and driving backend implementation of advanced wireless products. This role involves defining and improving design implementation flows, automation, and signoff methodologies, optimizing PPA metrics, and collaborating with other design teams. Requires extensive experience in VLSI physical design, proficiency in Synopsys tools, and scripting skills.

Lead Structural Design / physical design Implementation of Custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff, including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools. Optimizes design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.

Senior Design Engineer for Intel Chassis Group, focusing on logic design of component IPs for SoC chassis. Responsibilities include designing protocol conversion bridges, debug/trace components, and clock/power controls, translating standard protocols to custom transport protocols while managing QoS, Access Control, Flow Control, RAS, and Error Handling.

Lead Analog SerDes Architect/Design Engineer at Intel, focusing on high-speed connectivity for data centers. Responsibilities include defining circuit architecture, leading block level development, designing mixed-signal integrated circuits, and guiding junior engineers and test plan development.

Module Equipment Technician responsible for troubleshooting, repair, and preventive maintenance of assembly and test equipment in a semiconductor manufacturing plant. This role involves monitoring equipment performance, collaborating with engineering teams on experiments and upgrades, and ensuring production efficiency and quality.

Manufacturing Operator responsible for equipment maintenance, process optimization, and adhering to safety and quality standards in a manufacturing environment.