Intel

Experienced Post Silicon Validation Engineer needed to join Intel's CPU CORE Validation team. Responsibilities include validating product features, debugging functional bugs, and working with architecture and design teams. Requires BSC/MSC in Electrical Engineering, Computer Engineering, Software Engineering, or Computer Science with 2-7 years of expertise in Post Silicon chip functional validation. Python and Assembly programming skills are advantageous.

This role focuses on enabling Intel software products by providing debugging support, contributing to solution development, and performing testing and validation. It requires programming skills in Python, C, C++, and JavaScript.

Software developer for Linux Wifi team at Intel, contributing to open-source code for Intel's wifi devices on Linux. Role involves working on the Linux kernel in C, focusing on networking, PCI, and the wifi stack.

This role focuses on ensuring the functional correctness of complex digital designs for AI SoCs using formal methods. The engineer will own the formal verification strategy, develop environments, write properties, collaborate with design teams, and contribute to pre-silicon verification and post-silicon debug. The role also involves defining verification plans, executing them using simulation and emulation, debugging issues, and incorporating security verification activities.

Senior Photonic-Integrated-Circuit Engineer at Intel, responsible for the end-to-end development of silicon photonic integrated circuits, from concept and design to high-volume manufacturing. This includes system-level planning, component design and optimization, simulation, layout, testing, validation, and performance debug, working cross-functionally with various teams and foundries. Requires expertise in PIC design, simulation tools (Lumerical, RSoft, Matlab, Python), and layout tools (Cadence, KLayout).

Intel is hiring an Atom CPU Layout Design Engineer in Guadalajara, Mexico. The role involves the physical implementation of memory compilers, custom IP blocks, and layout partitions for future-generation Intel Atom microprocessors. Responsibilities include ensuring best-in-class layout methodologies, performing complex physical design assignments, interpreting schematics, contributing to the full design flow, and partnering with SoC teams. The ideal candidate will have 2+ years of layout design experience and strong analytical skills. A Master's degree and experience with VLSI/CMOS logic circuit design are preferred.

This role is for a TFM and PPA Physical Design Engineer in the CPU team at Intel, focusing on developing and automating backend physical design flows for high-performance CPUs. Responsibilities include synthesis, place-and-route, floor planning, timing analysis, power consumption estimation, and working with EDA vendors to enhance tool capabilities. Requires a Master's degree with 6+ years of experience or a Bachelor's degree with 8+ years of experience, with expertise in physical design tools and scripting.

Memory Debug Engineer at Intel, focusing on enabling, validating, and debugging memory subsystems for next-generation Intel IA-based platforms. Responsibilities include strategic oversight of memory IO interfaces, ensuring electrical performance and stability, leading complex issue resolution, and optimizing Memory Reference Code (MRC). Requires BS/MS/PhD in EE/CE with 4+ years of experience in DDR/LPDDR protocols and debug tools like oscilloscopes and logic analyzers.

Intel is seeking a Platform Power and Performance Architect to influence and drive technical direction across Intel and industry for client platforms. Responsibilities include developing test plans for deep learning models, defining and conducting power/performance experiments, analyzing workloads using tracing techniques, developing tools for analysis, and researching power optimization technologies. The role requires a Bachelor's or Master's degree in a related field with significant experience in computing system architecture, processor architecture, power management, or thermal management.

This role focuses on enabling next-generation high-speed I/O technologies by leading PHY and SerDes IP validation and integration for future platforms. Responsibilities include pre-silicon validation of PHY IPs for standards like PCIe Gen7 and Ethernet 1.6T, evaluating internal and third-party IPs, defining IP requirements, developing integration guidelines, and debugging test chips. Requires a Bachelor's degree in Electrical Engineering with 3+ years of experience in electrical validation and debugging, and a solid understanding of SerDes architectures.

This role focuses on integrating new products into Intel's manufacturing processes, managing technology transfers, improving quality and yield, and ensuring readiness for high-volume production. It involves data analysis, problem-solving, and cross-functional collaboration.

Internship role supporting SoC (System on Chip) development activities, focusing on learning about functionality, performance, and quality validation of integrated SoCs. Responsibilities include assisting in developing and executing Pre-Silicon validation plans and supporting Post-Silicon validation activities under supervision.

Senior DFT Design Engineer focused on post-Silicon product design enabling and optimization for client products. Responsibilities include resolving product quality and performance issues using design and manufacturing problem-solving expertise.

This role is a Facilities Mechanical Project Coordinator responsible for supporting project management activities, ensuring smooth project execution, and leading engineering teams on mechanical, electrical, and chemical systems for specific facilities. The role involves planning, organizing, coordinating activities, maintaining documentation, tracking milestones, and preparing reports. Qualifications include project coordination experience, technical skills in CAD and project management tools, and experience with mechanical systems in facilities.

Senior Device Engineer role at Intel, focusing on developing and customizing CMOS device technology for foundry customers. Responsibilities include collaborating with development and manufacturing teams, owning NPI, performing device optimizations, and utilizing data analysis for learning. Requires strong CMOS device physics knowledge and experience in advanced transistor architectures, preferably in a foundry environment.

This role is for a GPU Physical Design Engineer Lead at Intel, focusing on ASIC design for graphics and AI SoCs. Responsibilities include floor-planning, clocking, synthesis, GDS, static timing analysis, formal verification, and EM/IR/PDN verification. The candidate will lead a small team and interact with architecture and design teams to improve IP and product quality. Requires a Bachelor's or Master's in Electrical/Computer Engineering with significant relevant experience in VLSI/ASIC design flows.

This role is for a Director of Foundry Business Development at Intel, focusing on sales and customer engagement within the semiconductor industry, particularly for the AI era. The responsibilities include developing sales plans, building relationships, negotiating deals, and managing customer forecasts. While the company operates in the AI era and the role supports semiconductor manufacturing for AI, the core function is sales and business development, not direct AI/ML development.

Intel is seeking an experienced RTL/Logic Design Engineer to develop and maintain RTL designs using Verilog/System Verilog for FPGA and ASIC solutions. The role involves functional simulation, verification, debugging, and collaboration with cross-functional teams to ensure design quality and meet specifications. Experience with packet-based protocols and agentic AI is considered an advantage.

This role focuses on formal verification of microarchitecture using industry-standard tools and algorithms for server, client, and graphics IPs. The engineer will define verification scope, deploy strategies, create abstraction models, and ensure design correctness and quality on schedule. Experience with RTL languages, assertion languages, and formal verification principles is required.

Seeking a Senior Design Engineer with 10+ years of experience in Block Level design and 3+ years in Cache systems to join the AI industry's Habana group at Intel. Responsibilities include designing and implementing IP solutions, collaborating with cross-functional teams, and ensuring the quality and performance of IP designs. Requires B.Sc. in Electrical Engineering or Computer Engineering and strong RTL skills in System Verilog.

Senior Staff Analog Design Engineer focused on high-speed SerDes applications (112G and 224G) for data centers, AI infrastructure, and communication networks. Responsibilities include designing analog blocks, collaborating with cross-functional teams, leading validation and optimization, and mentoring junior engineers. Requires Master's degree, 5+ years of analog/mixed-signal design experience, and expertise in specific analog domains and simulation tools. Preferred qualifications include a Ph.D., more experience, and knowledge of next-gen standards and system-level modeling.

Senior Pre-Silicon Verification Engineer specializing in mixed-signal verification for semiconductor designs. Responsibilities include developing verification strategies, creating behavioral models, executing verification plans, and debugging pre-silicon environments.

Senior CPU Pre-Silicon Verification Engineer responsible for ensuring the functional correctness and robustness of CPU logic designs through pre-silicon verification methodologies. This involves developing and maintaining verification environments, test plans, coverage models, and debugging RTL and testbench failures. The role requires close collaboration with microarchitecture, design, and post-silicon teams to deliver high-performance, power-efficient, and reliable CPU IP.

Principal Engineer role focused on the architecture, design, and integration of SoC-wide clocking networks. Responsibilities include defining PPA trade-offs, collaborating with cross-functional teams, owning the technical roadmap, mentoring junior designers, and ensuring robust silicon correlation and yield. Requires extensive hands-on experience in SoC clocking, custom analog/digital circuit design, and timing architecture.

Senior Physical Design Technical Lead at Intel, responsible for leading and driving backend implementation of advanced wireless products. This role involves defining and improving design implementation flows, automation, and signoff methodologies, optimizing PPA metrics, and collaborating with other design teams. Requires extensive experience in VLSI physical design, proficiency in Synopsys tools, and scripting skills.

This role is for a Sr. Infrastructure Engineer focused on server hardware management, lifecycle management, and operating systems (Linux and Windows) within a data center environment. The engineer will be responsible for deployment, configuration, troubleshooting, and maintenance of servers, storage, and operating systems, with a focus on government programs and ensuring system stability, performance, and security. Experience with automation scripting (Bash, Python, PowerShell) and tools like iLO and BMC is required.

Lead Structural Design / physical design Implementation of Custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff, including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools. Optimizes design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.

Senior Design Engineer for Intel Chassis Group, focusing on logic design of component IPs for SoC chassis. Responsibilities include designing protocol conversion bridges, debug/trace components, and clock/power controls, translating standard protocols to custom transport protocols while managing QoS, Access Control, Flow Control, RAS, and Error Handling.

Intel is seeking an Identity Engineer experienced with SailPoint IdentityIQ for its Information Security organization supporting Intel Federal projects. The role involves installing, securing, upgrading, and patching SailPoint IdentityIQ, developing and configuring its modules, integrating with Active Directory, designing custom forms and workflows, automating processes with PowerShell, and maintaining Windows servers and SQL Server databases. The engineer will also consult on role and entitlement models, coordinate security assessments, and assist with architecting identity security products in secured enclaves.

Lead Analog SerDes Architect/Design Engineer at Intel, focusing on high-speed connectivity for data centers. Responsibilities include defining circuit architecture, leading block level development, designing mixed-signal integrated circuits, and guiding junior engineers and test plan development.

Equipment Engineer role focused on managing, optimizing, and maintaining test and assembly equipment in a high-volume manufacturing (semiconductor) environment. Responsibilities include ensuring equipment functionality, developing processes, providing technical support, integrating new technologies, and collaborating with teams to improve metrics like OEE, MTBA, and MTTR. Experience with data analysis tools like SQL, Python, R is preferred.

Develop logic design, RTL coding, simulation, and DFT timing closure support. Define and implement SoC main debug Fabrics (TAP and Scan). Develop automatic tools to improve design and integration. Work with Architecture, Silicon, and Manufacturing teams to define new features and improve DFT capabilities (Power, Performance, Test Time, coverage). Define validation activities and work with validation owners to increase coverage and design quality. Define IPs DFT requirements to meet SoC quality, support IPs integration and validation. Develop HVM ready content, enable it on Pre Si ENV and real Silicon. Drive Coverage improvement, DPM reduction and faster Content enabling on Silicon.

Module Equipment Technician responsible for troubleshooting, repair, and preventive maintenance of assembly and test equipment in a semiconductor manufacturing plant. This role involves monitoring equipment performance, collaborating with engineering teams on experiments and upgrades, and ensuring production efficiency and quality.

Manufacturing Operator responsible for equipment maintenance, process optimization, and adhering to safety and quality standards in a manufacturing environment.