This role focuses on developing, executing, and automating Bluetooth and Wi-Fi connectivity tests for hardware and software products. It involves creating validation environments, identifying and reporting issues, developing test plans, and collaborating with cross-functional teams. The role requires experience with test automation (Python) and network protocol analyzers, with a mention of integrating Gen AI Agents into validation tasks.

Performs functional verification of CPU logic, develops IP verification plans, test benches, and verification environments. Executes verification plans, runs system simulation models, analyzes power and timing, and debugs issues. Collaborates with architects, RTL developers, and physical design teams. Maintains verification infrastructure and methodology. Participates in defining CPU architecture and microarchitecture features.

This role focuses on developing, executing, and automating Bluetooth and Wi-Fi connectivity tests for hardware and software products. It involves creating validation environments, identifying and reporting issues, developing test plans, and collaborating with cross-functional teams. The role requires experience with test automation (Python) and network protocol analyzers, with a mention of integrating Gen AI Agents into validation tasks.

Physical Design Engineer responsible for delivering end-to-end Physical Design and Analog Layout for Intel's Hard-IP portfolios, supporting implementation from RTL/Netlist through GDSII. The role involves synthesis, place and route, clock tree synthesis, static timing analysis, and power/clock distribution, as well as verification and signoff.

Physical Design Engineer responsible for end-to-end Physical Design and Analog Layout for Intel's Client, Server and ASIC Hard-IP portfolios, as well as advanced testchips. The role involves execution from RTL/Netlist through GDSII using established Physical Design methodologies and sign-off practices, impacting product-level parameters such as power, frequency, and area.

This role focuses on developing, executing, and automating Bluetooth and Wi-Fi connectivity tests for hardware and software products. It involves creating validation environments, identifying and reporting issues, developing test plans, and collaborating with cross-functional teams. The role requires experience with test automation (Python) and network protocol analyzers, with a mention of integrating Gen AI Agents into validation tasks.

This role focuses on Supply Chain IT Systems and Tools, requiring expertise in Sourcing, Procurement, EDI, B2B protocols, and SAP MM/IM. The analyst will identify business requirements, configure systems, perform testing, analyze business procedures, design new systems, troubleshoot issues, and manage projects. Experience with Agile and SaFE methodologies is also needed.

This role involves designing, developing, and implementing analog circuits for advanced process nodes, optimizing circuit floorplans, simulating analog behavior models, and developing/executing test plans to ensure designs meet specifications. The engineer will evaluate test results, verify circuit functionality, and collaborate with cross-functional teams to resolve design challenges. Research into industry trends and innovations in analog and mixed-signal design is also a key responsibility.

This role focuses on the design, development, and optimization of analog circuits for advanced process nodes within Intel's Central Engineering Group. The engineer will work on analog and mixed-signal IPs, create floorplans, simulate behavior models, develop and execute test plans, analyze test results, and optimize circuits for performance, power, area, and leakage. Collaboration with cross-functional teams and staying informed on emerging trends in analog circuit design are also key aspects of the role. The position requires a Bachelor's or BS degree in Electrical Engineering with 0-1+ years of experience, or a Master's degree with 0 years of experience, and proficiency in circuit simulation tools and analog circuit design principles.

This role focuses on the design, development, and verification of analog and mixed-signal integrated circuits (IPs) for advanced process nodes at Intel. The engineer will be responsible for circuit design, simulation, test plan development, result analysis, and optimization to meet power, performance, area, and yield goals, collaborating with cross-functional teams.

This role focuses on the performance verification of graphics logic components (3D graphics, media, and display) within Intel's Data Center Group. The engineer will define and develop verification plans, test benches, and simulation models, debug issues in a presilicon environment, and collaborate with cross-functional teams to ensure design specifications are met. Experience with GPU/CPU subsystems, UVM, and graphics pipelines is required.

Develops and integrates software across the Linux stack, including drivers, OS, frameworks, and applications, with a focus on Bluetooth SW and tools. Requires experience in C/C++, embedded systems, Linux kernel, RTOS, and Linux device drivers.

Designs and Validates Power delivery solutions for Reference/Validation boards, including low voltage DC-DC regulators and power management circuits for CPU/SOC based platforms. Involves schematics capture, PCB layout review, component selection, BOM release, and lab validation.

Intel is seeking an experienced Platform Integration Engineer for the Intel Chassis Group. The role involves understanding SoC chassis requirements, designing and developing high-performance networks-on-chip using chassis foundation library components, and coordinating with the foundation IP development team. Requires 6+ years of experience in SOC and/or IP design, with preferred experience in microarchitecture, design IP systems, and fabric design/integration.

Senior Mixed Signal Validation and Debug Engineer responsible for developing leadership IPs for Server, Client, Networking SOCs and Intel Foundry Customers. The role involves pre-silicon to post-silicon IP characterization, test plan generation using AI driven tools and Python scripting, SOC board design reviews, Signal and Power Integrity simulations, and hands-on debug of IP related issues. Requires BS/MS/PhD in EE/CE and 6+ years of experience in post-silicon validation and debug of serial or parallel IOs, with proficiency in lab hardware and software.

PCB Layout Engineer responsible for the design, placement, and routing of CPU/FPGA based hardware boards, ensuring adherence to design guidelines and product specifications. Involves collaboration with mechanical teams and understanding architecture requirements.

Develops and validates software for Intel GPUs, including firmware, drivers, and APIs, optimizing performance for graphics and compute workloads, with applications in AI and data centers.

Intel is seeking an IP Logic Design Engineer to develop logic designs for high-performance IPs integrated into SoC products for Client, Graphics, and Data Center markets. Responsibilities include RTL implementation, architecture specification, optimization, verification support, and post-silicon validation.

Senior SoC Architect role focused on defining and driving architecture specifications for Unified Intel Chassis (UIC) IP components and subsystems. Responsibilities include power optimization, scalability, platform performance analysis, and collaboration with cross-functional teams. The role requires expertise in SoC IP architecture, AMBA protocols, and architecture specification writing. Familiarity with AI tools for developing machine-readable specifications is mentioned as a plus.

This role focuses on the functional logic verification of integrated SoCs, ensuring they meet specifications. Responsibilities include developing verification plans, test benches, and environments, executing these plans using emulation and simulation, debugging issues, and collaborating with design and architecture teams. The role also involves leveraging post-silicon learnings to improve future products.

This role focuses on developing, executing, and automating Bluetooth and Wi-Fi connectivity tests for hardware and software products. It involves creating validation environments, identifying and reporting issues, developing test plans, and collaborating with cross-functional teams. The role requires experience with test automation (Python) and network protocol analyzers, with a mention of integrating Gen AI Agents into validation tasks.

Senior Design Verification Engineer for Intel's Silicon Chassis team, responsible for owning verification of interconnect and chassis IP blocks. Requires expertise in verification planning, environment development, collaboration with cross-functional teams, and debugging. Experience with AI-assisted development tools is mentioned as part of the daily workflow.

Intel is seeking an IP Development Engineer with a Master's Degree in Electronics/VLSI/Computer Engineering. The role involves translating digital design concepts into RTL using System Verilog, developing microarchitectural specifications, coding RTL, running design tools, creating timing collateral, and supporting IP usage. Experience with functional bus protocols and JTAG is beneficial. Interest in automation using PERL/Python is a plus.

Mixed Signal Design Verification Engineer responsible for ensuring the quality and functionality of mixed signal components like PCIE, UCIE, and USB4/Type-C PHYs using methodologies like System Verilog, UVM, and Verilog. The role involves developing verification plans, test benches, simulation models, and conducting root cause analysis. Scripting skills in Python, Perl, or Tcl are required, along with familiarity with standard protocols and EDA tools.

This role focuses on designing and developing power delivery solutions for Intel's platforms, ensuring optimal energy efficiency and performance. Responsibilities include defining, analyzing, and implementing power delivery networks, designing power conversion and management solutions, and collaborating with architects. The role requires expertise in power delivery modeling, PCB design tools, and debugging power systems.

Senior Physical Design Engineer at Intel responsible for the physical design of custom IP and SoC designs, impacting products in Client, Data Center, AI, and Automotive sectors. The role involves the full RTL to GDS flow, optimizing power, performance, and area, and technical leadership for SoC/Subsystem implementation.

Intel is seeking a SOC Design Verification Engineer in Bangalore, India, to ensure the functionality, quality, and security of cutting-edge System-on-Chip (SoC) designs. Responsibilities include developing verification plans, test benches, and environments; executing verification plans using emulation and simulation; debugging presilicon issues; collaborating with cross-functional teams; and enhancing verification infrastructure. The role requires proficiency in System Verilog, OVM/UVM, and SoC test environment development, along with strong hardware design knowledge.

Analog Circuit Design Engineer role at Intel, focusing on designing, developing, and optimizing high-performance analog circuits for advanced process nodes. Responsibilities include circuit design, simulation, verification, and collaboration with cross-functional teams. Requires expertise in high-speed analog circuit design and proficiency in EDA tools.

Senior Physical Design Engineer specializing in Static Timing Analysis (STA) for Intel's mixed-signal IPs. Responsibilities include timing analysis, optimization, constraint generation, timing rollups, and clock network development to meet performance, power, and functionality goals for next-generation client, server, and ASIC hard-IP portfolios.

This role focuses on the architecture of CPUs, specifically on improving methodologies and infrastructure for power and performance modeling, analysis, and workload bring-up for next-generation client products. The individual will research and drive ideas to enhance SoC power and performance modeling, collaborate with design teams, and analyze bottlenecks to propose solutions.

Performs functional verification of mixed signal logic components, including analog behavioral modeling, to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to mixed signal microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with digital and analog architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Requires BS/MS with 10+ years of experience in Design verification, System Verilog and OVM/UVM. Experience in validation flow, testbench architecture, verification closure, debug, coverage, simulations, and GLS is essential. Knowledge of DDRPHY validation, DFI/DDR/LPDDR protocols, Python/Perl scripting, Formal Property Verification, and Git is preferred. Exposure to AI tools like GitHub CoPilot is a plus.

This role focuses on Static Timing Analysis (STA) for next-generation SoCs, ensuring optimal performance and efficiency. Responsibilities include performing timing analysis and optimization, generating and verifying timing constraints, resolving timing violations, conducting timing rollups, developing power-optimized clock networks, and defining methodologies for quality timing models. The role requires collaboration with various engineering teams to achieve clocking balance and power delivery optimization.

Intel's AI SoC organization is seeking an experienced SoC Subsystem Architect to lead the evaluation of architectural trade-offs, define and document micro-architecture for complex SoC IP blocks, and drive silicon bring-up and post-silicon validation for AI hardware. The role involves RTL design, integration, verification, timing constraints, and mentoring junior engineers.

This role focuses on IP Design Verification, ensuring the functional correctness and reliability of intellectual property designs. Responsibilities include developing verification plans, designing test benches, simulating designs, debugging pre-silicon issues, and collaborating with architects and RTL developers. The role requires proficiency in SystemVerilog, experience with complex protocols, and scripting languages like Python or Perl.

RTL Design Engineer for Intel Unified Chassis, focusing on protocol bridges and IP components. Responsibilities include design, implementation, verification, and collaboration with architects and senior engineers. Requires expertise in RTL coding, digital design principles, and hardware description languages like Verilog or VHDL.

This role focuses on the validation and debug of graphics IP offerings, ensuring the robustness and quality of graphics driver/application features. Responsibilities include integrating new graphics features, triaging and resolving failures, and developing debug tools to improve efficiency. The role also involves enabling new features for AI domains to enhance performance on graphics products.

Senior Software Engineer/Architect to design, build, and support internal web applications for technical documentation, publishing, and review workflows. Requires strong full stack engineering, architectural experience, and end-to-end ownership in an enterprise environment. Responsibilities include system architecture, coding standards, stakeholder partnership, and integrating tools. Experience with ML frameworks, distributed systems, and full-stack frameworks is required.

This role is for an SoC Logic Design Engineer responsible for developing logic design, RTL coding, and simulation for SoC designs, integrating IP blocks, and ensuring power, performance, area, and timing goals are met. The engineer will also perform quality checks, optimize logic, and collaborate with customers.

Develop and maintain silicon firmware (UEFI BIOS Reference code) that interfaces directly with hardware, abstracting low-level functionality for higher-level software. Responsibilities include design, implementation, code reviews, testing, validation, and debugging, with a focus on secure coding practices. Requires proficiency in C, computer architecture, and problem-solving.

This role is for an Ethernet Hardware Product Application Engineer at Intel, focusing on providing technical support for Intel's Ethernet products and technologies. Responsibilities include optimizing solutions, enabling ecosystem partners, developing design and validation tools, performing design reviews (schematic, board layout, signal integrity), creating technical collateral, and resolving customer technical issues during development, testing, and production. The role requires expertise in Ethernet architecture, interfaces, networking products, signal integrity, and analog circuit design. Familiarity with scripting languages like Python for test automation is a plus. The preferred qualifications mention an interest in learning AI/ML applications, but the core role is hardware engineering.

Seeking a Mixed Signal Logic Design Engineer to work on high-speed digital design for low power optimized IP implementations for cutting-edge DDRPHY IPs. Responsibilities include definition, design, verification, RTL implementation, automation flows, quality checks, and creating FE packages. The role requires expertise in mixed signal fundamentals, low-power design, and digital/analog design principles. Experience with hardware simulation tools, Front End design tools, and DDR protocols is essential. Familiarity with AI tools like VSCode GitHub CoPilot is a plus.

This role is for a Customer Facing Hardware Design Enabling Engineer who will support Xeon based data center and server platforms. The engineer will work directly with customers on hardware design enablement, including platform design, bring-up, debug, validation, and issue resolution. Key responsibilities include providing system-level design guidance, reviewing schematics and PCB layouts, supporting hardware bring-up and debug, and collaborating with cross-functional teams and ODMs. Signal Integrity (SI) and Power Integrity (PI) analysis for high-speed interfaces are important aspects of this role.

Develop and maintain behavioral models (BMods) for analog circuits using SystemVerilog, integrate them into digital verification environments, debug AMS simulations, and collaborate with design teams. The role involves exploring and adopting AI-based tools and workflows to enhance BMod development, simulation analysis, and reporting.

Senior SoC Logic Design Engineer responsible for designing and developing cutting-edge System-on-Chip (SoC) solutions for Intel products and Custom ASIC customers. This role involves RTL coding, simulation, IP integration, and optimization for performance, power, and area, with a focus on Server, Client, Networking, and AI applications. The engineer will also ensure design quality, security, and collaborate with cross-functional teams.

This role is for an IP and Subsystem Validation Engineering Manager at Intel, focusing on ensuring the reliability and functionality of cutting-edge IP designs. Responsibilities include developing verification plans, executing simulations, debugging issues, and collaborating with cross-functional teams. Requires a strong background in RTL design, verification methodologies, and leadership experience.

Analog Circuit Design Engineer role at Intel, focusing on designing and developing cutting-edge analog circuits for advanced process nodes. The role involves creating high-performance analog and mixed-signal IPs, optimizing circuits for various objectives, and collaborating with cross-functional teams. Requires expertise in high-speed IO circuits and analog circuit design, with a strong foundation in CMOS design principles.

Mixed Signal Design Verification Engineer responsible for ensuring the functionality and performance of mixed signal logic components using System Verilog, UVM, and Verilog, developing test plans and environments, and debugging issues in the presilicon environment.