Intel

The role involves developing Triton front-end and back-end components for Intel GPUs, focusing on creating efficient custom GPU kernels for AI workloads. Responsibilities include defining, designing, developing, testing, and maintaining software tools for domain-specific programming languages, working with hardware design teams and compiler development communities, and participating in language standards groups. The ideal candidate has experience in GPU programming for AI, C/C++/Python, compiler stages, code generation, optimization, and GitHub. Familiarity with PyTorch attention techniques for transformer models is also required.

AI Software Solution Engineer focused on validation and workload enabling for Intel platforms. The role involves optimizing AI model efficiency, accuracy, and performance by working with frameworks, algorithms, and hardware. Key responsibilities include enabling AI models on Intel GPUs, debugging deep learning models, conducting benchmarking and validation, developing automation pipelines, and evaluating AI models against competitors. The role also involves customer engagement for enablement and performance improvements, and translating AI workload needs into architecture insights.

Engineer to work on Intel's AI frameworks software stack, focusing on design, development, and optimization of features for AI accelerators and GPUs. This includes ML kernel development, enhancing training and inference capabilities, and contributing to open-source AI frameworks like PyTorch, Tensorflow, and JAX.

Senior System Debug Engineer responsible for the design and development of integrated AI solutions for deep learning and machine learning systems, focusing on hardware, software, firmware, board, and silicon components. The role involves AI systems architecture, defining product specifications, and impacting the AI product roadmap. It requires developing new methods in various AI/ML domains, leading design and implementation of component-level choices for performance and cost, defining system integration approaches, and delivering end-to-end technical solutions. The role also includes debugging and ensuring the reliability of AI infrastructure, collaborating on next-generation requirements, and influencing AI roadmap with customer knowledge.

This role focuses on designing and developing features for Intel's AI frameworks software stack, specifically optimizing inference serving frameworks (like SGLang, vLLM) and ML frameworks (PyTorch, Tensorflow, JAX) for Intel's AI accelerators and GPUs. The engineer will enhance deep learning training and inference capabilities, identify optimization opportunities, and contribute to open-source communities.

Engineer to design and develop features for Intel's AI frameworks software stack, focusing on inference serving frameworks (SGLang, vLLM) and ML frameworks (PyTorch, Tensorflow, JAX). The role involves optimizing software for Intel's AI accelerators and GPUs, enhancing training and inference capabilities, and contributing to open-source communities.

This role focuses on debugging and resolving complex system-level issues for Intel's AI GPU product roadmap, involving hardware, software, firmware, and silicon components. The engineer will lead root-cause analysis, manage the bug lifecycle, and collaborate with cross-functional teams to ensure efficient resolution of platform issues and customer escalations. While familiarity with ML frameworks and AI/ML deployment debugging is a plus, the core responsibility is system-level engineering and debugging.

Senior Director to lead Enterprise Data & AI Enablement, defining strategic roadmaps for data and AI capabilities, building robust data foundations for advanced AI applications, and overseeing data strategy, architecture, ingestion, and governance. The role focuses on enabling AI/ML initiatives by providing necessary data infrastructure and tooling.

This role focuses on electrical validation and tuning of System-on-Chip (SoC) components, specifically IO interfaces. The engineer will define validation strategies, ensure analog performance and signal integrity, conduct research in mixed-signal architectures, analyze customer returns for yield improvement, and perform root cause analysis for electrical issues. The position requires expertise in hardware validation, debug, signal delivery, and Python programming for validation tasks.

Analog Circuit Design Engineer role at Intel, focusing on designing and developing cutting-edge analog circuits for advanced process nodes. The role involves creating high-performance analog and mixed-signal IPs, optimizing circuits for various objectives, and collaborating with cross-functional teams. Requires expertise in high-speed IO circuits and analog circuit design, with a strong foundation in CMOS design principles.

This role focuses on the physical design and timing analysis of System-on-Chips (SoCs), ensuring optimal performance, power, and functionality. Responsibilities include timing analysis, constraint generation, violation fixing, clock network design, and methodology development for timing models. The role collaborates with various teams to deliver efficient chip integration and validate clock network guidelines.

Logic Design Engineer at Intel in Bangalore, India. This role involves contributing to technological advancements, solving complex problems, and collaborating with cross-functional teams. Responsibilities include applying technical skills to projects, analyzing and troubleshooting issues, conducting research, and preparing reports. Requires a Bachelor's degree in a technical field or equivalent experience, with proficiency in relevant software, tools, or systems. Preferred qualifications include a Master's degree, experience in collaborative projects, and strong communication skills.

Lead the design analysis and methodologies for memory blocks and data path subsystems in Intel's latest CPUs, focusing on high frequency (over 5GHz) and low-power digital designs.

Mixed Signal Design Verification Engineer responsible for ensuring the functionality and performance of mixed signal logic components using System Verilog, UVM, and Verilog, developing test plans and environments, and debugging issues in the presilicon environment.

Design Verification Engineer at Intel responsible for functional verification of IP logic, developing verification plans, test benches, and simulation environments. The role involves executing verification plans, debugging issues, collaborating with design teams, and maintaining verification infrastructure.

Entry Level Analog Layout Engineer to support analog and mixed signal IP development. Responsibilities include custom layout implementation and physical verification tasks for analog blocks used in SoC and IP designs.

Develops mixed signal logic design and RTL coding for high-speed IP blocks, focusing on optimizing power, performance, area, and timing. Responsibilities include static timing analysis, collaborating with SoC architects, and supporting integration into complex SoC designs.

Intel is seeking a Pre-Silicon Validation Engineer with 7+ years of experience to join their Central Engineering Group in Bangalore, India. The role involves defining and executing verification plans, developing test benches, and debugging complex SoC designs using SystemVerilog and UVM. The engineer will collaborate with cross-functional teams to ensure high-quality SoC delivery and contribute to Intel's next-generation products.

This role focuses on Pre-Silicon Validation Engineer for SoC designs at Intel. Responsibilities include defining and developing verification plans, test benches, and environments using SystemVerilog and UVM. The engineer will execute verification plans, debug issues in the presilicon environment, collaborate with cross-functional teams, and incorporate security validation. The role requires strong debugging capabilities for SoC, fabric, and memory subsystems, and knowledge of microarchitecture and computer architecture.

Intel is seeking a Silicon SoC Architect with 15+ years of experience to define and drive end-to-end SoC architecture for high-performance and low-power products. Responsibilities include defining architecture, evaluating trade-offs, conceptualizing microarchitecture, integrating IP blocks, developing test infrastructure, conducting simulations, and collaborating with cross-functional teams. Requires expertise in SoC architecture fundamentals, microarchitecture, RTL development, and system architecture integration, with a strong understanding of performance and power trade-offs.

This role is for a Pre-Silicon Validation Engineer at Intel in Bangalore, India. The engineer will apply technical skills to execute and support projects, analyze and resolve issues, and collaborate with cross-functional teams. The role requires a Bachelor's degree in a technical field and strong technical aptitude.

This role supports enterprise digital signage systems, focusing on operational support, monitoring, hardware health, procurement, and coordinating repair efforts. It also involves evaluating and piloting new technologies and solutions through POCs.

IT Support Specialist (L4) providing advanced operational and technical support for Microsoft Teams, Teams Rooms (MTR), Audio/Visual (AV), and Telephony services in a global, 24x7 enterprise environment. Responsibilities include ensuring high availability, performance, and user experience across meeting rooms, conferencing services, and voice systems. The role acts as an escalation point for complex incidents, leads problem management, and proactively maintains service health. This includes readiness validation for conference rooms, lifecycle management of MTR systems, voice infrastructure operations, and live meeting support.

IT Support Specialist serving as a technical team lead and subject matter expert for Microsoft Teams, Teams Rooms (MTR), Audio/Visual, and Telephony services. Provides Level 4 operational and escalation support in a global 24x7 environment, leading shift operations, coordinating major incidents, and ensuring service quality and SLA adherence. Acts as the primary escalation point for complex issues, mentors support specialists, and partners with engineering, network, and security teams for service stability and continuous improvement. Supports business-critical meetings and enterprise collaboration services with a focus on proactive issue prevention and operational excellence.

This role provides technical support for Intel products and technologies, focusing on solution design, development, validation, and market readiness. It involves creating technical collateral, enabling partners, and collaborating with customer R&D and manufacturing to ensure smooth product integration and ramp-up. The role requires strong C programming and UEFI/BIOS firmware development experience.

The role involves designing, developing, and maintaining firmware solutions that interface directly with hardware, including microcode, FPGA, and IP-specific firmware, for Intel's next-generation client platforms. This includes implementing abstractions of low-level hardware details and ensuring seamless integration between hardware and software layers.

Physical Design Engineer at Intel responsible for the end-to-end physical design implementation of next-generation Client SoCs, from RTL to GDS. This includes synthesis, floor planning, placement, routing, clock tree synthesis, power analysis, verification, and signoff. The role also involves performance optimization, developing and improving physical design methodologies, and automating design flows.

DFT Lead (Scan/ATPG) Engineer at Intel, responsible for driving DFT implementation for CPU designs in the latest process technology. Requires Master's or Bachelor's degree with significant experience in DFT, ATPG, fault models, memory BIST, IJTAG/TAP, RTL generation, verification, and post-silicon support.

Principal Engineer in SoC Design Verification at Intel, responsible for leading functional logic verification of integrated SoC designs, defining and developing verification plans, test benches, and environments, executing verification plans using emulation and system simulation, debugging presilicon issues, and collaborating with cross-functional teams. The role also involves mentoring technical leaders and ensuring security coverage.

Seeking a skilled SoC Security Validation Engineer with expertise in SoC architecture, OS fundamentals, CPU memory subsystems, and advanced security technologies like secure boot, trusted computing, and confidential computing. Responsibilities include leading security validation, developing threat models, designing penetration tests, validating security mechanisms, and developing automated test scripts using C, C++, and Python. Requires 7+ years of experience and strong programming skills.

Hardware Board Design Engineer with expertise in Power Delivery design and debug for Intel Core and Atom CPUs. Responsibilities include schematic capture, PCB design, power integrity simulation, board power-on and debugging, and customer technical support.

This role focuses on the functional verification of IP and subsystem logic for AI-accelerated systems within Intel's Data Center Group. The engineer will develop verification plans, test benches, and environments, execute these plans through simulation, and debug issues in the presilicon environment. Collaboration with architects, RTL developers, and physical design teams is key, as is maintaining and improving the verification infrastructure.

This role is for a System Modelling Engineer at Intel, focusing on the architecture, modeling, and performance analysis of 224Gbps SerDes IP. The engineer will develop end-to-end PHY system models, analyze electrical channels, optimize equalization algorithms, and perform clocking, jitter, and noise analysis. The role also involves supporting industry standards, defining test methodologies, and collaborating with cross-functional teams. The position requires a strong background in analog circuit design and high-speed design techniques.

Intel is seeking a Systems and Hardware Enabling Engineer to design and develop firmware for next-generation client platforms, interfacing directly with hardware components like microcode, FPGA, and IP-specific firmware. The role involves abstracting low-level hardware details, ensuring seamless integration, and optimizing performance and reliability. Responsibilities include firmware design, development, testing, validation, and collaboration with cross-functional teams, adhering to secure development lifecycle practices.

Analog Circuit Design Engineer at Intel focusing on PLLs and clocking circuits, involving design, validation, and reliability. Requires strong fundamentals in CMOS design and semiconductor device physics.

Analog Circuit Design Engineer responsible for designing and developing analog circuits in advanced process nodes for analog and mixed-signal IPs, optimizing for power, performance, area, timing, and yield. Requires experience in PLLs, clocking circuits, LC VCO/DCO design, and CMOS fundamentals.

Analog Circuit Design Engineer at Intel focusing on high-speed interconnect solutions, designing and verifying analog circuits in advanced process nodes. Responsibilities include transistor-level design, simulation, optimization, and post-silicon validation for SerDes PHY analog blocks.

Intel is seeking an Analog Circuit Design Engineer to design, simulate, and verify analog circuits for advanced process nodes, focusing on high-speed SerDes (112/224Gbps). The role involves optimizing circuits for power, performance, area, and yield, and collaborating with cross-functional teams. Experience with EDA tools and CMOS technologies is required.

Analog Circuit Design Engineer at Intel, focusing on designing, developing, and optimizing high-speed analog circuits in advanced process nodes for next-generation memory interface PHYs. Responsibilities include circuit design, simulation, optimization for power/performance/area, test plan creation, collaboration with cross-functional teams, layout reviews, and post-silicon debug.

Design, develop, and optimize high-speed SerDes circuits for Intel's next-generation technologies, collaborating with cross-functional teams and supporting silicon validation.

This role focuses on the functional validation of Accelerator IPs within Intel's Data Center Group. The engineer will define, develop, and perform validation for IP internals and their integration into system-level features, covering both pre- and post-silicon stages. Responsibilities include developing test plans, methodologies, and infrastructure, performing silicon debug, and collaborating with other engineering teams. The role requires strong programming skills in C/C++/Python for automation and experience with hardware architectures and lab equipment.

Intel is seeking an experienced Micro Architect/Senior Design Engineer to design, develop, and implement advanced Digital IO Controllers like PCIe/CXL/UCIe systems for next-generation data center and AI chips. This role requires microarchitectural expertise and hands-on RTL coding skills, with a deep understanding of high-speed IOs and interconnect protocols. Responsibilities include architecting memory coherency protocols, designing critical components of PCIe/UCIe controllers, collaborating with cross-functional teams, and staying updated on emerging technologies in AI/ML hardware.

Analog Circuit Design Engineer at Intel, responsible for designing, developing, and optimizing high-speed analog circuits in advanced process nodes. This role involves circuit design, validation, simulation, optimization for power/performance/area/timing/yield, test plan creation, cross-functional collaboration, and post-silicon debug. Requires expertise in high-speed analog circuits like TX/RX blocks, PLLs, DLLs, SerDes, and voltage regulators, with proficiency in industry-standard tools.

Analog Circuit Design Engineer at Intel responsible for designing, developing, and optimizing high-speed analog circuits in advanced process nodes, contributing to next-generation memory interface PHYs and analog/mixed-signal IPs. Involves circuit design, simulation, validation, optimization for power/performance/area, test plan creation, collaboration with cross-functional teams, layout reviews, and post-silicon debug.

Analog Circuit Design Engineer at Intel responsible for designing, developing, and optimizing high-speed analog circuits in advanced process nodes, contributing to next-generation memory interface PHYs and analog/mixed-signal IPs. Involves circuit design, simulation, validation, optimization for power/performance/area, test plan creation, collaboration with cross-functional teams, layout reviews, and post-silicon debug.

Develop, optimize, and maintain high-performance network solutions and device drivers for Intel's innovative products. Responsibilities include driver development across OS platforms, optimizing packet processing, debugging software stacks, implementing Ethernet standards, and working with virtualization technologies. Collaboration with firmware, hardware, validation teams, and OS vendors is key. The role also involves analyzing and improving OS kernel components and contributing to programming standards.

This role focuses on the functional verification of IP designs for Intel's advanced IP technologies. The engineer will develop and execute verification plans, test benches, and simulation models to ensure designs meet specifications and identify/debug issues in the presilicon environment. Collaboration with architects and RTL developers is key, as is maintaining verification infrastructure. The role requires strong coding skills in Perl or Python, proficiency in SystemVerilog and UVM/OVM, and experience with AMBA protocols.

Firmware Development Engineer at Intel, focusing on designing, developing, and maintaining embedded firmware for silicon, SoC subsystems, and controllers. Responsibilities include end-to-end feature ownership, low-level driver development, RTOS integration, pre-silicon to post-silicon debug, and collaboration with cross-functional teams. Requires strong C/C++, embedded systems fundamentals, and experience with pre-silicon workflows and debugging tools.

Intel is seeking a Compiler Engineer to design, develop, test, and enhance software tools for domain-specific programming languages like P4. The role involves collaborating with hardware design teams, optimizing code generation for ASIC network packet processing, and participating in language standards groups. Requires strong C/C++ skills, deep understanding of compiler internals, and expertise in frameworks like GCC or LLVM.

This role is for an IP Design Verification Engineer at Intel, focusing on ensuring the quality and reliability of Intel's IP designs. Responsibilities include developing and executing verification plans, creating test benches and cases, performing simulations, debugging issues, and collaborating with cross-functional teams. The role requires proficiency in System Verilog and Python, knowledge of IP validation tools and methodologies, and experience in test planning and hardware simulation.