Intel

This role is for a Defect Metrology Engineer in semiconductor manufacturing, focusing on substrate packaging technologies. The engineer will use defect inspection tools to detect and resolve process issues, collaborate with teams to improve yield, manage next-generation tool installations, develop equipment roadmaps, and work with suppliers. The role requires a degree in a relevant engineering or science field with significant experience in semiconductor manufacturing and defect metrology tool ownership.

Supports management/senior leadership to incorporate process and quality improvements in Intel's substrates strategy. Defines material inspection methodology, conducts studies related to cost control, process control, and production yield, and implements plans and programs to optimize supply chain. Supports product long range plan development by defining next generation methodology capabilities to support Intel's supply chain roadmap. Explores and benchmarks emerging technology in the industry. Contributes to Intel's future technology definition and requirements. Highlights gaps between roadmap strategy, manufacturing capability, and market demands and recommends solutions to addresses those gaps. Tracks supply demand trends, conducts root cause analysis to find opportunities for process and quality improvements, and collaborates with supply chain leads to implement solutions. Leads supplier selections for new business in partnership with commodity managers and technical/quality partners and drives product and purchase specification content to ensure commodity performance compliance. Performs alternate sourcing risk mitigation for single sourced commodities. Establishes control standards, determines KPIs, monitors performance against targets, and drives root cause analysis for supply chain issues to arrive at solutions. Drives supplier process window validation activities on critical process modules through all stages of development. Drives supplier improvements on quality, reliability, yield, and cost. Maintains quality standards and systems, creating relevant specifications to minimize variability and subjectivity to align with operational capability requirements. Leads quality excursion management and drives failure mode analysis with suppliers.

IT Support Specialist (L4) providing advanced operational and technical support for Microsoft Teams, Teams Rooms (MTR), Audio/Visual (AV), and Telephony services in a global, 24x7 enterprise environment. Responsibilities include ensuring high availability, performance, and user experience across meeting rooms, conferencing services, and voice systems. The role acts as an escalation point for complex incidents, leads problem management, and proactively maintains service health. This includes readiness validation for conference rooms, lifecycle management of MTR systems, voice infrastructure operations, and live meeting support.

IT Support Specialist serving as a technical team lead and subject matter expert for Microsoft Teams, Teams Rooms (MTR), Audio/Visual, and Telephony services. Provides Level 4 operational and escalation support in a global 24x7 environment, leading shift operations, coordinating major incidents, and ensuring service quality and SLA adherence. Acts as the primary escalation point for complex issues, mentors support specialists, and partners with engineering, network, and security teams for service stability and continuous improvement. Supports business-critical meetings and enterprise collaboration services with a focus on proactive issue prevention and operational excellence.

Security Software Validation Engineer at Intel, focusing on validating complex software-hardware security innovations for Intel CPUs using Pre-Silicon simulations and identifying/mitigating security risks. Requires strong C++/C programming and software development experience.

Student role focused on power and performance post-silicon validation of Intel's client CPU products. Responsibilities include system setup, calibration, and execution of power/performance studies in a lab environment.

This role provides technical support for Intel products and technologies, focusing on solution design, development, validation, and market readiness. It involves creating technical collateral, enabling partners, and collaborating with customer R&D and manufacturing to ensure smooth product integration and ramp-up. The role requires strong C programming and UEFI/BIOS firmware development experience.

The role involves designing, developing, and maintaining firmware solutions that interface directly with hardware, including microcode, FPGA, and IP-specific firmware, for Intel's next-generation client platforms. This includes implementing abstractions of low-level hardware details and ensuring seamless integration between hardware and software layers.

Physical Design Engineer at Intel responsible for the end-to-end physical design implementation of next-generation Client SoCs, from RTL to GDS. This includes synthesis, floor planning, placement, routing, clock tree synthesis, power analysis, verification, and signoff. The role also involves performance optimization, developing and improving physical design methodologies, and automating design flows.

Develops and validates board assembly process solutions for Intel's integrated circuit (IC) packages and sockets, focusing on Surface Mount Technology (SMT) processes. Responsibilities include designing and optimizing SMT processes, testing prototype boards, analyzing process data, and documenting procedures.

DFT Lead (Scan/ATPG) Engineer at Intel, responsible for driving DFT implementation for CPU designs in the latest process technology. Requires Master's or Bachelor's degree with significant experience in DFT, ATPG, fault models, memory BIST, IJTAG/TAP, RTL generation, verification, and post-silicon support.

Principal Engineer in SoC Design Verification at Intel, responsible for leading functional logic verification of integrated SoC designs, defining and developing verification plans, test benches, and environments, executing verification plans using emulation and system simulation, debugging presilicon issues, and collaborating with cross-functional teams. The role also involves mentoring technical leaders and ensuring security coverage.

Student role in Intel's Validation Engineering lab, assisting with engineering trials, testing, and maintenance of complex systems using test equipment, computers, and automation robots. Requires current Electrical/Computer Engineering studies and ability to work on-site.

This role is for a Clocking / Physical Design Engineer at Intel, focusing on the physical design implementation of CPU cores, including synthesis, place and route, floorplanning, clock tree synthesis, static timing analysis, and verification. The role requires a Bachelor's or Master's degree in a relevant STEM field with experience in backend design, scripting languages, and high-frequency clock distribution.

Senior Clock Architecture & Design Engineer role focused on developing clocking architecture for next-generation CPUs, involving the design of clock distribution networks, custom circuits, and optimization of clock tree synthesis flows. Requires experience in physical design, CTS, static timing analysis, and custom circuits.

This role is for a Quality Program Engineer in semiconductor manufacturing, focusing on ensuring quality, reliability, and audit readiness. Responsibilities include owning the internal audit program, facilitating quality meetings, driving root cause analysis and corrective actions, and analyzing yield/quality metrics to lead improvement initiatives. The role requires experience in semiconductor manufacturing, quality management systems, and leading quality programs with cross-functional teams.

Senior Yield Engineer at Intel focusing on semiconductor manufacturing, specifically substrate and advanced packaging. The role involves leading process development, performing advanced statistical analysis and data visualization, developing methods to analyze big data for yield modeling and defect understanding, and collaborating cross-functionally to resolve yield issues. It requires expertise in engineering analysis tools, data analysis techniques, scripting languages (Python), manufacturing process flows, and large-scale data analytics (JMP, SQL, Python).

Principal Analog Circuit Design Engineer with expertise in high-speed SerDes applications, focusing on design, development, and verification of analog circuits in advanced process nodes. The role involves floorplanning, circuit design, parameter extraction, simulation, test plan creation, and optimization for power, performance, area, timing, and yield. Requires strong foundational knowledge of analog design principles and hands-on experience with advanced FinFET CMOS processes and simulation tools. The principal engineer is expected to influence technical direction, mentor junior engineers, and drive technical strategy.

Principal Analog Circuit Design Engineer to lead the design and validation of cutting-edge analog circuits for high-speed (112G and 224G) SerDes applications. Requires expertise in PLL, CDR, CTLE, DFE, ADC, or TX design, and experience with advanced FinFET CMOS technologies. Role involves technical direction, mentorship, and cross-functional collaboration.

Intel is hiring a Post Silicon Validation Engineer in Haifa, Israel. This role involves developing validation architecture, test plans, methodologies, infrastructure, and content. The engineer will also perform deep dive investigations, advanced hardware/firmware/software debug, and bug fix definition for next-generation Intel processors. The position is for a College Grad and requires an on-site presence.

Intel is seeking a Senior Thermal Solutions Architect to lead end-to-end thermal solution co-engineering with OEM customers across desktop and notebook platforms. This role involves defining system-level thermal architectures to enable performance scaling, reliability, and product differentiation across Intel's client portfolio, influencing platform decisions from concept through manufacturing.

This role focuses on the end-to-end development of silicon packaging substrate design, including physical layout, routing, and optimization of package performance. It involves working closely with silicon and hardware teams, defining design rules, and resolving design rule violations. The position also requires documentation, customer interaction, and providing consultation on packaging problems.

Embedded OS Software Engineering Developer role focusing on Zephyr RTOS, involving design, development, testing, and optimization of operating systems, hardware abstraction layers, OS services, and user space software subsystems. Responsibilities include implementing virtualization, containerization, connectivity stacks, networking, power management, and performance optimization, while collaborating with open-source communities and leading software development processes.

Seeking a Principal Analog Design Engineer to lead the design and validation of high-speed analog circuits for SerDes applications. Requires expertise in analog/mixed-signal design, high-speed communication standards, and silicon bring-up. Will mentor junior engineers and collaborate with cross-functional teams.

Early-career FPGA Developer role focused on RTL design and verification (VHDL/Verilog/System Verilog) for a proprietary JTAG-based debug tool used in microprocessor and SoC bring-up and validation. Responsibilities include implementing FPGA RTL, assisting with integration, writing simulations, debugging RTL and hardware issues, and contributing to FPGA build flows. The role involves collaboration with software, validation, and hardware teams.

Software Application Development Engineer for Intel's Foundry Automation team, focusing on developing and implementing solutions for automated factories. The role involves partnering with end-users, gathering requirements, analyzing processes, managing projects, and providing L3 support in a 24/7 manufacturing environment. Requires PL/SQL and RDBMS schema design experience, with a strong emphasis on collaboration and technical problem-solving within manufacturing systems.

Software Performance Engineer role focused on optimizing application workloads through device driver enhancements, performance analysis, and optimization techniques. Requires strong C/C++ and Python skills, system-level programming, and understanding of computer architecture and compilers.

This internship focuses on the development and optimization of engineering tools like compilers, debuggers, profilers, and build systems to improve developer productivity and streamline workflows. The role involves collaborating with cross-functional teams to align tool capabilities with platform needs and solve complex technical challenges.

Lab Engineering Technician at Intel supporting the development of next-generation packaging technologies by preparing samples, executing experimental measurements, maintaining lab equipment, and helping develop new tools, fixtures, and test methods. This is a hands-on role in a dynamic R&D environment.

Senior Manager for U.S. Domestic Tax Compliance at Intel, responsible for leading complex tax work, ensuring accurate and timely execution of U.S. domestic tax compliance and filings, including partnerships and consolidated returns. Requires strong analytical skills, judgment, and end-to-end ownership.

Design and test complex mixed-signal system-on-chip (SoC) and FPGA solutions for quantum computer control electronics, interfacing with qubits and generating control signals. Requires expertise in RF/analog/mixed-signal circuit design, silicon prototyping, and signal integrity analysis.

Develops logic design, RTL coding, and simulation for CPU cell libraries, functional units, and IP blocks. Participates in architecture and microarchitecture definition, optimizes logic for power, performance, area, and timing, and reviews verification plans. Documents microarchitectural specs and supports SoC customers.

This role focuses on driving manufacturing excellence and yield improvements in semiconductor packaging through data-driven initiatives, advanced analytics, and model-based problem solving. The engineer will extract insights from manufacturing data, monitor yield performance, and communicate findings to shape manufacturing decisions.

Seeking a skilled SoC Security Validation Engineer with expertise in SoC architecture, OS fundamentals, CPU memory subsystems, and advanced security technologies like secure boot, trusted computing, and confidential computing. Responsibilities include leading security validation, developing threat models, designing penetration tests, validating security mechanisms, and developing automated test scripts using C, C++, and Python. Requires 7+ years of experience and strong programming skills.

Hardware Board Design Engineer with expertise in Power Delivery design and debug for Intel Core and Atom CPUs. Responsibilities include schematic capture, PCB design, power integrity simulation, board power-on and debugging, and customer technical support.

This role focuses on the functional verification of IP and subsystem logic for AI-accelerated systems within Intel's Data Center Group. The engineer will develop verification plans, test benches, and environments, execute these plans through simulation, and debug issues in the presilicon environment. Collaboration with architects, RTL developers, and physical design teams is key, as is maintaining and improving the verification infrastructure.

This role is for a System Modelling Engineer at Intel, focusing on the architecture, modeling, and performance analysis of 224Gbps SerDes IP. The engineer will develop end-to-end PHY system models, analyze electrical channels, optimize equalization algorithms, and perform clocking, jitter, and noise analysis. The role also involves supporting industry standards, defining test methodologies, and collaborating with cross-functional teams. The position requires a strong background in analog circuit design and high-speed design techniques.

Internship role focused on supporting the development and implementation of manufacturing processes for semiconductor modules, including equipment troubleshooting, maintenance, and optimization of process control. Requires a chemical science discipline and analytical skills.

This role involves the design, development, and verification of Mix Signal IPs, including proprietary Intel IPs, for Intel's client products. Responsibilities include collaborating with cross-functional teams, developing and executing simulations, debugging issues, creating technical documentation, and improving IP development processes. Requires a Bachelor's degree in a relevant field and proficiency in HDLs, digital design, simulation tools, and scripting languages.

This role focuses on the design, development, and verification of Intel proprietary IPs for client products, involving collaboration with cross-functional teams, documentation, simulation, testing, and automation. It requires proficiency in HDLs like Verilog/VHDL and scripting languages like Python.

Intel is seeking a Systems and Hardware Enabling Engineer to design and develop firmware for next-generation client platforms, interfacing directly with hardware components like microcode, FPGA, and IP-specific firmware. The role involves abstracting low-level hardware details, ensuring seamless integration, and optimizing performance and reliability. Responsibilities include firmware design, development, testing, validation, and collaboration with cross-functional teams, adhering to secure development lifecycle practices.

Supply Chain Engineer responsible for direct material issues in the ATM assembly test process, managing quality, new product introductions, cost reduction, and continuous improvement. The role involves defining inspection methodologies, optimizing the supply chain, and collaborating with suppliers. It also includes leading and mentoring junior engineers and contributing to future technology definitions.

Develops and optimizes RTL code for GPU IPs, ensuring alignment with architecture and microarchitecture specifications. Performs power, performance, area, and timing optimization, and executes unit-level verification. Collaborates with SoC customers for seamless integration.

Seeking a CPU Core Logic Designer to develop logic design, RTL coding, and simulation for CPU IP blocks. Responsibilities include defining architecture and microarchitecture features, optimizing logic for power, performance, area, and timing, and reviewing verification plans. The role requires experience with System Verilog/Verilog/VHDL, logic design, and computer architecture.

Manager for Process Integration Development Engineering within Intel's Fab Sort Manufacturing (FSM) organization, focusing on qualifying innovative integrated process solutions for advanced and mature node semiconductor technologies to meet quality, yield, and output targets. The role involves leading a team, collaborating with global development teams, developing yield analysis tools, and driving root cause analysis for yield and performance issues.

Seeking an IP Design Verification Engineer to ensure the functional integrity of intellectual property designs. Responsibilities include developing verification environments, executing test plans, debugging issues, and collaborating with cross-functional teams. The role also involves exploring and implementing AI/ML-driven verification techniques and custom automation scripts to improve efficiency.

Develops and implements test technology for advanced semiconductor packaging, focusing on high-mix, low-volume testing and future technologies. This role involves process integration, equipment solutions, feasibility studies, and modifications to improve efficiency and output, supporting Intel's advanced packaging roadmap for AI and edge computing.

This role focuses on the physical design and timing analysis of DDRPHY IP, ensuring high performance and low power consumption. Responsibilities include chip/block-level timing analysis, optimization, clock network design, and collaboration with various engineering teams. The role requires expertise in static timing analysis tools, clock design, and TCL scripting.

This role focuses on the functional validation of CPUs, ensuring performance, power, and area goals are met. Responsibilities include developing validation methodologies, executing test plans, performing silicon debug, and collaborating with various engineering teams throughout the product lifecycle. The role requires knowledge of CPU architecture, coding in C/C++ or Python, and experience with hardware/software validation tools.

Intel is seeking a CPU Validation Engineer to define, develop, and perform functional validation for CPUs, focusing on CPU internals and integration in system-level features. The role involves applying hardware and software tools, developing validation methodologies and test plans, executing these plans, and collaborating with other engineers for design optimization and troubleshooting. Responsibilities include silicon debug, root cause analysis, testing feature interactions, developing post-silicon validation infrastructure, publishing validation reports, and working with cross-functional teams (architecture, design, verification, board, platform, manufacturing) to improve debug and validation strategies. The engineer will also develop content to increase specific IP interactions and engage in all product life cycle phases, including bug hunting in simulation, emulation, and FPGAs.