Production Line Engineer responsible for managing shift loop operations to meet quality and output goals in a semiconductor fabrication environment. Key responsibilities include strategic WIP management, optimizing loop performance, coordinating maintenance, gathering tool status, documenting utilization gaps, and understanding root causes for missed goals. Requires strong analytical, communication, and problem-solving skills, with experience in manufacturing or semiconductor operations.

Mechanical Design Engineer responsible for designing Tape and Reel packaging, substrates, heat spreaders, and other mechanical components for semiconductor packaging and assembly. Requires CAD skills and collaboration with cross-functional teams.

This role involves characterizing semiconductor nano-devices using advanced transmission electron microscopy (TEM) to support technology development, process development, and process integration. The engineer will perform imaging and analysis using TEM, EELS, EDX, and 4D STEM, with a focus on improving time-to-information-return for critical manufacturing processes.

Drives technology development and enablement for semiconductor manufacturing, focusing on process integration, equipment solutions, and feasibility studies for new product designs. The role involves leading the design and development of manufacturing processes, including material selection, parameter optimization, and equipment metrology, with a strong emphasis on dry etch semiconductor manufacturing. Responsibilities include performing pathfinding activities, recommending modifications to operating equipment, partnering with suppliers, and conducting process technology feasibility studies. The role requires expertise in plasma etch fundamentals, statistical analysis, and DOE methodologies, with a demonstrated record of improving yield, reliability, performance, or manufacturability for advanced technology nodes.

Drives technology development and enablement for semiconductor manufacturing, focusing on process integration, equipment solutions, and feasibility studies. Leads design and development of manufacturing processes, including material selection, parameter optimization, and equipment metrology. Performs pathfinding activities for process and hardware development, enabling innovative device architectures and developing roadmaps. Recommends and implements modifications to operating equipment to improve production efficiency and output. Partners with suppliers for technology enablement. Requires PhD/Master's/Bachelor's in a semiconductor-related STEM field with relevant experience in dry etch semiconductor processing, plasma etch fundamentals, process development, optimization, and characterization. Proficiency in statistical data analysis and DOE tools is expected.

Module Process / Equipment Engineer at Intel Ireland supporting development and high-volume manufacturing of advanced semiconductor technologies. Responsibilities include ownership of module/equipment performance, qualification, monitoring, continuous improvement, preventative maintenance, troubleshooting, and partnering with cross-functional teams to solve technical challenges and improve operational performance. Requires a Bachelor's/Master's in Engineering/Science with 0-4 years of experience, strong interest in semiconductor manufacturing, and analytical/problem-solving skills.

Junior Design-for-Test (DFT) Engineer role focused on developing, integrating, and validating DFT solutions for CPU core designs, including ATPG generation, fault coverage analysis, and pattern debug. Responsibilities involve RTL-level DFT implementation, script development for automation, and collaboration with cross-functional teams for silicon bring-up and test flows.

Seeking a Modeling Development Engineer to join Intel's modeling engineering team, focusing on integrating and validating software for microcontroller firmware and hardware models within the semiconductor product development lifecycle. Requires strong C software engineering practices and experience with source control tools.

This role focuses on developing and manufacturing advanced semiconductor process technologies, including designing, executing, and analyzing experiments to meet engineering specifications. It involves integrating manufacturing steps, ramping to production volumes, and transferring technology to manufacturing counterparts. The role requires a Ph.D. in a relevant STEM field and significant semiconductor industry experience, with specific expertise in overlay development and understanding of modern semiconductor manufacturing processes.

Develops and executes lithography manufacturing processes for semiconductor devices, ensuring manufacturing viability and high-volume production. This role involves designing experiments, analyzing data, collaborating with partners and suppliers, and transferring technology to other factories.

This role focuses on the development and execution of lithography manufacturing processes for semiconductor devices. Responsibilities include designing and analyzing experiments, developing intellectual property, collaborating with equipment suppliers, installing and qualifying High Volume Manufacturing (HVM) capacity, and transferring technology to other Intel factories. It is an entry-level position requiring a Master's degree in a relevant science or engineering field and some experimental lab work.

Module Equipment Technician role at Intel focused on maintaining and optimizing manufacturing equipment for semiconductor fabrication, specifically in Dry Etch, Diffusion, and Thin Films processes. Responsibilities include equipment maintenance, repair, troubleshooting, and defect reduction. Requires STEM education or equivalent experience and strong problem-solving skills.

Physical Design Engineer for Core IP at Intel, responsible for the implementation of custom CPU designs from RTL to GDS, including synthesis, place and route, timing analysis, and verification. The role involves optimizing CPU designs for power, frequency, and area, and working with EDA vendors to enhance tool capabilities.

Internship role focused on Power Integrity/Delivery Electrical analysis for IC packages, involving extraction, analysis, and optimization of high-performance interfaces. Requires Masters/PhD in Electrical Engineering and experience with simulation tools.

Analog Circuit Design Engineer role at Intel, focusing on designing, developing, and optimizing high-performance analog circuits for advanced process nodes. Responsibilities include circuit design, simulation, verification, and collaboration with cross-functional teams. Requires expertise in high-speed analog circuit design and proficiency in EDA tools.

Senior Physical Design Engineer specializing in Static Timing Analysis (STA) for Intel's mixed-signal IPs. Responsibilities include timing analysis, optimization, constraint generation, timing rollups, and clock network development to meet performance, power, and functionality goals for next-generation client, server, and ASIC hard-IP portfolios.

This role focuses on the architecture of CPUs, specifically on improving methodologies and infrastructure for power and performance modeling, analysis, and workload bring-up for next-generation client products. The individual will research and drive ideas to enhance SoC power and performance modeling, collaborate with design teams, and analyze bottlenecks to propose solutions.

Performs functional verification of mixed signal logic components, including analog behavioral modeling, to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to mixed signal microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with digital and analog architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Requires BS/MS with 10+ years of experience in Design verification, System Verilog and OVM/UVM. Experience in validation flow, testbench architecture, verification closure, debug, coverage, simulations, and GLS is essential. Knowledge of DDRPHY validation, DFI/DDR/LPDDR protocols, Python/Perl scripting, Formal Property Verification, and Git is preferred. Exposure to AI tools like GitHub CoPilot is a plus.

Facility engineer role focused on project management for lab modifications and space projects, ensuring process and safety compliance, assisting with project filing, data management, and coordination. Requires construction management experience, technical knowledge of project management software, strong communication, attention to detail, multitasking, and basic financial concepts. Bachelor's degree required.

Senior Pre-Si Verification Engineer for Intel's E-Core CPU team, responsible for verifying new and existing features for next-generation CPU IP using simulation-based environments and formal verification. Requires expertise in hardware description languages, test bench development (System Verilog UVM/OVM), programming languages, and functional coverage analysis.

Student position in the UPW group focusing on system verification, maintenance, and monitoring of equipment in a semiconductor manufacturing facility. Requires a Practical Engineer degree and proficiency in Excel and Microsoft Office.

Network Security Engineer role focused on designing, architecting, and building secure classified network products for USG operations, requiring experience with load balancing, network security infrastructure, and hardening systems in accordance with federal guidance. Requires active Top Secret clearance.

This role focuses on designing, deploying, and managing Public Key Infrastructure (PKI) solutions, including certificate lifecycle management and automation. It involves collaboration with security, infrastructure, and DevOps teams, and ensuring compliance with internal and regulatory requirements. The position requires a Bachelor's or Master's degree in a relevant field and experience with PKI integration, X.509 certificates, and related standards.

Manufacturing Operators at Intel in Penang, Malaysia, are responsible for performing product manufacturing and assembly tasks, operating equipment, collecting and evaluating operating data, maintaining production efficiency, and ensuring quality control of raw materials and finished products. The role involves setting up and operating production equipment, supporting installation and training of new equipment, and collaborating with management to meet output requirements. Key responsibilities include operating machinery, monitoring production processes, assisting with material handling, maintaining work area cleanliness, meeting production targets, and participating in training.

Develops logic design, RTL coding, and simulation for IP blocks, optimizing for power, performance, area, and timing. Supports SoC customers and ensures quality integration and verification of IP blocks for full chip designs. Requires expertise in microarchitecture, high-speed designs, timing convergence, low-power techniques, and protocols like PCIe and CXL.

Construction Project Manager role at Intel, focusing on building semiconductor manufacturing factories. Responsibilities include planning and delivering projects from initiation to closeout, managing scope, schedules, budgets, contracting, EHS, and quality. Requires experience with project/construction management on major industrial facilities and large scope base build construction projects.

This role focuses on CPU validation and verification for next-generation Intel processor designs, involving developing test plans, creating test content and tools, and debugging silicon bugs. It requires proficiency in Python and scripting languages, and a strong understanding of CPU architecture and validation methodologies.

This role focuses on Static Timing Analysis (STA) for next-generation SoCs, ensuring optimal performance and efficiency. Responsibilities include performing timing analysis and optimization, generating and verifying timing constraints, resolving timing violations, conducting timing rollups, developing power-optimized clock networks, and defining methodologies for quality timing models. The role requires collaboration with various engineering teams to achieve clocking balance and power delivery optimization.

Intel's AI SoC organization is seeking an experienced SoC Subsystem Architect to lead the evaluation of architectural trade-offs, define and document micro-architecture for complex SoC IP blocks, and drive silicon bring-up and post-silicon validation for AI hardware. The role involves RTL design, integration, verification, timing constraints, and mentoring junior engineers.

Facilities Engineer focused on instrumentation and controls for industrial automation platforms (GE Cimplicity, Rockwell Automation Control Logix PLC) in a manufacturing/facility setting. Responsibilities include system design, maintenance, troubleshooting, project management, and ensuring operational efficiency and compliance.

This role focuses on designing, implementing, and enabling next-generation hardware design tools, flows, and methodologies for advanced technology nodes at Intel. The engineer will analyze and optimize methodologies for power, performance, area, and efficiency, build platforms and scripts for design automation, and collaborate with EDA vendors to test and adopt new tools. The role requires experience in EDA tools, physical design, digital design, and verification.

Operate and monitor production equipment, conduct maintenance, perform wafer production functions, optimize machinery settings, collaborate to meet targets, maintain logs, drive quality and cost improvements, conduct quality control, and support equipment installation and training.

This role focuses on the physical design of custom IP and SoC for high-performance computing applications, covering the full RTL-to-GDS flow. Responsibilities include synthesis, place-and-route, timing analysis, verification, and optimization using EDA tools, with a strong emphasis on scripting for automation and collaboration with cross-functional teams.

This role focuses on IP Design Verification, ensuring the functional correctness and reliability of intellectual property designs. Responsibilities include developing verification plans, designing test benches, simulating designs, debugging pre-silicon issues, and collaborating with architects and RTL developers. The role requires proficiency in SystemVerilog, experience with complex protocols, and scripting languages like Python or Perl.

Develops CAD software solutions for Intel's RTL Design and Validation teams, focusing on HW validation needs like RTL Coverage and UVM support. Responsibilities include developing flows, offering technical training, and providing hands-on assistance to validation engineers in areas such as Test-Bench development, regression management, coverage, failure analysis, and trace analysis.

This role focuses on quantum computing, specifically measuring and characterizing silicon spin qubits using cryogenic systems. It involves experimental design, data analysis, and collaboration to advance quantum processor technology.

This role is for an Ocotillo Technology Fabrication Shift Group Leader at Intel, responsible for managing technicians in a manufacturing environment. The role involves ensuring performance, development, and employee relations, creating roadmaps to meet goals in safety, quality, availability, velocity, affordability, and training. Responsibilities include supervising product teams, assessing personnel and material levels, assigning tasks, monitoring workflow, establishing operating policies, and ensuring overall safety. The ideal candidate will have strong leadership, communication, problem-solving skills, and a proven track record of delivering results through people in a high-performing team culture.

Electrical Validation Engineering Intern for Client IO team at Intel, focusing on validating high-speed and low-speed silicon interfaces. Responsibilities include hardware bring-up, lab testing, data analysis, and supporting automation framework development. Requires final-year Bachelor's or Master's in Electrical Engineering with Python/C++ experience.

Designs and implements physical layout and routing of silicon interposers and embedded bridges, collaborating with silicon, technology development, and hardware teams to optimize system-level design. Utilizes EDA tools for package layouts and analyzes design data to resolve checks for manufacturability.

Experienced Module Engineer for Ocotillo Technology Fabrication (OTF) at Intel in Phoenix, Arizona. This role focuses on defining roadmaps, establishing process flows, selecting materials and equipment, conducting experiments, driving process improvements, and transferring processes to high-volume manufacturing. Requires a strong background in semiconductor engineering and experience supporting manufacturing ramps and technology transfers.

RTL Design Engineer for Intel Unified Chassis, focusing on protocol bridges and IP components. Responsibilities include design, implementation, verification, and collaboration with architects and senior engineers. Requires expertise in RTL coding, digital design principles, and hardware description languages like Verilog or VHDL.

Accountant role focused on financial accuracy, compliance, and operational excellence within Intel's finance group. Responsibilities include preparing and analyzing financial records, supporting close processes, conducting financial data analysis, collaborating with auditors, ensuring internal controls (including SOX), and identifying process improvement/automation opportunities. Requires proficiency in ERP systems and US GAAP.

Senior Circuit Design Engineer for next-generation CPU programs, focusing on designing high-performance, low-power custom circuits meeting PPA targets. Responsibilities include circuit simulation, verification, optimization, and applying advanced CMOS technology.

Intel Foundry Services is seeking a Senior Physical Verification Application Engineer to provide technical support to customers on layout verification and parasitic extraction for advanced CMOS processes. The role involves resolving complex physical design challenges, developing technical content, leading verification methodology improvements, and engaging with customers. Requires experience with advanced CMOS processes, EDA tools for layout verification and parasitic extraction, and scripting languages. US Citizenship and ability to obtain security clearance are required.

Senior Design Engineer focused on developing logic design, RTL coding, and simulation for AI SoC development, integrating IP blocks, defining architecture, and optimizing for power, performance, and timing. The role involves collaboration with verification teams, driving silicon bring-up, and mentoring junior engineers.

Lead Senior Design Engineer for Intel's AI SoC organization, focusing on the development of logic design, RTL coding, simulation, and integration of IP blocks for AI hardware. The role involves defining architecture and microarchitecture, optimizing for power, performance, and timing, and driving silicon bring-up and validation. It requires strong engineering skills in ASIC/SoC development and leadership qualities.

IT Network Operation Engineer responsible for sustaining and operating mission-critical complex manufacturing network infrastructure supporting Intel Foundry environments. Focuses on operational execution, network stability, incident response, and problem analysis for Cisco networks (including ACI) in a 24x7 production environment.

Network Security Engineer role focused on designing, architecting, and building secure classified network products for USG operations, involving firewall configuration, network hardening, and security assessments.