NVIDIA
- HQ
- California, US
- Founded
- 1993
- Size
- 35,000+
- Website
- nvidia.com
NVIDIA currently has 496 active AI-related job listings. The majority of these roles, 52%, are focused on serving infrastructure, with agents representing another significant segment at 23%. Engineering is the dominant function, with 441 positions. The United States leads hiring geographies with 287 roles, followed by China with 64. Frequent tech tags include model_serving, inference_infra, and agent_orchestration, suggesting a focus on deployment and management of AI models. Over the last 30 days, NVIDIA posted 214 new AI roles, a 27% decrease compared to the previous 30-day period.
Currently tracking 440 active AI roles, down 50% versus the prior 4 weeks. Primary focus: Serve · Engineering. Salary range $100k–$575k (avg $262k).
NVIDIA currently has 487 active AI-related roles in our index. The most common open titles are: Deep Learning Performance Architect (4), Senior Deep Learning Performance Architect (4), AI Research Scientist (3), Developer Technology Engineer - AI (3), Manager, Deep Learning Algorithms (3). Most positions are in Engineering and Research.
NVIDIA's active AI hiring is concentrated in: serving infrastructure (54%), agents (21%), application (8%). These categories follow a seven-stage AI lifecycle: data, pre-training, post-training, serving infrastructure, agents, evaluation, and application.
NVIDIA is hiring AI talent in: United States (286 roles), China (59 roles), Israel (50 roles), Germany (21 roles).
Job postings at NVIDIA most frequently reference: model serving, inference infra, agent orchestration, llm observability, multimodal.
In the past 30 days, NVIDIA has posted 110 new AI-related roles. That is a -50% change versus the prior 30 days (218 → 110).
| Title | Stage | AI score |
|---|---|---|
| Principal Software Engineer – CSP Engagements Principal Software Engineer role at NVIDIA focused on Data Center Systems and Software CSP engagements, driving system software architecture, technical deep dives, and resolving complex customer issues for NPI projects. Requires extensive experience in scalable server systems, SW/HW interface, computer architecture, and low-level hardware/software interfaces. | — | 0 |
| Senior Firmware Engineer – CSP Engagements Senior Firmware Engineer role focused on system software for Datacenter products, involving embedded firmware development, customer engagement, hardware bring-up, protocol stacks, and debugging for NVIDIA's next-generation computing platforms. | — | 0 |
| Senior Software Engineer – Simulation and Virtualization Senior Software Engineer to contribute to architecting and developing a simulation platform for next-gen NVIDIA DGX platforms, integrating new HW features, and bringing up the full SW stack on the simulator. |
| — |
| 0 |
| Senior Systems Software Security Engineer – Data Center Systems Senior Systems Software Security Engineer focused on securing NVIDIA's Data Center Systems, with responsibilities including designing and implementing security features for AI Data Center systems, focusing on firmware, root of trust, and industry standards. | — | 0 |
| Senior ASIC Verification Engineer NVIDIA is seeking a Senior ASIC Verification Engineer to verify the design and implementation of SoCs and GPUs, impacting product lines from consumer graphics to self-driving cars and AI. The role involves defining verification scope, developing verification infrastructure, and collaborating with designers. Requires a Bachelors/Masters in EE/CS/CE, 4+ years of verification experience, knowledge of verification techniques (constrained random, scoreboard, functional coverage), SystemVerilog/UVM, and memory subsystem concepts. Experience with AI tools and workflow is a plus. | — | 0 |
| Senior ASIC Design Engineer Senior ASIC Design Engineer responsible for micro-architecture and digital design implementation of various innovative IPs for hardware security, clocking, voltage regulation, and silicon correlation. Collaborates with Architects, Circuit Designers, and Verification engineers to deliver next-generation solutions. Develops scalable RTL designs, executes synthesis, performs timing analysis, functional verification, CDC checks, and formal equivalence. Supports post-si bringup and debug activities, and develops tools and flows including Agentic AI flows. | — | 0 |
| Site Reliability Engineer - Hardware Infrastructure Site Reliability Engineer focused on hardware infrastructure, responsible for defining, developing, and supporting large-scale production systems with high efficiency and availability. The role involves incident management, root cause analysis, defining reliability metrics, and applying automation and Generative AI/Agentic solutions to improve operations. | — | 0 |
| Senior Software Engineer - Chip Simulation Develop and maintain simulation models for next-generation NVIDIA networking hardware features, build validation frameworks and test suites for InfiniBand and NVLink protocol implementations, create automation tools and CI/CD pipelines for regression testing and result analysis, design developer-friendly simulation environments that enable rapid iteration and debugging, and collaborate with hardware, firmware, and software teams to ensure accurate chip behavior modeling. | — | 0 |
| ATE Test Engineer NVIDIA is seeking an ATE Test Engineer to develop and implement ATE test program solutions for advanced chips, focusing on NV advanced chips. Responsibilities include ATE test method code development, debugging, scripting, and automation tool development. The role involves cross-functional collaboration with Product Development Engineering, DFT, and IC design teams to debug product failures and implement solutions. Experience with Advantest 93K ATE platform, Linux, C/C++/Java, and Perl/Python is essential. Familiarity with silicon verification, testing, manufacturing, Silicon Photonics, CPO, optical engines, high-speed IO, SRAM testing, 2.5D/MCM assembly, and DFT techniques is required. | — | 0 |
| Senior Tool and Test Development Engineer - DataCenter System Software Senior Tool and Test Development Engineer for DataCenter System Software at NVIDIA, focusing on designing, developing, and maintaining automated test frameworks and pipelines for server firmware and software. The role involves collaborating with cross-functional teams, executing tests, analyzing results, and supporting factory test processes. Experience with AI coding tools is mentioned as a plus. | — | 0 |
| Formal Verification Engineer NVIDIA is seeking a Formal Verification Engineer for their Networking team, focusing on pre-silicon design and verification of switch technologies using state-of-the-art formal verification tools and methodologies to ensure design correctness. | — | 0 |
| Senior Chip Design Verification Engineer NVIDIA is seeking a Senior Chip Design Verification Engineer to join their Networking Silicon Engineering team. The role involves planning and designing verification units for Switch silicon, GPU, and HCA, working closely with architecture, micro-architecture, and firmware teams. Requires 4+ years of experience in RTL verification, with knowledge in Specman, Verilog, and networking being advantageous. | — | 0 |
| Software Engineering Manager - GPU Communications Libraries Software Engineering Manager to lead a team developing GPU communication libraries (NCCL, NVSHMEM, UCX) for Deep Learning and HPC applications, focusing on performance and scalability. | — | 0 |
| Principal Firmware Engineer – Server Manageability and Observability NVIDIA is seeking a Principal Firmware Engineer to lead the end-to-end system software architecture for their data center systems, including firmware, kernel drivers, and operating systems. The role involves technical leadership, customer engagement, and strategic collaboration with hyperscalers to architect next-generation products. | — | 0 |
| ASIC Clocks Verification Engineer - New College Grad 2026 NVIDIA is seeking an ASIC Clocks Verification Engineer to join their GPU clocks group. The role involves verifying high-frequency clock structures, collaborating with design and verification teams, and debugging silicon bugs. Requires a Master's degree in Electrical Engineering, experience with SystemVerilog, UVM, Design Verification, Logic Design, Logic Synthesis, and scripting languages like Python or Perl. | — | 0 |
| Senior System Software Engineer - Tegra Tools Senior System Software Engineer at NVIDIA focused on building and optimizing software tools for flashing and provisioning NVIDIA chips and platforms across various product lines (Automotive, Embedded, Data Center). The role involves the full tools lifecycle, from pre-silicon development to post-silicon validation, and requires strong C/C++, Python, and low-level system understanding. | — | 0 |
| Senior Circuit Design Engineer NVIDIA is seeking a Senior Circuit Design Engineer to join their team, focusing on improving netlist and timing quality for processor designs. The role involves developing innovative digital, semi-custom, and mixed-signal analog circuits for silicon correlation and hardware security, collaborating with cross-functional teams, and creating prototypes. Requires BSEE or equivalent with 8+ years of circuit design experience, understanding of deep submicron processes, and hands-on simulation experience. | — | 0 |
| ASIC Verification Engineer NVIDIA is seeking an ASIC Verification Engineer to verify the design and implementation of SoCs and GPUs. The role involves defining verification scope, developing verification infrastructure, and collaborating with cross-functional teams. Requires a Bachelors/Masters degree in EE/CS/CE, 2+ years of experience, strong verification methodology knowledge, C++/SystemVerilog fluency, and familiarity with design/verification tools. | — | 0 |
| Senior Mask Design Engineer - Hardware Senior Mask Layout Design Engineer for chiplet interface projects, focusing on physical layout of mixed-signal functions using Cadence tools in advanced CMOS technologies. | — | 0 |
| Senior Systems Software Engineer - Rust, Go, C++ Senior Systems Software Engineer role at NVIDIA, focusing on designing, developing, and maintaining high-performance, rack-scale management solutions for datacenter environments. The role involves systems software development, hardware/firmware integration, distributed systems, and telemetry/health monitoring, primarily using Rust, Go, and C++. | — | 0 |
| Senior Software Engineer, Chip Simulation Infra Develop and maintain simulation infrastructure components for NVIDIA's high-performance networking chips and GPUs. This role involves defining, implementing, and validating simulations, optimizing CI/CD, and collaborating with hardware and software teams to simulate complex behaviors. | — | 0 |
| Formal Verification Engineer NVIDIA is seeking an experienced Formal Verification Engineer to work on CPU/GPU projects. The role involves crafting and optimizing formal verification flows, verifying micro-architectures using advanced formal techniques, and ensuring design correctness. Responsibilities include specifying and maintaining formal verification flows, developing automation scripts, reviewing setups, maintaining assertion libraries, identifying key verification behaviors, and debugging RTL. Requires a Bachelor's/Master's degree, 1+ years of experience in formal techniques, strong analytical and scripting skills, knowledge of CPU architectures and digital logic, and experience with HDLs like Verilog/System Verilog. | — | 0 |
| GPU Profiling Software Engineer Software Engineer role focused on developing and improving GPU profiling tools and libraries to help developers analyze and optimize application performance on NVIDIA GPUs. This involves working with low-level libraries, hardware specifications, and cross-disciplinary teams. | — | 0 |
| Senior Test Methodology Engineer Senior Test Methodology Engineer at NVIDIA, focusing on designing, developing, and implementing Automatic Test Equipment (ATE) testing methods for new IC products. Responsibilities include debugging and developing ATE test method code, scripting tools, and web-based tools, as well as solving production and throughput issues related to test methodology. Requires 5+ years of experience with ATE platforms like Advantest 93K and programming skills in C/C++ or Java. | — | 0 |
| Distinguished Engineer – Data Center System Software Architect NVIDIA is seeking a Distinguished Engineer to lead the end-to-end system software architecture for their data center products, including DGX and HGX platforms. This role involves deep expertise in firmware, kernel drivers, operating systems, and user mode drivers, with a focus on SW/HW interfaces and collaboration with hyperscalers and component leads. | — | 0 |
| Senior ASIC Verification Engineer, Coherent High Speed Interconnect Senior ASIC Verification Engineer responsible for verifying high-speed coherent interconnects for NVIDIA's mobile SoCs and GPUs, contributing to products ranging from consumer graphics to AI and self-driving cars. | — | 0 |
| Senior Package Layout Engineer - Hardware Senior Package Layout Engineer at NVIDIA focusing on the design and development of IC substrates for NVIDIA products, collaborating with design teams on schedules, costs, manufacturing, and electrical design issues. | — | 0 |
| Senior Software Development Engineer - CAD Infrastructure Senior Software Development Engineer role focused on architecting and developing CAD infrastructure tools using C++ and Python for semiconductor product development. The role involves collaborating with VLSI organizations and requires strong software engineering skills, with knowledge of GenAI, LLM, and AI Code Generation being a plus. | — | 0 |
| Senior Hardware Systems Engineer NVIDIA is seeking a Senior Hardware Systems Engineer to develop manufacturing test solutions for Datacenter products, leveraging HW and SW expertise in tester design and test automation. The role involves defining and implementing test solutions, investigating new test technologies, developing test strategies for new product features, reviewing DFT, and debugging complex hardware/software issues. Requires 8+ years of post-silicon validation experience, a degree in EE/CE or equivalent, proven experience in platform-level manufacturing test programs, datacenter platform familiarity, and proficiency in Python and Bash scripting. | — | 0 |
| Senior System Software Engineer, GeForce NOW Client Platforms Senior System Software Engineer role focused on developing and maintaining client applications for NVIDIA's GeForce NOW and NVIDIA App, involving cross-platform development (Windows, Mac, Linux, mobile) and full-stack engineering. The role requires strong C++ development skills, experience with real-time applications, and collaboration with distributed teams. | — | 0 |
| Senior ASIC Design Engineer – Clocks IP Senior ASIC Design Engineer role focused on designing and optimizing clocking networks for GPUs and CPUs at NVIDIA. Responsibilities include architecting clock domains, collaborating with cross-functional teams (front design, floor-planning, back end, SW, silicon solution), improving Power, Performance, and Area (PPA), and participating in the end-to-end ASIC execution cycle from micro-architecture to silicon bring-up. | — | 0 |
| Senior Power Integrity Engineer - LPU Packaging Senior Power Integrity Engineer for LPU Packaging at NVIDIA, focusing on designing and optimizing power delivery networks from die to rack level for GPUs, HBM, and high-speed SerDes. Requires extensive experience in PI, chip-package-board PDN design, simulation, and lab validation. | — | 0 |
| Senior Reliability Engineer - LPU Packaging Senior Reliability Engineer for LPU packaging at NVIDIA, focusing on package-level reliability specifications, qualification, materials selection, and data analysis for IC packaging and board-level reliability. | — | 0 |
| Senior ASIC Verification Engineer Senior ASIC Verification Engineer with extensive experience in Design Verification for clocking and reset logic in SOC and GPU ASICs. The role involves owning validation from start to finish, developing scalable solutions, and using industry-standard tools and methodologies. | — | 0 |
| Senior Memory Controller Verification Engineer Senior Verification Engineer for Tegra SoC Memory Subsystem IP verification at NVIDIA. Responsibilities include developing verification infrastructure, driving test plan execution, ensuring functional and performance correctness, and collaborating with FPGA and software teams. Requires 3+ years of ASIC verification experience with System Verilog and UVM. | — | 0 |
| Senior SOC Design Engineer NVIDIA is seeking a Senior SOC Design Engineer to join their SOC Design team. The role involves integrating advanced ASICs and collaborating with experts in various design fields to build cutting-edge GPUs and SOCs. Responsibilities include developing system-level methodologies, streamlining SOC design, ensuring RTL quality, and collaborating across teams. Requires 3+ years of chip design experience, expertise in RTL design, SOC integration, and automation, with proficiency in scripting languages. | — | 0 |
| Senior ASIC Verification Engineer Senior ASIC Verification Engineer role at NVIDIA, focusing on verifying and improving verification methodologies for system-level IPs. Requires expertise in System Verilog, UVM, Python, and RTL design. | — | 0 |
| Senior Cell Modeling and Verification Engineer NVIDIA is seeking a Senior Cell Modeling and Verification Engineer to develop behavioral models and verification for custom mixed-signal design cells used in NVIDIA's ASIC products. The role involves using Verilog, SystemVerilog, Perl, or Python, collaborating with cross-functional teams, and ensuring RTL meets design targets. | — | 0 |
| Senior Software Engineer, Hardware Tools and Methodology Development This role is for a Senior Software Engineer at NVIDIA, focusing on developing tools and methodologies for RTL generation in hardware design. The position requires strong C++ skills, understanding of ASIC design and Verilog RTL, and experience with automated workflows and algorithm improvement for RTL generation. While NVIDIA heavily utilizes AI, this specific role is in hardware tools development, not directly building AI models or systems. | — | 0 |
| Senior Hardware Systems Engineer - LPU Platform Pathfinding This role focuses on hardware systems engineering for NVIDIA's Language Processing Unit (LPU) platforms, which are designed to support demanding AI workloads. The engineer will drive hardware pathfinding, guide system-level technical decisions, and work across various teams (silicon, data center, cloud, manufacturing) to deliver production-ready systems. Responsibilities include full-stack system debug, owning interconnect and cooling architecture, and supporting program execution. The role requires broad system knowledge in electrical, mechanical, thermal, and firmware domains, with exposure to large-scale AI platforms. | — | 0 |
| Senior Design Engineer, Coherent High Speed Interconnect Senior Design Engineer role focused on the architecture and design of high-speed coherent interconnects (NVLINK-C2C) for NVIDIA's mobile SoCs and GPUs. This involves collaboration with various teams to deliver a class-leading interconnect solution that enables chiplet-based integrated products. | — | 0 |
| Senior Package Layout Engineer - Hardware Senior Package Layout Engineer at NVIDIA focusing on the design and development of IC substrates for NVIDIA products, collaborating with design teams on schedules, costs, manufacturing, and electrical design issues. | — | 0 |
| Senior I/O Subsystem Architect This role focuses on defining and architecting advanced chip interconnects and protocols, specifically for NVLink chip-to-chip communication. The responsibilities include researching and crafting architecture solutions, collaborating with various design and software teams, and driving the product lifecycle from concept through deployment. The role requires extensive experience in link layer architecture and existing interconnects. | — | 0 |
| Lead ATE Test Development Engineer - LPU NVIDIA is seeking a Lead ATE Test Development Engineer for their LPU team. This role involves defining, developing, and implementing ATE test programs for LPU products, working with overseas manufacturing teams to improve yields and reduce costs, and collaborating with cross-functional teams to debug failures and enhance reliability. The position requires a Bachelor's degree in Electrical/Computer Engineering, 12+ years of VLSI ATE testing experience, and proficiency with Advantest 93K ATE platform. | — | 0 |
| ASIC Verification Engineer NVIDIA is seeking an ASIC Verification Engineer to verify global IP across multiple products, including those related to AI. The role involves developing test plans, infrastructure, and automation flows, ensuring coverage, and collaborating with design teams. Requires BS/MS in Electrical or Computer Engineering, 2+ years of pre-silicon verification experience (UVM, SystemVerilog), ASIC design flow knowledge, and programming skills in Perl or Python. | — | 0 |
| Senior IP Verification Engineer NVIDIA is seeking a Senior IP Verification Engineer for their front-end multi-media IP team. The role involves developing and verifying multi-media IP designs using System Verilog and UVM, building testbenches, enhancing automation flows, and collaborating with design engineers and architects. Experience with HLS designs and AI-enabled IDEs is a plus. | — | 0 |
| SOC Design Engineer, ASIC Tools and Methodology Development This role focuses on developing and deploying in-house tools and workflows for SOC design and verification at NVIDIA. The engineer will manage tools for common design blocks, act as a DevOps engineer for automated RTL generation, and build new integration methodologies. Requires a Bachelor's/Master's in EE/CE, 3+ years of experience, Verilog, Python/Perl scripting, and Unix/Linux shell scripting. | — | 0 |
| Senior ASIC Verification Engineer Senior ASIC Verification Engineer role at NVIDIA, focusing on verifying global IP across various product lines including consumer graphics, self-driving cars, HPC, cloud computing, and AI. Responsibilities include developing test plans, verification infrastructure, and ensuring functional correctness and performance expectations are met. Requires 5+ years of experience in pre-silicon verification, ASIC design flow, and scripting languages like Perl or Python. | — | 0 |
| Senior ASIC Design Engineer - Hardware Senior ASIC Design Engineer focused on system-level IP, performance measurement methodologies, and RTL design for NVIDIA's GPUs and SOCs. | — | 0 |
| Senior Mask Design Engineer Senior Mask Layout Design Engineer to perform physical layout for mixed-signal functions in sub-micron CMOS technologies using Cadence tools. Responsibilities include floor planning, custom layout, verification against design rules and schematics, fill, post-processing, DRC mitigation, and foundry interactions. | — | 0 |